KR100257163B1 - Method and apparatus for locality control of symmetric multiprocessing system - Google Patents

Abstract

PURPOSE: A method and apparatus for controlling a locality of a symmetric multiprocessing system are provided to process a transaction generated in one processor node, and to prevent a degradation according to remote memory access to another processor node by improving a locality in each processor node using hardware. CONSTITUTION: In case that a transaction generated from one processor among a plurality of processors is driven to a local bus, and cache memories of the rest processors are referred through the first local bus by a cache miss generated from the first processor. In case that the cache miss is generated from each processor, a bus transaction control unit senses the cache miss, and judges whether relevant data are existed in the first shared memory or a local memory.

Description

The method and apparatus for locality control of symmetric multi-processing system

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a medium-to-large computer of symmetric multi-processing (hereinafter, abbreviated as "SMP"), which is a distributed shared memory structure, and more particularly, to another node in an SMP computer system. The present invention relates to a method and apparatus for controlling locality of an SMP system that implements and controls local memory in hardware so as to minimize remote memory access referring to memory.

In general, as shown in FIG. 1, the SMP system has a plurality of processors 11 to 13 including a CPU and a cache memory connected to an interconnection bus, and share data through the interconnection bus. The shared memory 14 is connected to the interconnection bus.

The single bus-based SMP system configured as described above has a cache memory in each processor 11 to 13 to maintain data consistency on the interconnect bus by hardware, so that the software is highly portable, easy to program, and simply a processor device. The performance increase effect by the expansion of is large.

In addition, since the nodes of the shared memory 14 are concentrated in one place, when the shared memory 14 is accessed by each of the processors 11 to 13, a latency time is constant. Therefore, such a structure is called a uniform memory access (UMA) structure.

However, such an SMP system has a problem in scalability of the system. In other words, because hundreds of signals are transmitted on the interconnect bus and it becomes faster, the physical and electrical limitations of the signal transmission and the number of processors that can be connected to it because of the collision of bus transactions on the interconnect bus are limited. there was.

Accordingly, in order to improve such scalability, an SMP system having a distributed shared memory structure is constructed as shown in FIG. 2.

The SMP system having a distributed shared memory structure as described above connects a plurality of processors to a local bus, processes transactions driven on the local bus, and includes first and second processor nodes 20 having separate shared memories. 30; It consists of an interconnection bus that connects the first and second processor nodes 20 and 30 to exchange data with each other.

In the SMP system of the conventional distributed shared memory structure configured as described above, since the first and second shared memories 26 and 36 are distributed to each processor node 20 and 30, the SMP system is driven on a local bus in a predetermined processor. In order to process one transaction, the data needs to access the memory of its own processor node, and if it does not exist in the memory of its own processor node, it must access the memory of another processor node.

For example, if desired data exists in the first memory 26 under the control of the first bus transaction control unit 25 to process a transaction driven by a predetermined processor present in the first processor node 20, this may be the case. Access to the processor. However, when the requested data exists in the second memory 26 of the second processor node 30, the requested data may be remotely accessed through the interconnection bus under the control of the first bus transaction control unit 25. Patches from the second memory 26 to provide to the processor.

In this case, when each processor accesses the memory of its processor node, the delay time is short, and when the memory of another processor node needs to be accessed, a relatively long delay time is required.

That is, since the delay time is not constant when the processor accesses the memory, such a structure is called a non-uniform memory access (hereinafter, abbreviated as "NUMA") structure. Among these NUMA structures, a structure that maintains data consistency on the interconnect bus by hardware is called a cache coherent NUMA (hereinafter, abbreviated as "ccNUMA") structure.

Systems implemented with such a ccNUMA structure are based on a single node unit in which processors and memory are installed. In these nodes, a plurality of SMP processors within a certain range are installed. It is connected by interconnection bus. In addition, to compensate for the determinism of the multi-processor system of the SMP structure as shown in FIG. 1, that is, to connect a plurality of nodes, a SC (Scalable Coherent Interconnect: hereinafter abbreviated as "SCI") bus, crossbar A new interconnect bus is used, such as a crossbar switching bus.

However, in a distributed shared memory system, it is best to exchange data in the cache memory of each processor in its processor node. If a cache miss occurs from each processor, the memory loaded in the processor node may be changed. Approach If there is no data in the memory of its processor node, it should refer to the data of another processor node.

However, in the SMP system of the distributed shared memory structure according to the related art, when the memory area of another processor node needs to be accessed in order to process a transaction generated by a given processor, in particular, access to such another processor node is not possible. As the frequency increases, system performance deteriorates.

Therefore, there is a problem in that the hardware implementation is very complicated in order to minimize the access to the interconnection bus of the processor node by mounting a large external cache memory to improve the above problem.

In addition, there is a software solution to implement the characteristics such that process scheduling or memory allocation can occur in an adjacent processor or memory in order to improve the above problems, but the implementation method It is very complicated and has a high difficulty.

Accordingly, the present invention seeks to improve the above-mentioned problems of the prior art by hardware improvement of locality within each processor node, thereby processing more transactions generated within one processor node of a distributed shared memory structure, and thus the other. An object of the present invention is to provide a method and apparatus for controlling locality of an SMP system that prevents performance degradation due to remote memory access to a processor node.

1 is a block diagram of a conventional single bus multi-processing system,

2 is a block diagram of an apparatus for controlling locality of a symmetric multiprocessing system according to the present invention;

FIG. 3 is a detailed block diagram of the locality controller of FIG. 2;

4 is a flowchart of a locality control process of a symmetric multiprocessing system according to the present invention.

<Description of the code | symbol about the principal part of drawing>

100, 200: first and second nodes

101 to 104, 201 to 204: first to eighth processors

110, 210: first and second bus transaction control unit

111, 211: first and second shared memory

120, 220: first and second locality control unit 121: first tag address queue 122, 124: second, third tag address storage unit

123 and 125: first and second comparators 126: control unit

127: index address storage unit 128: index address counter

129: local memory

301 and 302: first and second input / output bus bridges

The locality control method of the SMP system for achieving the above object of the present invention, when access to the memory of the other node to supply the data corresponding to the transaction occurred on the local bus of the multi-processor system of the distributed shared memory structure, Detecting a number of times the same address accesses the memory of another node during the time period; A second process of storing burst data of the driven address area from a memory of another node to a local memory of its own node when the frequency of access to the other node is more than a predetermined number of times; When the data corresponding to the address driven on the local bus is present in the local memory, the third process of providing the data to the processor.

In this case, when the first process needs to refer to the memory of the remote node in order to process a transaction generated by a given processor, the first process monitors the relevant address of the transaction and determines whether the access frequency of the remote node to another address is currently measured. Judging; Storing the currently driven address for comparison with a later driven address after the measurement of the frequency of access to the remote node for the other address is complete; Storing the currently driven address and comparing it with a previously driven address if the access frequency to the remote node is not being measured; Counting the number of times according to a match state as a result of the comparison; And determining whether the number of matches is a set number or more.

Locality control apparatus of a symmetric multiprocessing system for achieving the object of the present invention is a bus transaction control means for controlling the memory access of the address to process transactions generated on the local bus connecting multiple processors, the bus transaction control means When a memory access to a remote node occurs through a plurality of times, as the same address occurs more than a set number of times within a predetermined time, a plurality of locality control means for storing a certain amount of data of the corresponding address area in the local memory of its node A node; And an interconnection bus for interconnecting each node to share an input / output bus and for transmitting an address and data to each other under the control of the bus transaction control means.

Here, the locality control means included in each node includes a first tag address storage unit for storing a corresponding tag address when a bus transaction from a bus transaction control means to a remote node occurs; A second tag address storage unit for storing an address stored in the first tag address storage unit to measure the number of transactions to a remote node; A first comparator that compares an address stored in the second tag address storage with an address of a subsequent generated transaction and equally measures a transaction frequency to a remote node within a predetermined time; A third tag address storage unit for storing a corresponding tag address when a request is made to the remote node more than a predetermined number of times within a predetermined time as a result of the comparison of the first comparator; A second comparator for detecting whether a transaction of the same address as the tag address stored in the third tag address storage is driven; Control means for controlling the comparison unit and each storage means; A local memory for storing the data from a memory of a remote node in which data corresponding to a tag address area stored in the third tag address storage unit is stored; An index address storage section for storing an index address portion of an address snooped by the bus transaction control means; And an index address counter that generates an index address as data is stored in the local memory.

When described in detail with reference to the accompanying drawings a preferred embodiment of the present invention made as follows.

FIG. 3 is a schematic block diagram of an apparatus for controlling locality of a symmetric multiprocessing system according to an exemplary embodiment of the present invention. As shown in FIG. 3, the first and second processor groups 101 connected to the first and second local buses, respectively, are shown in FIG. 104) 201 to 204; First and second bus transaction controllers (BTCs) 110 and 210 for controlling memory accesses of corresponding addresses to process transactions generated through the local buses; Under the control of the first and second bus transaction controllers 110 and 210, a data read or write operation is performed in response to requests from the respective processors 101 to 104, 201 to 204, and other nodes. First and second shared memories 111 and 211; When a memory access to a remote node occurs through the first and second bus transaction controllers 110 and 210, as the same address occurs more than a set number of times within a predetermined time, constant data of the corresponding address area is generated. The first and second nodes 100 and 200 are configured to include first and second locality controllers 120 and 220 to be stored in a local memory of the first and second nodes 100 and 200. Are connected to each other, and the input / output buses 301 and 302 are shared, and the bus and the bus transaction control unit 110 and 210 are controlled by the interconnect bus.

In this case, the first and second locality controllers 120 and 220 monitor the corresponding tag address when a bus transaction from the bus transaction controller 110 and 210 to another node occurs as shown in FIG. 4. A first tag address queue (Tag Address Queue [31: 13]) 121 for storing Address 1; A second tag address store (Tag Address Store [31:13]) 122 which stores the address stored in the first tag address queue 121 to measure the number of transactions to a remote node; The first comparison unit 123 which compares an address stored in the second tag address storage unit 122 with an address of a later generated transaction (Monitoring Address2) and measures a transaction frequency to a remote node within a predetermined time when it is the same. Wow; A third tag address storage unit 124 for storing a corresponding tag address when a request is made to the remote node more than a predetermined number of times within a predetermined time as a result of the comparison of the first comparison unit 123; A second comparison unit (125) for detecting whether a transaction (Snooping Address) of the same address as the tag address stored in the third tag address storage unit (124) is driven; A control unit (Main Locality Controller) 126 for controlling the comparison units 122 and 125 and the storage units 121, 122, and 124; A local memory (DATA RAM) 129 for reading and storing the data from a shared memory of another node in which data corresponding to a tag address area stored in the third tag address storage unit 124 is stored; An index address storage unit (127) for storing an index address portion of an address snooped by the bus transaction control unit (110) (210); An index address counter 128 that generates an index address as data is stored in the local memory 129 is configured.

In addition, the local memory 129 is composed of a small capacity high speed memory.

The operation of the present invention configured as described above will be described in more detail with reference to FIGS. 2 to 5.

First, when the transaction generated in one of a plurality of processors is driven on the local bus, for example, a cache miss generated in the first processor 101 may cause a different processor 102 to be executed through the first local bus. The desired data is fetched with reference to the cache memory of ˜104). However, when a cache miss occurs in each of the processors 102 to 104, the bus transaction controller 110 detects this and determines whether the corresponding data exists in the first shared memory 111 or the local memory 129.

If the requested data exists in the first shared memory 111, the corresponding data may be provided to the first processor 101. In addition, if desired data exists in the local memory 129 in the locality control unit 120 according to the case (when the address of a transaction driven on the local bus is the shared memory address of the second node 200), the corresponding data is removed. 1 may be provided to the processor 101.

However, if it does not exist in the first shared memory 129 or the local memory 129, the shared memory 211 of the second node 200 is referred to through the interconnection bus.

Such a memory reference of the second node 200 will be described in more detail with reference to FIG. 5 as follows.

When it is necessary to refer to the shared memory 210 of the second node in order to process a transaction generated in the first local bus, the corresponding address is shared by the second node 200 under the control of the first bus transaction controller 110. It is driven to an interconnect bus for reference to the memory 210.

In this case, the first locality controller 120 acquires a remotely requested address. The address thus obtained is determined by the first locality controller 120 to measure a matching counting of the same tag address to the second node within a predetermined time to determine whether the address is a predetermined number or more. At this time, when measurement of the access frequency to the second node 200 is already performed, another address is stored in the first tag address queue 121.

As described above, when the bus transaction controller 110 stores the address for referring to the shared memory 211 of the second node 200 in the first tag address queue 121, whether the match count is over, that is, the previous count is completed. It is determined whether the match count is completed, and if it is completed, the first address entered in the first tag address queue 121 is stored in the first tag address storage 122, otherwise, the first tag address queue 121 is not included. Discards the first address entered.

If the match counting is not currently performed, the tag of the related address is stored in the second tag address storage 122. The tag address stored as described above is compared with a bus transaction address to a remote node which is sequentially generated in the first comparator 123.

On the other hand, when match counting of the address currently driven by the first comparator 123 is in progress, the corresponding address is compared with a previously stored tag address to determine whether there is a match. If there is a match, it is determined whether the match counter is set, that is, how many times the frequency of occurrence of the same tag address occurs within a predetermined time.

If the same frequency of occurrence of the same tag address does not occur more than the set number of times within a predetermined time and ends when the set match time passes. However, when the frequency of occurrence of the same tag address within a predetermined time is more than the set number of times, the match count is set, and the bus transaction controller 110 is requested to pause the local bus in the first node 100, and the second 4 KB of data is read from the second shared memory 211 of the node 200 at one time and written to the first local memory 129 of the first node 100. After the writing is finished, the bus transaction controller 110 is notified to operate the first local bus in the first node 100 again.

As such, the data stored in the first local memory 129 may provide data at a request of the bus transaction controller 110 later. That is, the controller 126 compares the tag address stored in the third tag address storage unit 124 with the snooping address by the bus transaction controller 110 in the second comparison unit 125. The corresponding data stored in the first local memory 129 is provided to the requesting processor. In this case, the index address storage unit 127 stores the index address portion of the snooping address to facilitate retrieval of data stored in the first local memory 129 using the stored index address.

The index address counter 128 generates an index address when data is read from the second shared memory 211 of the second node and stored in the first local memory 129.

As described above, the present invention measures the frequency of referencing to a remote node of an address in order to process a transaction generated on a local bus, and when the frequency is a predetermined number of times for a predetermined time, the data of the address is taken from the remote node's memory and stored. Then, by implementing a locality control device including local memory provided at the request of the bus transaction control unit, it is possible to reduce the delay time for transaction processing as well as to implement the hardware when accessing the memory to a remote node. This has an easy effect.

Claims (8)

When accessing the memory of another node to supply the data corresponding to the transaction occurred on the local bus of the multi-processor system of the distributed shared memory structure, the number of times that the same address accesses the memory of the other node for a certain time is detected. 1 course; A second step of storing burst data of the driven address area from a memory of another node to a local memory of its own node when the frequency of access to the other node is more than a predetermined number of times; And a third process of providing the data to a corresponding processor when data corresponding to an address driven on the local bus exists in the local memory. 2. The method of claim 1, wherein the first step monitors the associated address of the transaction and, if it is necessary to refer to the memory of the remote node to process a transaction originating from a given processor, and to the remote node for a different address now. Determining whether an access frequency is being measured; Storing the currently driven address for comparison with a later driven address after the measurement of the frequency of access to the remote node for the other address is complete; Storing the currently driven address and comparing it with a previously driven address if the access frequency to the remote node is not being measured; Counting the number of times according to a match state as a result of the comparison; And determining whether the number of matches is greater than or equal to a predetermined number of times. The method of claim 1, wherein the second process stops a transaction currently occurring in the local bus of its own node when the frequency of access to the other node is greater than or equal to a predetermined number of times, and then enters the memory of the other node more than the set number of times. Reading and storing related data of an accessed address from a memory of a remote node; And normal operation of the transaction generated in the local bus after completing the storage in the local memory of the node from the remote node. The method of claim 1, wherein the third process stores an index address portion of a corresponding address when an address of a transaction generated by snooping a local bus does not exist in its node, and compares the address with a tag address stored in a local memory. Making a step; And if there is a matching tag address as a result of the comparison, supplying corresponding data from the local memory. Bus transaction control means for controlling memory access of a corresponding address to process transactions generated on a local bus connecting multiple processors, and when the memory access to a remote node occurs through the bus transaction control means, the same address is set for a predetermined time. A plurality of nodes including locality control means for storing data of a predetermined size of a corresponding address area in a local memory of its own node as the number of times set within the same number of times occurs; Locality of a symmetric multiprocessing system comprising an interconnection bus for interconnecting each node to share an input / output bus, and transmitting address and data to each other under the control of the bus transaction control means. Control unit. 6. The system of claim 5, wherein the bus transaction control means included in each node mediates snooping the local bus, controls memory access requests from its own nodes, and controls memory accesses from processors and input / output devices of remote nodes. And controlling the history of the memory and controlling access to the memory and the input / output devices of the remote node when referring to the memory of the remote node. 6. The system of claim 5, wherein the locality control means included in each node comprises: a first tag address storage unit for storing a corresponding tag address when a bus transaction from a bus transaction control means to a remote node occurs; A second tag address storage unit for storing an address stored in the first tag address storage unit to measure the number of transactions to a remote node; A first comparator that compares an address stored in the second tag address storage with an address of a subsequent generated transaction and equally measures a transaction frequency to a remote node within a predetermined time; A third tag address storage unit for storing a corresponding tag address when a request is made to the remote node more than a predetermined number of times within a predetermined time as a result of the comparison of the first comparator; A second comparator for detecting whether a transaction of the same address as the tag address stored in the third tag address storage is driven; Control means for controlling the comparison unit and each storage means; A local memory for storing the data from a memory of a remote node in which data corresponding to a tag address area stored in the third tag address storage unit is stored; An index address storage section for storing an index address portion of an address snooped by the bus transaction control means; And an index address counter which generates an index address as data is stored in the local memory. 6. The symmetric multiprocessing system of claim 5, wherein the interconnection bus is comprised of a local bus having an input / output bus bridge connected and having the same protocol as a local bus connecting the processor to connect each node. Locality control.

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