KR100257147B1 - Fail cell test method of semiconductor device - Google Patents

Abstract

PURPOSE: A failed cell test method of a semiconductor element is provided to reduce the test time by retesting only spare cells which replaces the failed cells. CONSTITUTION: Failed cell test is performed for each cell(ST1). When there occurs a failed cell(ST2), it is determined where they it can be replaced with a spare cell(ST3). If the replacement is possible, the failed cell is stored(ST4) as a column and row address. The repair process, which replaces failed cells with spare cells, is processed by cutting the fuse designed in the semiconductor chip. Then, the test is performed only for the replaced spare cells. If the test result of the spare cells is good, the semiconductor chip is judged to be satisfactory.

Description

Method for testing fail cell of semiconductor device

FIG. 1 is a flow chart illustrating a first test method in a fail cell test method of a semiconductor device according to an embodiment of the present invention; FIG.

FIG. 2 is a diagram illustrating a method of testing a fail cell of a semiconductor device according to an embodiment of the present invention. FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

B: Spare row address cell C: Spare column address cell

[Object of the invention]

[TECHNICAL FIELD]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to testing semiconductor devices, and more particularly, to a fail cell testing method of a semiconductor device that replaces a spare cell as an object to be replaced at the time of fail.

BACKGROUND ART [0002]

Spare cells formed on each chip on which a semiconductor element is formed are limited to the size of the entire chip and have approximately 1 to 2% of the total number of the chips of the chip. Therefore, as a result of the cell test, after the failure cell is replaced with the spare cell, the cell is re-tested to determine whether the chip operates normally.

The conventional test method has a problem that unnecessary test time is wasted because the test cell of 98 to 99%, which is good in the first test, is also tested in addition to the maximum spare cell capacity of 1 to 2% in the retest.

[PROBLEMS TO BE OBTAINED BY THE INVENTION]

Therefore, it is an object of the present invention to provide a fail-cell test method of a semiconductor device capable of reducing test time by excluding cells determined as good during the primary fail test after replacement with a spare cell.

According to the present invention, a test method comprises the steps of: examining a cell's fail to replace a failed cell with a spare cell, and storing the failed column and row address cells into a file; And testing only the stored spare cell.

[Configuration and operation of the present invention]

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a flowchart illustrating a process of creating a file for storing fail address information for replacing a failed cell with a spare cell according to an embodiment of the present invention.

In this method, if a failed cell is generated while a test is performed for each cell, it is determined whether it is replaceable by a spare cell, and if possible, a fail address is stored.

FIG. 2 is an example for explaining the fail address storing operation in the third step (ST3) of FIG. 1 for one megadream, where the horizontal axis is the failed column address and the vertical axis is the failed row address.

In the case of 1 megadamir, there are 1024 columns from 0 to 1023 and 1024 row address cells from 0 to 1023, assuming that the failed column addresses are 100, 200, 300, 400, and the failed row address is 10 , 20, 30, and 40, respectively.

As shown in the figure, the four lines B of the failed row address and the four lines C of the column address are replaced with four rows and four columns of each row spare, Can be switched to good products.

In the first step of the method of the present invention, the fail address is stored in a predetermined file. Here, assuming that the file name is A, the files corresponding to the file name A are shown in Table 1.

[Table 1]

Next, a repair operation for replacing a failed cell with a spare cell is performed using the information stored in the above step. The repair work is performed by cutting the fuse designed in the semiconductor chip.

Then, in the above step, a spare cell is substituted for the address, and a secondary test is performed to determine whether the entire chip is converted into a good product.

The second test is obtained by opening file A which holds eight lines of fail addresses identified in the first test, and only the spare cells in this part are tested.

[Effects of the Invention]

As described above, the present invention can significantly reduce the test time by re-testing spare cells that have been replaced using the information on the failed cell after a repair operation in which the failed cell is replaced with a spare cell.

That is, in the case of 1 megadiram, 1048576 (= 1024 × 1024) cells must be tested in the conventional method. However, according to the method of the present invention, only 8192 {= (4 × 1024 + (4 × 1024) , It is possible to obtain a reduction in test time of up to 99% as in the following calculation.

Although specific embodiments of the present invention have been described and illustrated herein, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Therefore, the following claims are to be understood as including all modifications and variations as fall within the true spirit and scope of the present invention.

Claims (1)

Inspecting a cell's failing to replace a failed cell with a spare cell, and storing the failed column and row address cells into a file; Testing only the stored spare cells. ≪ Desc / Clms Page number 17 >