KR100256563B1 - Method for operating dual port ram - Google Patents

Abstract

PURPOSE: A method for operating a dual port RAM is provided to prevent a memory shortage of a DPRAM possibly occurring in communicating with the DPRAM between an HIT communication processor and a main processor, use the DPRAM effectively and reduce a unit cost by operating the DPRAM with reduced capacity and error generation rate. CONSTITUTION: It is determined whether a flag has been set(302). If a flat has not been set, it is determined whether a length of a message to be written in a cell is the smaller than or the same as 64Kbyte(304). If the length is greater than 64Kbyte, the required number of cells computed from the length of the message, the computed integer value is set as a count, and a computed value is taken and set as a dummy(306). It is determined whether a flag has been set in even one of the number of cells counted from the cells in which a data of a DPRAM is desired to be written(308). If there is no cell for which a flag has been set, a head is added to 64byte corresponding to the message to write the message in the corresponding cell in which the data is to be written, and1 is subtracted from the count value and set as a count value(310). It is determined whether the count value is 0 (312). If the count value is not 0, it is determined whether the corresponding cell in which the data of the DPRAM is to be written is the final cell(314). If the current cell is not the final cell, it moved to the next cell(316). If the cell in which the message has been currently recorded is not the final cell, it moves to the first cell(318). It is determined whether a dummy value exists in the head of the moved DPRAM cell(320). If there is no dummy value, 72byte, the next part of the message is moved to the current cell(322). If there is a dummy value(320), it is determined whether a count value is 1 (324). If the count value is 1 , it is recorded in the cell in which a data is currently desired to be written as many as the final dummy of the message(326). If the count value is not 1 (324), 72 byte, the next part of the message, is recorded in the current cell(328). After 1 is subtracted from the count value and the subtracted value is set as a count value(330). If the count value is 0 (312), a flag is set in the first cell(332). If the length of the input message is smaller than or the same as 64 byte(304), a data including head information and a message information in the current cell and a flag of the cell is set(334). It is determined whether the cell of the DPRAM is the final cell(336). If the current cell is not the final cell, it moves to the next cell and returns to the first procedure(338).

Description

How to operate dual port RAM

The present invention relates to a method of operating dual port RAM (abbreviated as DPRAM), and in particular, a large amount of messages can be processed with a small DPRAM by using a DPRAM used for bidirectional communication matching. It relates to the operation of the DPRAM.

As is well known in the art, in the development of electronic switchboards, DPRAM is used for various types of communication, such as communication between processor and processor, or high-level data link control (HDIT) interface time_slot (HIT) bus communication between processors. The main focus is to ensure that the communication is dedicated independently.

For example, in the lower processor of the TDX-100 switch (hereinafter abbreviated as TP), the MC680MH acts as the main CPU and the MC68MH360 is used for the HIT bus communication. I'm using a dog.

The size of DPRAM used in the TDX-100 exchange is 64Kbytes. Since the maximum message size required for HIT bus communication is 500 bytes, 508 bytes including the head of the communication message is the size of the buffer needed to process one message.

Therefore, the TP in the prior art should be able to communicate with up to 64 devices at the same time, and one device should communicate with the TP with only one buffer on average. That is, one buffer must be cleared, but the next message can be delivered. As a buffer that allocates a large send buffer and a receive buffer to DPRAM in a conventional manner, there is a large amount of DPRAM in the communication message processing between the TP and the device. There is a drawback that the communication between processors can fail because the volume of messages cannot be accommodated.

Disclosure of Invention The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a method for operating a communication DPRAM having a small capacity and a low error rate of DPRAM resources used for bidirectional communication matching. .

In order to achieve the above object, the present invention, the main processor responsible for the control of the processor in the processor, and the role of the transmission and reception matching of communication messages between the main processor and each HIT communication processor and functions such as command processing and status transfer In an interprocessor communication system including a DPRAM to receive and communication data, and each HIT communication processor capable of reading and writing data, it is determined whether a flag is set in a cell of a DPRAM to write a current message. If it is determined that the flag of the DPRAM cell to which the current message is to be written is not set in the first determination step and the first determination step, the length of the message to be written in the corresponding cell is smaller than the preset message length. The second judgment step of judging whether or not the same or the same, and the path of the message input Is determined to be smaller than or equal to the preset message length, writing data including the head information and the message information to the current cell, setting a flag of the cell, and determining whether the cell of the DPRAM is the last cell. And if it is determined in the third determination step that the current cell is not the last cell, moving to the next cell; and if it is determined in the third determination step that the cell for which the current message is recorded is the last cell, the first cell of the DPRAM is determined. It provides a method of operating a DPRAM comprising the step of moving to a cell.

1 is a block diagram illustrating an embodiment of operating a DPRAM according to the present invention;

2 is a data structure diagram showing a format for dividing data in DPRAM according to the present invention;

3 is a flow chart illustrating the steps of writing a message to a DPRAM in a processor in accordance with the present invention.

4 is a flowchart illustrating steps of reading a message of a DPRAM in a processor according to the present invention.

<Description of the code | symbol about the principal part of drawing>

10: upper processor 12: lower processor

13: HIT bus communication unit 120: main processor

121: bus 122: communication processor

124: first ROM 126: first RAM

128: DPRAM 130: master HIT communication bus

132: second ROM 134: second RAM

136, 138, 140: first, second, third slave HIT communication processor

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings.

Referring to the configuration of the present invention with reference to Figure 1, the TP 12 for controlling a plurality of devices, the main processor 120 in charge of the control of the TP 12 in the TP 12, the upper processor, The bus 121 responsible for transferring addresses, data, system data, etc. between the main processor 120, the communication processor 122, the first ROM 124, the first RAM 126, and the DPRAM 128, and the above. A communication processor 122 for controlling communication with the device, a first ROM 124 for allowing the TP 12 to be loaded normally with mounting information and other system information for loading a program in the TP 12, A first RAM 126 capable of writing and reading data required by the above-described communication processor 122 and the main processor 120, and a master HIT communication processor capable of reading and writing data from a memory by receiving communication information. 130, and each diva through the master HIT communication processor 130 Communication between the first, second, and third slave communication processors 136, 138, and 140 communicating with the host, and the main processor 120 and the respective HIT communication processors (130, 136, 138, and 140). DPRAM 128, which serves to match transmission and reception of messages, and functions as command processing and status transfer, and master communication processor 130 and first, second, and third slave communication processors 136, 138, and 140, respectively. A second RAM 134 for storing a transmitted message when communicating between devices, and a second ROM 132 for loading a communication program between the DPRAM 128 and the master HIT communication processor 130 to communicate between the processors. It is configured to include).

Referring to FIG. 1, a block diagram showing an embodiment of DPRAM operation according to the present invention will be described in detail. The TP 12 controls a plurality of devices, and collects data collected from each device. The collected data is transmitted to a higher processor, and input and output of messages and control signals input from a plurality of devices are controlled.

The main processor 120 is a processor responsible for the overall control of the TP 12 in the TP 12. For example, the TDX-100 switch implements the main processor 120 using the MC68060, a 32-bit high-performance processor. It was.

The four communication processors 130, 136, 138, 140 in the TP 12 take one independent form, separate from the main processor 120, including the DPRAM 128, a HIT bus communication unit 13. do.

The HIT bus communication unit 13 in the TP 12 has a structure of a master slave for HIT bus communication, and is connected to each device in the E1 / CEPT (Committee for Europe Postal Tele-communication) method. Each MC68MH360 and the second RAM 134 are connected to each other via a HIT bus by accommodating four MC68MH360 processors, which are processors that support registration and provide a function of distributing one physical channel into 32 logical channels. Connect.

The HIT bus communication unit 13 communicates with an operating system mounted on the main processor 120 with the DPRAM 128 interposed therebetween, and is dedicated to transmitting and receiving HIT bus messages at the TP 12, and one independent firmware is provided. The DPRAM 128 and the second RAM 134 are controlled according to the size of the cell of the message inputted by the second ROM 132, and the master communication processor 130 and the respective slave communication processors 136 and 138. 140, to control communication.

The HIT bus communication unit 13 communicates with the master HIT communication processor 130 and the slave HIT communication processors 136, 138, and 140 via the HIT bus, the DPRAM 128, and the bus 121. And communication between the main processor 120.

Each HIT communication bus (130, 136, 138, 140) has 16 channels, and one TP (120) having four HIT communication buses (130, 136, 138, 140) is 2.048 Mbps at 128 Kbps. It may have a variable communication bandwidth.

DPRAM 128 is connected to the data, system data, address bus 121 and stores the message input from the HIT bus communication unit 13, and at the same time the main processor 120 or communication processor 122 via the bus 121 Reads the message, and transmits the message to the upper processor through the communication processor 122.

When the message is transmitted from the upper processor or the main processor 120 through the communication processor 122, the DPRAM 128 stores the transmitted message and reads it from the master HIT communication processor 130.

The second ROM 132 is between the DPRAM 128 and the master HIT communication processor 130 and the master HIT communication processor 130, each of the first, second, and third slave HIT communication processors 136, 138, 140. It implements firmware that allows communication between the device and each device.

The lowest communication bandwidth between each HIT communication processor 130, 136, 138, and 140 and each device is 64, that is, a value of dividing 2.048 Mbps into 32 time slots, that is, 64 Kbps becomes one time slot.

Since only one time slot can transmit or receive, two channels consist of 64Kbps and 128Kbps.

Referring to FIG. 2, a data structure diagram showing a format for dividing data in DPRAM will be described in detail. The control parameter area 20 analyzes an input parameter to recognize a device or an address corresponding to the parameter.

Each of the transmit buffer 22 and the receive buffer 24 should be allocated by 72 bytes. In this case, each of the transmit / receive cells has the same size of DPRAM and the transmit / receive cells are 451, respectively. 130, 136, 138, 140).

When the size of the message input from the device or the main processor 120 is large, the message is divided and transmitted to the corresponding area.

INT (main processor-> HIT communication processor) 26 indicates when a message is sent from main processor 120 to the corresponding HIT communication processor.

An INT (HIT communication processor-> main processor) 28 indicates when a message is sent from the main processor 120 to the corresponding HIT communication processor.

The cells of the transmit / receive buffers 22 and 24 divided into 72 bytes each have a head including a device address, a dummy, a type, a message number, a piggyback, a group name, and a length 222. ), And transmits the corresponding message 224.

In the above description, the type, message number, and piggyback are information necessary for executing the sliding window.

Referring to Figure 3 in detail with respect to the step of writing a message to the DPRAM in the processor according to the present invention,

It is determined whether a flag is set in the cell of the DPRAM 128 to which the current message is to be written (step 302).

If it is determined in step 302 that the flag of the DPRAM 128 cell to which the current message is to be written is set, then the process returns.

If it is determined in step 302 that the flag of the DPRAM 128 cell to write the current message is not set, it is determined whether the length of the message to write to the cell is less than or equal to 64 bytes (step 304).

If it is determined in step 304 that the length of the input message is greater than 64 bytes, the number of required cells calculated from the length of the message is calculated, the calculated integer value is set to count, and (message length-64Byte)- 72, the calculated value is taken and set as a dummy (step 306).

It is determined whether or not a flag is set even in one cell among the number of cells counted in the cell to which data is currently written in the DPRAM 128 (step 308).

As an example, when there is a message having a count of 3, it is determined whether the flag is set in a cell in which the flag is not set three consecutive times.

If it is determined in step 308 that at least one cell has a flag set among the number of cells counted in the cells of the DPRAM 128 to which the current data is to be written, it returns.

If it is determined in step 308 that none of the counted cells in the current cell has a flag set, the message is recorded in the corresponding cell to which the current data is to be written by attaching a head to 64 bytes corresponding to the corresponding message. Then, 1 is subtracted from the count value to set the count value (step 310).

It is determined whether the count has a value of 0 (step 312).

If it is determined in step 312 that the count does not have a value of zero, it is determined whether the corresponding cell to which data is currently written in the DPRAM 128 is the last cell (step 314).

If it is determined in step 314 that the current cell is not the last cell, it sequentially moves to the next cell (step 316).

If it is determined in step 314 that the cell for which the current message is recorded is the last cell, it moves to the first cell (step 318).

It is determined whether a dummy value exists in the head of the moved DPRAM 128 cell (step 320).

If it is determined in step 320 that there is no dummy value, 72Byte, which is the next part of the message, is moved to the current cell and the process proceeds to step 330 (step 322).

If it is determined in step 320 that there is a dummy value, it is determined whether the count value is 1 (step 324).

If it is determined in step 324 that the count value is 1, the last dummy message is written in the cell to which the current data is to be written, and the flow proceeds to step 330 (step 326).

If it is determined in step 324 that the count value is not 1, then the next portion of the message, 72 bytes, is written to the current cell and the process proceeds to step 330 (step 328).

After subtracting 1 from the count value, the subtracted count value is set to the count value and the process proceeds to step 312 (step 330).

If it is determined in step 312 that the count has a value of 0, a flag is set in the corresponding first cell and the process proceeds to step 336 (step 332).

If it is determined in step 304 that the length of the input message is less than or equal to 64 bytes, the message is recorded in the current cell with data including the head information and the message information, and a flag of the cell is set (step 334).

It is determined whether the cell of the current DPRAM 128 is the last cell (step 336).

If it is determined in step 336 that the current cell is not the last cell, it moves to the next cell and returns to start from the first step (step 338).

If it is determined in step 336 that the cell for which the current message is recorded is the last cell, it cycles to the first cell of the DPRAM 128 and returns to start from the first step (step 340).

Referring to FIG. 4, the steps of reading a message of the DPRAM in the processor according to the present invention will be described in detail. It is determined whether a flag is set in the cell of the DPRAM 128 to which the current message is to be read ( Step 402).

If it is determined in step 402 that the flag of the DPRAM 128 cell for which the current message is to be read is not set, then the process returns.

If it is determined in step 402 that the flag of the DPRAM 128 cell to which the current message is to be read is set, it is determined whether the length of the message of the cell to be read is smaller than or equal to 64 bytes (step 404). .

If it is determined in step 404 that the length of the message to be read is greater than 64 bytes, the message containing the head (8 bytes) is read from the cell of the current DPRAM 128, and the count (the number of messages is several cells). Is calculated, and the value calculated by (length of message-64Byte) -72 is taken and set as a dummy (step 406).

It is determined whether the count has a value of zero (step 408).

If it is determined in step 408 that the count does not have a value of 0, it is determined whether the corresponding cell to which the current data of the DPRAM 128 is to be read is the last cell (step 410).

If it is determined in step 410 that the current cell is not the last cell, it sequentially moves to the next cell (step 412).

If it is determined in step 410 that the cell read from the current message is the last cell, it moves to the first cell (step 414).

It is determined whether a dummy value exists in the head of the moved DPRAM 128 cell (step 416).

If it is determined in step 416 that there is no dummy value, the next byte of the message, 72 bytes, is read from the current cell and the process proceeds to step 426 (step 418).

If it is determined in step 416 that there is a dummy value, it is determined whether the count value is 1 (step 420).

If it is determined in step 420 that the count value is 1, it reads from the cell to read the current data as much as the last pile of the message and proceeds to step 426 (step 422).

If it is determined in step 420 that the count value is not 1, then the next portion of the message, 72 bytes is read into the current cell and the process proceeds to step 426 (step 424).

Clear the flag of the cell area from which the current message has been read (step 426).

After subtracting 1 from the count value, the subtracted count value is set to the count value and the process proceeds to step 408 (step 428).

If it is determined in step 408 that the count has a value of 0, the flag is cleared in the first cell and the process proceeds to step 434 (step 430).

If it is determined in step 404 that the length of the input message is less than or equal to 64 bytes, the head information and the message information are read from the message in the current cell and the flag of the read information is cleared (step 432).

It is determined whether the cell of the current DPRAM 128 is the last cell (step 434).

If it is determined in step 434 that the cell read from the current message is not the last cell, it moves to the next cell and returns to start from the first step (step 436).

If it is determined in step 434 that the cell read from the current message is the last cell, it cycles to the first cell of the DPRAM 128 and returns to start from the first step (step 438).

The principles of the invention have been described above in connection with specific devices, which are described by way of example only, and are not limited to the spirit of the invention as described in the appended claims.

As described above, the present invention can prevent the memory shortage of the DPRAM 128 that may occur when the DPRAM 128 is communicated between the HIT communication processor and the main processor 120, and the DPRAM 128 may be prevented. It can be used efficiently, and the cost can be reduced.

Claims (5)

The role and command processing of the transmission and reception matching of communication messages between the main processor 120 and the main processor 120 and the respective HIT communication processors (130, 136, 138, 140) in the processor and the main processor 120 and An interprocessor communication system including a DPRAM 128 that functions to transfer status, and respective HIT communication processors 130, 136, 138, and 140 that receive communication information and read and write data from a memory. In A first determining step of determining whether a flag is set in a cell of the DPRAM 128 to write a current message; If it is determined in the first determination step that the flag of the DPRAM 128 cell to write the current message is not set, it is determined whether the length of the message to be written to the cell is less than or equal to the preset message length. A second judging step; If it is determined in the second determination step that the length of the input message is smaller than or equal to the preset message length, writing data including head information and message information in the current cell and setting a flag of the cell; ; A third determining step of determining whether the cell of the DPRAM 128 is the last cell; If it is determined in the third determination step that the current cell is not the last cell, moving to the next cell; And if it is determined in the third determination step that the cell in which the current message is recorded is the last cell, moving to the first cell of the DPRAM (128). The method of claim 1, And if it is determined in the second determination step that the length of the input message is greater than the preset message length, the message is cut into the preset message length and a ties message is written to the DPRAM 128. . The method of claim 1, The preset message length is 64 bytes, and the head is set to 8 bytes. The role and command processing of the transmission and reception matching of communication messages between the main processor 120 and the main processor 120 and the respective HIT communication processors (130, 136, 138, 140) in the processor and the main processor 120 and An interprocessor communication system including a DPRAM 128 that functions to transfer status, and respective HIT communication processors 130, 136, 138, and 140 that receive communication information and read and write data from a memory. In A first judging step of judging whether a flag is set in a cell of the DPRAM 128 for reading a current message; If it is determined in the first determination step that the flag of the DPRAM 128 cell to read the current message is set, is the length of the message to be read of the cell smaller than or equal to the preset message length? A second judging step of judging; Reading head information and message information from a message in a current cell and clearing a flag of the read information if it is determined in the second determination step that the length of the input message is smaller than or equal to a preset message length; A third determining step of determining whether the cell of the DPRAM 128 is the last cell; If it is determined in the third determination step that the cell read from the current message is not the last cell, moving to the next cell; And if it is determined in the third determining step that the cell read from the current message is the last cell, moving to the first cell of the DPRAM (128). The method of claim 4, wherein If it is determined in the second determination step that the length of the message input to the DPRAM 128 is larger than the preset message length, the input message is read and the message which is cut to the preset message length is read back to the original message. DPRAM operation method characterized in that the reading.

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