KR100253302B1 - Full adder - Google Patents

Abstract

PURPOSE: A full adder is provided to calculate and output a carry signal as rapidly as a delay velocity in one exclusive-OR gate. CONSTITUTION: An exclusive-OR gate(XOR1) receives and exclusively ORs input signals(A)(B). An exclusive-OR gate(XOR2) receives and exclusively ORs the output of the exclusive-OR gate(XOR1) and an input signal(C) and outputs an adding signal(SUM). A carry signal calculating unit(100) receives the input signals(A),(B),(C) and outputs a carry signal(CA). PMOS transistors(PM1)(PM2) are connected to a power source voltage(VCC) in parallel, and each drain is commonly connected, and receives the input signals(B)(A) to each gate. A PMOS transistor(PM3) and an NMOS transistors(NM3) drain connecting dot thereof are connected to the PMOS transistors(PM1)(PM2) in serial, and receives the input signal(C) in each gate. NMOS transistors(NM1)(NM2) each drain thereof is connected to the source of the NMOS transistors(NM3) in parallel, and each source is connected to a VSS, and receives the input signals(B)(A). In addition, PMOS transistors(PM4)(PM5) and NMOS transistors(NM4)(PM5) are provided. An inverter(INV1) is commonly connected to the drain connection dot of the PMOS transistor(PM3), the NMOS transistor(NM3) and the drain connection dot of the PMOS transistor(PM5), the NMOS transistor(NM4). The inverter(INV1) receives and reverses an output of the common connection dot and outputs a carry signal.

Description

Full adder {FULL ADDER}

TECHNICAL FIELD The present invention relates to a full adder, and more particularly, to a full adder and a computing device suitable for improving the performance of a computing device using the full adder by reducing a delay time delayed by a carry operation of the full adder. will be.

In general, the adder has a full adder and a half adder, and the full adder receives a carry, which is a rounding number, generated when both the mantissa and the addee are '1' together with the mantissa and the singer and adds three bits. The half adder is a combination circuit that simply adds two bits without considering carry. These two half adders can be used to design the full adder. When described in detail with reference to the accompanying drawings, such a conventional full adder and a computing device using the same as follows.

1 is a circuit diagram of a conventional general full adder, as shown in FIG. 1, an AND gate AND1 for receiving and inputting input signals A and B, and an exclusive OGX for exclusive ora combination; An AND gate AND2 for receiving and outputting the output of the exclusive OR gate XOR1 and the input signal C, and an exclusive OR gate XOR2 for outputting the addition signal SUM in combination with the exclusive OR; It consists of an OR gate OR1 that receives the outputs of the AND gates AND1 and AND2 from one side and the other side, and outputs a carry signal CA by combining the OR's. The reference numeral 10 denotes a carry signal calculator. The operation of the conventional general full adder configured as described above will be described below.

First, since the input signals A and B are input to the exclusive ora gate XOR1 and combined with the exclusive ora, '1' is output only when the input signals A and B are different from each other. The sum of the input signals A and B is output. When the input signals A and B are both '1', '1' is output through the AND gate AND1. This is the carry of the input signal (A), (B) is output.

In addition, since the sum of the input signals A and B output through the exclusive OR gate XOR1 is combined with the exclusive signal through the input signal C and the exclusive OR gate XOR2, the input signal A The addition signal SUM of, (B) and (C) is output through the exclusive orifice XOR2. At this time, since the sum of the input signals A and B output through the exclusive ogate XOR1 is AND-combined again through the input signal C and the AND gate AND2, the input signals A and ( The carry of the sum of B) and the input signal C is output. Therefore, the carry of the sum of the input signals A and B output through the AND gate AND2 and the carry of the input signal C are the input signals A and B output through the AND gate AND1. The carry signal of the input signal (A), (B), (C) is outputted by being orally combined through the carry and the OR gate OR1.

FIG. 2 is a circuit diagram of a full adder using a conventional multiplexer, and an exclusive ogate (XOR3) which receives an input signal (B) and (C) and combines an exclusive oar as shown therein; An exclusive ogate XOR4 that receives the output TEMP and the input signal A of the exclusive ogate XOR3 and outputs an addition signal SUM by combining the exclusive oars; Input signals A and C are input to the respective input terminals IN1 and IN2, and the output TEMP of the exclusive OR gate XOR3 is input to the selection terminal S, and the input signals A and C are input. ) And a multiplexer MUX1 for outputting the carry signal CA, where reference numeral 20 denotes a carry signal calculator. Hereinafter, the operation of the full adder using the conventional multiplexer configured as described above will be described.

The operation of outputting the addition signal SUM of the input signals A, B, and C through the exclusive ogates XOR3 and XOR4 is the same as the general full adder of FIG.

However, the carry signal CA, which is the output of the carry signal calculation unit 20, is determined by the selection output of the multiplexer MUX1. That is, when the output TEMP of the exclusive OR gate XOR3 is '1' (when the input signals B and C are different), the multiplexer MUX3 receives the input to the selection terminal S and receives the input terminal IN2. Select the input signal (A) input to output the carry signal (CA), on the contrary, when the output TEMP of the exclusive OR gate (XOR3) is '0' (input signal (B), (C) When the same, the multiplexer MUX3 receives the input to the selection terminal S and selects the input signal C input to the input terminal IN1 to output the carry signal CA. The full adder using the multiplexer thus operated has a truth table as described in the table below.

A B C TEMP SUM CA 0 0 0 0 0 0 0 0 One One One 0 0 One 0 One One 0 0 One One 0 0 One One 0 0 0 One 0 One 0 One One 0 One One One 0 One 0 One One One One 0 One One

FIG. 3 is a diagram illustrating an example of a computing device in which two full adders using a conventional multiplexer are connected. As shown in FIG. 3, the input signals A1, B1, and C1 are received as shown in FIG. A first full adder FA1 for outputting the addition signal SUM1 and the carry signal CA1 through a calculation using a multiplexer; The addition signal SUM1 of the first full adder FA1 is input as the input signal A2, the carry signal CA1 is input as the input signal C2, and the input signal B2 is received from the user. Comprising a second full adder FA2 for outputting the addition signal SUM2 and the carry signal CA2 through the operation, the operation of the embodiment of the prior art configured as described above is as follows.

The addition signal SUM1 and the carry signal CA1, which receive the input signals A1, B1, and C1, respectively, and are output through the internal operation of the first full adder FA1, correspond to two exclusive ogates. Has a delay time. The second full adder FA2 receives the addition signal SUM1 as the input signal A2, receives the carry signal CA1 as the input signal C2, and receives the input signal B2 from the user. The addition signal SUM2 and the carry signal CA2 are output through an internal operation. Therefore, the addition signal SUM2 and the carry signal CA2 have a delay time corresponding to four exclusive ogates.

However, the conventional general full adder operated as described above is delayed by a delay time corresponding to two exclusive ogates when the addition signal is calculated, and the carry signal is delayed more than the addition signal because it uses more gates than the addition signal. The full adder using the multiplexer receives a signal in which the second and third input signals are exclusively combined at a selection stage, selects the first and third input signals of the input stage, and outputs the carry signals. Although the delay difference between the signal and the carry signal is reduced, there is still a problem of delaying the delay time corresponding to two exclusive ogates when calculating the addition signal. Therefore, a computing device that connects a plurality of full adders in series or in parallel has a problem of deterioration in performance due to delay accumulation of the addition signal and the carry signal as described above.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a full adder capable of outputting a carry signal as fast as the delay of the carry signal. .

In addition, another object of the present invention is to reduce the delay of the entire system by using a carry signal that is quickly output from the full adder when multiplying a plurality of full adders in series or in parallel to achieve the above object is achieved In addition, the present invention provides a computing device that can improve performance.

1 is a circuit diagram of a conventional general full adder.

2 is a circuit diagram of a full adder using a conventional multiplexer.

3 is a diagram illustrating one embodiment of a computing device in which two full adders are connected.

4 is a circuit diagram of a full adder according to the present invention;

FIG. 5 is a diagram of one embodiment of a computing device in which two full adders are connected in FIG.

*** Description of the symbols for the main parts of the drawings ***

FA10, FA20: 1st, 2nd full adder 100: Carry signal calculation unit

PM1 to PM5: PMOS transistors NM1 to NM5: Enmo transistors

XOR1 to XOR4: Exclusive ore gate INV1: Inverter

The object of the present invention as described above is to add the first exclusive or the first and second input signal and the exclusive exclusive combination by receiving the output of the first exclusive or gate and the third exclusive signal and the third exclusive signal. A second exclusive ogate for outputting a signal; First and second PMOS transistors each source is connected in parallel to a power supply voltage, and each drain is commonly connected to receive a second input signal and a first input signal to each gate; A third PMOS transistor and a third NMOS transistor connected in series with the drain connection points of the first and second PMOS transistors to receive a third input signal to each gate; First and second NMOS transistors, each drain being connected in parallel to a source of the third NMOS transistor, each source being connected to ground, and receiving a second input signal and a first input signal to each gate; A fourth PMOS transistor that is connected in series with the power supply voltage and ground to receive the first input signal to the gate, the fifth PMOS transistor that receives the second input signal to the gate, and the fourth input to receive the second input signal to the gate A fifth NMOS transistor receiving the NMOS transistor and the first input signal to the gate; The drain connection point of the third PMOS transistor and the third NMOS transistor and the drain connection point of the fifth PMOS transistor and the fourth NMOS transistor are commonly connected, and the output of the common connection point is inverted to output a carry signal. This is achieved by configuring an inverter.

In addition, another object of the present invention is to provide a serial or parallel connection to a plurality of full adders configured as described above, wherein the carry signal of the nth full adder is input as the first input signal of the n + 1 full adder. And inputting the addition signal of the nth full adder to the third input signal of the n + 1th full adder. Where n is an integer.

Hereinafter, with reference to the accompanying drawings, a full adder and a computing device using the same according to the present invention will be described in detail.

4 is a circuit diagram of a full adder according to the present invention, and as shown therein, an output of an exclusive ogate XOR1 and an exclusive ogate XOR1 for receiving an exclusive or combination of input signals A and B. And an exclusive ogate (XOR2) for receiving an input signal (C) and outputting an addition signal (SUM) by combining an exclusive oar; It is composed of a carry signal calculation unit 100 for receiving the input signals (A), (B), (C) and outputs a carry signal (CA). The carry signal operation unit 100 includes PMO transistors PM1 for which respective sources are connected in parallel to the power supply voltage VCC, and drains are commonly connected to receive input signals B and A to each gate. (PM2); PIM transistors PM3 and PM2 and NMO3 which are connected to their drain connection points in series with the PMO transistors PM1 and PM2 and receive the input signal C at each gate; Each drain is connected in parallel to the source of the NMOS transistor NM3, and each source is connected to the ground VSS to receive the input signals B and A at each gate. (NM2); PMOS transistor PM4 that is connected in series with the power supply voltage VCC and ground VSS to receive the input signal A at the gate, PMOS transistor PM5 that receives the input signal B at the gate, and is input. An NMOS transistor NM4 that receives the signal B at the gate and an NMOS transistor NM5 which receives the input signal A at the gate; The drain connection point of the PMOS transistor PM3 and the NMOS transistor NM3 and the drain connection point of the PMOS transistor PM5 and the NMOS transistor NM4 are connected in common, and the output of the common connection point is inverted to carry The operation of the full adder according to the present invention, which is composed of an inverter INV1 for outputting a signal CA, is as follows.

The operation of outputting the sum signal SUM of the input signals A, B, and C through the exclusive ogates XOR1 and XOR2 is the same as the conventional general full adder of FIG.

However, in the carry signal calculating unit 100, when the input signals A and B are both '0', the PMOS transistors PM4 and PM5 are turned on, so that the voltage power supply is independent of the input signal C. The high potential according to VCC is inverted through the inverter INV1, and the carry signal CA is output as '0'.

When only one of the input signals A and B is '1', any one of the PMOS transistors PM1 and PM2 is turned on and any one of the NMOS transistors NM2 and NM2 is turned on. Since PMO transistors PM3 and NMOS transistors NM3 are operated as inverters, the inverted signal of the input signal C is output at the drain connection points of the PMOS transistors PM3 and NMOS transistors NM3. Since the output signal is inverted again through the inverter INV1, the signal corresponding to the input signal C is output as the carry signal CA.

When the input signals A and B are both '1', the enMOS transistors NM4 and NM5 are turned on, so that the low potential according to the ground potential VSS is independent of the input signal C. Is inverted through the inverter INV1, and the carry signal CA is output as '1'.

Therefore, the carry signal CA is delayed and output by the turn-on time of the MOS transistor and the delay time of the inverter INV1 in any of the input signals A, B, and C. This delay is not much different from the delay in one exclusive ogate.

FIG. 5 is a diagram showing an embodiment of a computing device connected to two full adders according to the present invention. As shown in FIG. 5, the input signals A1, B1, and C1 are inputted. A first full adder FA10 for outputting the addition signal SUM1 and the carry signal CA1 through an operation according to the invention; The carry signal CA1 of the first full adder FA10 is input as the input signal A2, the addition signal SUM1 is input as the input signal C2, and the input signal B2 is received from the user. Comprising a second full adder FA20 for outputting the addition signal (SUM2) and the carry signal (CA2) through the operation, the operation of the embodiment of the present invention configured as described above is as follows.

The addition signal SUM1, which receives the input signals A1, B1, and C1, respectively, and is output through the internal operation of the first full adder FA10, is delayed by two exclusive ogates, and the carry signal ( CA1) has a delay time corresponding to one exclusive ogate. The second full adder FA20 receives the addition signal SUM1 as the input signal C2, receives the carry signal CA1 as the input signal A2, and receives the input signal B2 from the user. The addition signal SUM2 and the carry signal CA2 are output through an internal operation. Therefore, the addition signal SUM2 and the carry signal CA2 have a delay time corresponding to three exclusive ogates.

The full adder according to the present invention operated as described above shortens the delay time of the carry signal so as to have a delay time corresponding to one exclusive ogate, thereby delaying accumulation of arithmetic unit for connecting a plurality of all adders in parallel or in series. This saves time and has the effect of improving overall system performance.

Claims (1)

A second exclusive ogate that receives the first and second input signals and combines the output of the first exclusive or gate and the first exclusive or gate and the third exclusive signal and receives the exclusive input and outputs the addition signal. Wow; First and second PMOS transistors each source is connected in parallel to a power supply voltage, and each drain is commonly connected to receive a second input signal and a first input signal to each gate; A third PMOS transistor and a third NMOS transistor connected in series with the drain connection points of the first and second PMOS transistors to receive a third input signal to each gate; First and second NMOS transistors, each drain being connected in parallel to a source of the third NMOS transistor, each source being connected to ground, and receiving a second input signal and a first input signal to each gate; A fourth PMOS transistor that is connected in series with the power supply voltage and ground to receive the first input signal to the gate, the fifth PMOS transistor that receives the second input signal to the gate, and the fourth input to receive the second input signal to the gate A fifth NMOS transistor receiving the NMOS transistor and the first input signal to the gate; And an inverter for common connection between the drain connection points of the third PMOS transistor and the third NMOS transistor and the drain connection points of the fifth PMOS transistor and the fourth NMOS transistor, and receiving and inverting them to output a carry signal. Full adder.

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