KR100252635B1 - The i/o control apparatus of digital still camera - Google Patents

Abstract

PURPOSE: A device for controlling input/output of various paths using a digital signal processor and a both directions buffer and a device for controlling input/output of a digital still camera adapting thereto are provided to perform the optimum function by performing an input/output control of various paths using a digital signal processor and a both directions buffer and controlling an offset and an interference between signals. CONSTITUTION: A digital signal processor(1), which is a main processor, controls each portion, and adjusts a control time of the portions. A plurality of both directions buffers are connected to the digital signal processor(1), and convert an input/output port by selecting an on/off operation of signals of both end portions of a buffer(2) and two directions. In addition, a frame buffer stores a frame temporarily. A compression restoration processor performs a compression restoration of the frame. A memory card stores a compressed and restored frame. An NTSC encoder converts a digital signal into an analogue signal.

Description

I / O controller of multiple paths using digital signal processor and bidirectional buffer and I / O controller of digital still camera

1 is a configuration diagram of an input / output controller of multiple paths using a digital signal processor and a bidirectional buffer according to an embodiment of the present invention.

2 is a block diagram of an input / output device of a digital still camera using a digital signal processor and an input / output controller of various paths using a bidirectional buffer according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1: Digital signal processor 2 to N: Bidirectional buffer

S1 to S3: Each part in the system 1-1: A / F processing unit

A: A / D converter B: Color space converter

C: NTSC encoder D: Frame buffer

E: Decompression Processor F: Memory Card

E1: first signal stage E2: second signal stage

E3: third signal stage 0E: fourth signal stage

G: fifth signal terminal DIR: sixth signal terminal

RD: 7th signal stage WR: 8th signal stage

CONT: 9th signal stage

The present invention relates to an input / output controller of multiple paths using a digital signal processor and a bidirectional buffer, and an input / output controller of a digital still camera using the same. In more detail, if many functions must be performed in a limited path, the digital signal processor and a bidirectional buffer are used to control each one and to direct the flow of signals in a desired direction to avoid the collision and duplication of signals. The present invention relates to an input / output control apparatus of a digital still camera using the same and a device to make the same.

Conventional input and output control devices have to separate the path to avoid interference and cancellation between signals.

That is, the input and output paths must be separately set to prevent the interference between signals at each function execution, and there are limitations in eliminating interference and cancellation effects between signals occurring on the limited path.

Therefore, the conventional input / output device has to set a separate path in order to prevent interference between signals, causing complexity in the design, and there is a high possibility of causing interference and cancellation effects of the signals.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to control input / output of various paths using a digital signal processor and a bidirectional buffer, and to cancel signals between signals while passing many different types of signals on a limited signal path. And to control the interference as appropriate to perform an optimal function.

The configuration of the present invention for achieving the above object,

A digital signal processor which controls each part as a main processor and adjusts a control time of each part;

It consists of several bidirectional buffers that can switch input / output ports by selecting two directions with the signal on / off action across the buffer.

Hereinafter, with reference to the accompanying drawings will be described in detail the most preferred embodiment of the present invention.

1 is a configuration diagram of an input / output controller of multiple paths using a digital signal processor and a bidirectional buffer according to an embodiment of the present invention.

2 is a block diagram of an input / output controller of a digital still camera using a digital signal processor and an input / output controller of multiple paths using a bidirectional buffer according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the structure of this invention is

A digital signal processor (1) for controlling each part as a main processor, and each part adjusting a control time;

It is connected to the digital signal processor 1, and consists of a plurality of bidirectional buffers that can switch input / output ports by selecting two directions together with the on / off action of the signals across the buffer 2.

The operation of the present invention made as described above is as follows.

First, in order to control the signal from S1 to S2 and not from S3, the digital signal processor is controlled as follows. First, S1 and S2 are connected to the digital signal processor so that the signal is transmitted and the buffer is not transmitted to the digital signal processor. At this time, in order to connect S1 and S1 to the digital signal processor, E1 and E2 are in a low level "L" signal state, and the fifth signal stage of the buffer is not connected to the digital processor 1 so as not to connect the buffer 2. A high level "H" signal is applied to G) to cause the buffer 2 to be in an interrupted state, and the seventh signal terminal DIR is also automatically in an interrupted state.

In order to prevent the signal from flowing from S3 to S2 and not from S1 to S3, first, the digital signal processor 1 is connected to S2 and S3 so that the signal is transmitted, and the buffer 2 is connected to the digital signal processor 1. ). At this time, S2 and S3 are connected to the digital signal processor 1 so that E2 and E3 are in the low level "L" signal state, and the buffer is connected to the digital signal processor 1 to flow the signal in the reverse direction. The fifth signal terminal G of 2) has a low level "L" signal state and the sixth signal terminal DIR of the buffer 2 has a high level "H" signal state.

In order to control the signal from S1 to S2, the signal from S1 to S3, and the signal from S1 to S3 not to flow while the function is performed at S3, the digital signal processor 1 performs stepwise control as follows.

First, a signal is transmitted by connecting S1, S2, and S3 to the digital signal processor 1, and at this time, the first signal stage E1 and the second signal to connect the S1, S1, and S3 to the digital signal processor. Both the signal terminal E2 and the third signal terminal E3 are brought to the low level "L" state. A low level "L" signal is applied to the fifth signal terminal G of the buffer to bring the buffer into an active state, and the seventh signal terminal DIR also applies a low level "L" signal to the color space converter B. ), The signal flows to the AD converter (A).

The next step is to connect S1 and S2 to the digital signal processor 1 so that the signal flows, and the signal does not flow with S3 so that the signal is not transmitted. It also allows you to perform the functions of S3. At this time, in order to connect to the signal processor, the first signal stage E1, the second signal stage E2, and the third signal stage 3 are both in a low level "L" state. A high level "H" signal is applied to the fifth signal terminal G of the buffer to cause the buffer to be stopped, and the sixth signal terminal DIR is not automatically performed.

Another configuration of the present invention for achieving the above object,

A digital signal processor including an F processor which controls each part as a main processor and adjusts a control time of each part;

A bidirectional buffer capable of switching input and output ports by selecting two directions together with on and off effects of signals across the buffer;

A frame buffer for temporarily storing the frame;

A decompression processor for performing decompression of the frame;

A memory card for storing the decompressed frame;

It consists of NTC encoder that converts digital signal into analog signal.

Hereinafter, another embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an input / output device of a digital still camera to which an input / output control device of various paths using a digital signal processor and a bidirectional buffer according to an embodiment of the present invention is applied.

As shown in FIG. 2, a configuration of an input / output device of a digital still camera using a digital signal processor and an input / output controller of various paths using a bidirectional buffer according to an embodiment of the present invention is described.

A digital signal processor 1 including an F processor 1-1 which controls each part as a main processor and adjusts a control time of each part;

A bidirectional buffer (2) (3) connected to the digital signal processor (1) and capable of switching input / output ports by selecting two directions together with on / off action of signals across the buffer;

A frame buffer (D) connected to the bidirectional buffer (2) and for temporarily storing a frame;

A decompression processor (E) connected to the digital signal processor (1) and the bidirectional buffer (2) (3) and performing decompression of a frame;

A memory card F connected to the decompression processor E;

It is connected to the color space converter (B), and consists of an NTC encoder (C) for converting digital to analog.

The operation of the present invention made as described above is as follows.

The digital still camera receives an analog RG B input signal, converts it from an analog signal to a digital signal, and performs various functions to compress and store the image on a memory card (F), and to display it back on the screen if necessary. Has the ability to Looking at the operation in more detail, the analog input signal is output as a 24-bit RGB digital signal through the AD converter (A), the RGB signal is converted into a 16-bit YCBCR signal through the color space converter (B). The signal may be output as a video directly through an NC encoder (C), or may be stored in the frame buffer (D) and image-compressed by the decompression processor (E) to convert the signal into a bit stream. Save to F). The stored image information is displayed on the monitor through the NC encoder (C) as necessary.

At this time, the control of the entire system is performed by the digital signal processor 1, and separately there is an F processing unit 1-1 in the digital signal processor 1, and Y entered through the A processing unit 1-1. The digital signal processor 1 performs the operation with the signal, and the operation result is fed back to the analog input through an unspecified digital converter.

First, when a moving image is displayed and the AF processing unit 1-1 is continuously performed, the fourth converter OE of the AD converter A and the color space converter B has a low level "L" signal state. It is still displayed on the NTC encoder. In the first stage, one frame of the video is stored in the frame buffer D. In this stage, the fifth signal stage G of the buffers 2 and 3 has a low level "L" signal state, and the sixth signal stage ( DIR) automatically maintains the "L" signal state, which is always at a low level, and gives a low level "L" signal to the eighth signal terminal WR of the frame buffer D. The next step is to apply a high level "H" signal to the fifth signal terminal G of the buffers 2 and 3 and a high level "H" signal to the seventh signal terminal RD of the frame buffer D. Data is transferred from the frame buffer D to the AFC processing unit 1-1. In this case, the data transmitted from the frame buffer D to the AF processing unit 1-1 and the color space converter B from the AD converter A by giving the fifth signal terminal G with a high level "H" signal. Prevent collisions with incoming data.

When the image is compressed and stored in the memory card F, the procedure until the image is written to the frame buffer D is performed by the fourth signal terminal OE of the AD converter A and the color space converter B at a low level. The sixth signal stage DIR has a low level "L" signal state and the fifth signal stage G has a low level "L" signal state and the eighth signal stage WR of the frame buffer. Has a low level "L" signal. In the next step, the seventh signal stage RD of the frame buffer has a high level "H" signal state, the fifth signal stage G has a high level "H" signal state, and the ninth terminal of the decompression processor E. CONT has a low level "L" signal, and the decompression processor E receives data from the frame buffer D, performs a compression function, and stores it in the memory card F. FIG. In this case, the process of displaying the video through the NTC encoder C is continued.

When the compressed image is restored and displayed on a monitor, the data received from the memory card F is restored by the decompression processor E, and sent to the frame buffer D. At this time, the eighth signal terminal WR has a low level "L". &Quot; Signal state " The fifth signal stage G maintains the " H " signal state at high level. In the next step, the seventh signal stage RD of the frame buffer D has a high level "H" signal, the fifth signal stage G has a low level "L" signal, and the sixth signal stage DIR has a high level. The fourth signal stage OE of the AD converter A and the color space converter B maintains a high level " H " signal and is displayed on the NTC encoder C. The " H " Therefore, when displaying with the NC encoder (C), the data signal is prevented by stopping the fourth signal terminal (OE) of the AD converter (A) and the color space converter (B). In many other modes, signal control through buffers and digital signal processors allows for optimal functionality.

With the effects of the present invention operating as described above, it is possible to avoid collisions and cancellations between signals occurring when performing various functions simultaneously, to implement more functions on a limited path, and to design signals and control stages. In consideration of the optimal state can be designed. You can also continue to watch video while performing compression on your digital still camera. In addition, one NC encoder can be used to reproduce both still and moving images. Performs the F function related to the continuous CD processing speed and the correction function accordingly.

Claims (2)

A digital signal processor which controls each part as a main processor and adjusts a control time of each part; A digital signal processor and a multi-path input / output controller using a bi-directional buffer, characterized by a plurality of bidirectional buffers that can switch input / output ports by selecting two directions along with the on / off action of the signals at both ends of the buffer. A digital signal processor including an F processor which controls each part as a main processor and adjusts a control time of each part; A bidirectional buffer capable of switching input and output ports by selecting two directions together with on and off effects of signals across the buffer; A frame buffer for temporarily storing the frame; A decompression processor for performing decompression of the frame; A memory card for storing the decompressed frame; Digital still camera input / output controller using digital signal processor and multi-path input / output controller using bi-directional buffer, characterized in that it consists of NTS encoder which converts digital signal into analog signal.