KR100249970B1 - Apparatus for correcting delay in isdn - Google Patents

Abstract

The present invention relates to an ISDN delay compensation device capable of compensating for delays between channels by minimizing hardware configuration in an n-BRI interface that transmits data using a plurality of channels, and n criteria corresponding to each of n channels. An index table for storing index bits, each of which is received through each of the n channels, and stores n transmission index bits each having the same bit value as the n reference index bits, when the shift control signal is provided N shift registers for selectively shifting the stored n transmission index bits sequentially by one bit, each reference index bit provided in the index table and each corresponding transmission index bit or shifted angle provided in the n shift registers, respectively. The transmission index bits are compared respectively, and corresponding to the comparison result Delay of each channel is detected based on the n comparison units generating discrimination signals and the discriminating signals generated respectively, and when a delay is detected in a specific channel, the transmission index bit received through the specific channel and And a control unit for generating the shift control signal for sequentially shifting corresponding transmission index bits stored in the corresponding shift register by one bit until the corresponding reference index bits match.

Description

Delay Compensation Device in Integrated Information Network (ISDN)

The present invention relates to an integrated services digital network (ISDN), and more particularly, to a delay compensation method in ISDN suitable for correcting a delay for each channel in communication between the same system at a remote location.

As is well known, ISDN has emerged to overcome the service limitations of individual networks that handle voice, video, and data separately, and is a comprehensive information and communication network that integrates each individual network and digitalizes each data to provide a comprehensive service. .

The interface for transmitting video data in the ISDN network is classified into 1-BRI, 2-BRI, 3-BRI, ..., depending on how many channels are used to transmit video data of one frame.

That is, it is called 1-BRI when transmitting using one channel, 2-BRI when transmitting using two channels, and 3-BRI interface when transmitting using three channels. Is proportional to the number of such channels.

However, in the above-described IS-BRI (n is 2 or more) interface of the ISDN, in transmitting video data for one frame, a delay occurs in each channel to restore the data transmitted from the receiver to the original data. Many errors will occur.

Therefore, to solve this problem, ISDN's N-BRI interface uses an industry standard bonding protocol as a method of correcting delay. Effort is required, and there are still problems that many errors still occur in the implemented system.

Accordingly, the present invention is to solve the problems of the prior art described above, to provide a delay compensation method on the IS-BRI (Bearer Rate Interface) of ISDN that can compensate the delay between channels by minimizing the logic for delay correction Its purpose is to.

In order to achieve the above object, the present invention provides an index table for storing n reference index bits corresponding to each of n channels, and each bit received through each of the n channels and having the same bit value as the n reference index bits. N shift registers each storing n transmission index bits each having, and selectively shifting the stored n transmission index bits sequentially by one bit when a shift control signal is provided, each reference index bit provided in the index table And n corresponding comparison index bits respectively provided in the n shift registers or n shifted transmission index bits, respectively, and n comparison units each generating a discrimination signal corresponding to the comparison result, and each generated discrimination. On the basis of the signal, the delay of each channel is detected and Is detected, the shift control signal for sequentially shifting the corresponding transmission index bits stored in the corresponding shift register by one bit until the transmission index bits received through the specific channel coincide with the corresponding reference index bits. It provides a delay compensation device of a comprehensive information communication network led to a control unit for generating a.

1 is a block diagram showing the configuration of an apparatus for delay compensation of ISDN 3-BRI according to an embodiment of the present invention;

2 is a diagram showing index data for each channel on 3-BRI of ISDN according to a preferred embodiment of the present invention;

3 is a view for explaining a delay compensation method in ISDN according to a preferred embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

11, 12, 13: 1st, 2nd, 3rd shift register 20: Index table

31, 32, 33: first, second, 3 XOR gate 40: signal processing unit

50: control unit

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating a configuration of a delay compensation device in an ISDN 3-BRI according to a preferred embodiment of the present invention. The first and second and third shift registers 11, 12, and 13 and an index table ( 20), the first, second, and third XOR gates 31, 32, and 33, a signal processor 40, and a controller 50.

The first, second, and third shift registers 11, 12, and 13 receive index data in bit streams for each channel provided from the transmitting side, and shift the index data based on a control signal of the controller 50. 20 pre-stores index data for each channel on the receiving side and provides them to the first, second, and third XOR gates 31, 32, and 33.

The first, second, and third XOR gates 31, 32, and 33 are provided from the index data for each channel and the index table 20 on the transmitting side provided from the respective shift registers 11, 12, and 13. An XOR operation is performed on the receiving index data and the resultant value is provided to the controller 50.

The controller 50 generates a control signal to the shift register 11 for the corresponding channel until the operation result output from each of the XOR gates 31, 32, and 33 becomes '0', thereby providing an index provided from the transmitting side. Will shift the data.

FIG. 2 is a diagram illustrating index data for each channel on 3-BRI of ISDN according to a preferred embodiment of the present invention. Looking at the data transmission / reception process on a 3-BRI system having three channels is as follows.

Each system on an ISDN 3-BRI with three channels (a channel, b channel, and c channel) is equipped with separate index bits for each channel, as shown in the diagram, to allow data to be When you want to send to the system, insert each index at the beginning of the data and send it.

That is, when data is transmitted to a certain system using three channels a, b, and c at the transmitting side, data at the beginning of a channel data is' a1, a2, a3, .. ., a8 'inserts and transmits the index bits, b channel' b1, b2, b3, ..., b8 'index bits and c channel' c1, c2, c3, ..., The index bits of c8 'are inserted and transmitted.

In addition, the receiving side receiving the data for each channel provided from the transmitting side includes the same index bit for each channel in the index table, and performs an XOR operation on the index of the transmitted data and its own index so that the value becomes '0'. The data of the channel is shifted.

That is, if the data of each channel is normally received without being delayed, the result of the XOR operation is all '0' because the received index bits and the index bits configured in the index table are the same, and the delay of the data occurs. At least '1' is included in the result value of the XOR operation of the corresponding channel, so that the controller 50 determines that the data of the channel is delayed.

FIG. 3 is a diagram illustrating a delay compensation method in an ISDN according to a preferred embodiment of the present invention. Referring to FIG.

3A, 3C, and 3E of the respective data shown in the drawing are index bits for each channel previously stored in the index table 20 on the receiving side, and FIGS. 3B, 3D, and FIG. 3 f represents an index bit transmitted from the transmitting side and stored in each shift register 11, 12, 13.

Referring to the figure, when the data transmitted from the transmitting side is provided to the receiving side, each shift register 11, 12, 13 is the beginning of the received data for each channel (a, b, c channel). It stores the index bits for each channel inserted into it.

At this time, the data of channel a is input as shown in FIG. 3b and stored in the first shift register 11, and the data of channel b is delayed by two bits as shown in FIG. 3d and stored in the second shift register 12. If the data of channel c is delayed by one bit as shown in FIG. 3 f and stored in the third shift register 13, the controller 50 may determine index bits for each channel stored in each shift register 11, 12, and 13. The XOR gates 31, 32, and 33 for each channel are output.

In addition, the control unit 50 generates a control signal to the index table 20, whereby the index bits for each channel on the receiving side stored in the index table 20 (Figs. 3A, 3C, and 3E) are also for each channel. To the XOR gates 31, 32, 33.

On the other hand, the XOR gates 31, 32, and 33 for each channel are provided with index bits (FIGS. 3B, 3D, and 3F) provided from the first, second, and third shift registers, and the receiving side provided from the index table 20. FIG. The index bits (Figs. 3A, 3C, and 3E) are XORed.

That is, the first XOR gate 31, which first calculates each index bit for the a channel, operates on each index bit, that is, a1 ?? a1 ', a2 ?? a2', ..., a8 ?? a8 In this case, since no delay occurs in the data stored in the first shift register 11, the operation results output from the first XOR gate 31 are all '0', and the control unit 50 Therefore, the data of channel a determines that no delay occurs.

Then, the second XOR gate 32 that calculates each index bit for the b channel is operated on each index bit, that is, b1 ?? b7 ', b2 ?? b8', ..., b8 ?? b6 ' In this case, since the data stored in the second shift register 12 has a 2-bit delay, the operation result output from the second XOR gate 32 is not necessarily '0'.

Accordingly, the controller 50 generates a control signal to the second shift register 32, sequentially shifts the data stored in the second shift register 12 by one bit, and provides the second XOR gate 32 again. Done.

The second XOR gate 32 performs b1 ?? b6 ', b2 ?? b7', ..., b8 ?? b5 'again. Similarly, since the index bits do not coincide, the second XOR gate Not all calculation results output from (32) become '0'.

Therefore, the controller 50 repeats the above-described process to shift the index bit input to the second shift register 12. As a result, the controller 50 determines that the operation result of the second XOR gate 32 is Second shift register until all are '0', i.e. b1 ?? b1 ', b2 ?? b2', ..., b8 ?? b8 ', until the result of the XOR operation is all' 0 ' The index bit of (12) is shifted.

Then, again, the third XOR gate 33 that calculates each index bit for the c channel is operated on each index bit, that is, c1 ?? c8 ', c2 ?? c1', ..., c8? c7 'is performed, but the calculation result output from the third XOR gate 33 is not all' 0 '.

Accordingly, the controller 50 performs a shift operation on each index bit of the third shift register 13, so that the operation result of the third XOR gate 33 is the same as in the operation result of each index bit of the b channel described above. The index bits of the third shift register 13 are shifted until all are '0'.

That is, by performing c1 ?? c1 ', c2 ?? c2', ..., c8 ?? c8 ', the index bits of the third shift register 13 are shifted until all of the XOR operation results in' 0 '. Let's go.

As a result, the controller 50 controls the index bits for each channel provided from the transmitter to have the same delay time based on the index bits for each channel previously stored in the receiver.

That is, the receiving side adjusts the delay time of the index bit inserted at the beginning of the data stream for each channel provided from the transmitting side in the same way, so that the image data for each channel subsequently received after the index bit also has the same delay time.

Meanwhile, when the delay time of the data for each channel is compensated through the above-described process, the controller 50 transmits the image data provided from the transmitter to the signal processor 40 through the respective shift registers 11, 12, 13. The signal processor 40 displays data for each channel having the same delay time through a predetermined signal processing process.

Therefore, image data input through different channels are delay-compensated and displayed on a monitor not shown.

On the other hand, the delay time compensation device of the ISDN as described above, will be able to compensate for the delay for each channel by applying the same method as in the present invention regardless of the number of channels to interface. That is, in the case of 2-BRI for transmitting data using two channels, for example, by configuring two shift registers as described above, the delay of the video signal for each channel can be compensated.

As described above, according to the present invention, there is an effect of compensating for the delay of the image data generated in the ISDN n-BRI using simple hardware, and accordingly, the complex delay compensation device used in the past is easily used. There is an effect that can be implemented.

Claims (4)

An apparatus for compensating for the occurrence of delay in each channel in a general information communication network that transmits time-divided data through n channels from a transmitter to a receiver, the index storing n reference index bits corresponding to the n channels. table; Each of the n transmission index bits received through each of the n channels, each having the same bit value as the n reference index bits, and selectively storing the stored n transmission index bits when a shift control signal is provided N shift registers for sequential shifting by one bit into a plurality of shift registers; Each reference index bit provided in the index table and each corresponding transmission index bit or each shifted transmission index bit provided in the n shift registers are respectively compared, and a discrimination signal corresponding to the comparison result is generated. n comparison units; And detecting a delay of each channel based on each generated discrimination signal, and when a delay is detected in a specific channel, when a transmission index bit received through the specific channel and a corresponding reference index bit match. The delay compensation device of the integrated information communication network which leads to the control unit for generating the shift control signal for sequentially shifting the corresponding transmission index bits stored in the shift register by one bit. The delay compensating apparatus of claim 1, wherein the n shift registers correspond to the number of n channels. The delay compensating apparatus of claim 2, wherein the n comparison units correspond to the number of the n shift registers. The apparatus of claim 3, wherein each of the comparators comprises an XOR gate.

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