KR100249655B1 - Modeling method for bipolar transistor - Google Patents

Abstract

Modeling for a bipolar device is disclosed. The bipolar device includes a substrate of a first conductivity type, an buried layer of a second conductivity type formed on top of the substrate, an island of a second conductivity type formed on top of the buried layer, and an isolation region of the first conductivity type to isolate the island from the substrate And a collector region of the second conductivity type, a base region of the first conductivity type, and an emitter region of the second conductivity type formed on the surface of the island. The variables affecting the breakdown voltage between the islands are determined, and the breakdown voltage change is modeled as a quadratic equation with respect to the change of the variables, and each parameter used in the equation is extracted through simulation. By presenting the modeling of the relationship between the layout of the isolation region and the circuit characteristics that greatly affect the size of the chip, the minimum width of the isolation region can be set by forming an organic relationship between the process and the circuit design.

Description

Modeling Method for Bipolar Devices

The present invention relates to a modeling method for a bipolar device, and more particularly, to a model for a bipolar device for setting the minimum width of the isolation region in the bipolar device.

A bipolar device refers to an electronic device in which both electrons and holes act as carriers and operate by movement of both electrons and holes. That is, a bipolar device is an electronic device having two pn junctions, and has three device regions, an emitter base and a collector. The two pn junctions are called emitter-base junction and collector-base junction, and the modulation of current flow in the pn junction by the bias change of adjacent junctions is called bipolar transistor action.

Typically, bipolar devices are used in amplifying devices or switching devices because they have high current driving characteristics and high speed switching characteristics. In application to amplifying devices, bipolar devices serve to amplify small ac signals and, in the case of switching devices, a small amount of current is used to switch the bipolar devices from ON to OFF or vice versa. It is done.

The most commonly used structure for bipolar integrated circuits is a junction-isolated bipolar device, which uses reverse-biased pn junctions to isolate collectors on the same chip. Such junction-isolated bipolar devices are formed in either a standard buried collector (SBC) process, collector-diffused isolation (CDI) process, or triple diffusion (3D) process. Standard-burying collector processes are the most widely used.

In the manufacturing process of the junction-isolation standard-embedded collector bipolar device, forming an n ⁺ buried layer in a predetermined region of a p-type silicon substrate, and an n-type epitaxial layer on the substrate where the n ⁺ buried layer is formed forming an epitaxial layer, by forming p-type isolation diffusion regions on a surface of the n-type epitaxial layer, an n-type island which is a semiconductor region electrically isolated from the substrate by the p-type isolation diffusion region. ), Sequentially forming n ⁺ collector region, p-type base region and n ⁺ emitter region on the surface of the n-type island, and the n ⁺ collector region, p-type base region and n ⁺ emi Forming a metal wiring layer on each of the rotor regions.

However, the chip size of a bipolar integrated circuit is highly dependent on the width of the isolation region, in which the junction-isolation bipolar device forms a pn junction which is reverse biased to isolate the island from the substrate by diffusion. Therefore, the junction-isolation bipolar device described above has a disadvantage in that the total width of the isolation region is determined by the lateral diffusion, so that the silicon region occupied by the inactive isolation region is too large, resulting in poor integration.

Accordingly, recently, a method of forming an isolation region using an oxide film or reducing the thickness of an epitaxial layer and forming a bottom layer in order to reduce side diffusion is used.

However, the above-mentioned methods have a problem in that the production cost is increased or a mask is added and a new process is required in terms of mass production. In addition, parasitic npn transistors are created between the islands on which the collector, base and emitter regions are formed, thus degrading device characteristics.

Accordingly, an object of the present invention is to provide a modeling for a bipolar device that can set the minimum width of the isolation region by modeling the relationship between the circuit characteristics and the layout of the isolation region.

1 is a side view of a bipolar device according to an embodiment of the present invention.

<Description of the code | symbol about the principal part of drawing>

100: p-type silicon substrate 102: n ⁺ buried layer

104: n-type island 106: isolation region

108: n ⁺ collector region 110: p-type base region

112: n ⁺ emitter region 116: wiring layer

In order to achieve the above object, the present invention provides a substrate of a first conductivity type, a buried layer of a second conductivity type formed on the substrate, an island of a second conductivity type formed on the buried layer, the substrate and the island. A bipolar device having an isolation region of a first conductivity type and a collector region of a second conductivity type, a base region of a first conductivity type, and an emitter region of a second conductivity type formed on a surface of the island for isolating Provide modeling methods. The variables affecting the breakdown voltage between the islands are determined by the spacing between the bottom layer and the buried layer defined at the bottom of the emitter region and the isolation region, and the width of the isolation region. The change in the breakdown voltage with respect to the change in the field is modeled by a quadratic form of equation, and each parameter used in the equation is extracted by comparing the actual measured value with the values obtained through simulation.

According to the present invention, the electrical characteristic value representing the interference between islands is most clearly defined as the breakdown voltage between islands, and the variables affecting the breakdown voltage are determined to model the change of the breakdown voltage with respect to the change of the variables. Preferably, the distance between the emitter region and the isolation region, the distance between the bottom layer and the buried layer defined at the bottom of the isolation region, and the width of the isolation region as variables affecting the breakdown voltage. Decide In addition, we select the variable array that corresponds to the main points of the variable coordinate system to obtain the maximum information with the minimum simulation.

Therefore, according to the present invention, by presenting a modeling of the relationship between the layout of the isolation region and the circuit characteristics that greatly affect the size of the chip, it is possible to set the minimum width of the isolation region by forming an organic relationship between the process and the circuit design. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a side view of a bipolar device in accordance with one embodiment of the present invention, illustrating a junction-isolation standard-buried collector bipolar device.

Referring to FIG. 1, a bipolar device according to an embodiment of the present invention may include a p-type silicon substrate 100, an n ⁺ buried layer 102 formed on the p-type substrate 100, and an n ⁺ buried layer ( N-type island 104 formed as an epitaxial layer on top of substrate 100 including 102, isolation region 106 for isolating between p-type substrate 100 and n-type island 104, the n-type N ⁺ collector region 108, p-type base region 110, and n ⁺ emitter region 112, the n ⁺ collector region 108, p-type base region 110 formed on the surface of island 104. And an insulating layer 114 having contact holes exposing the n ⁺ emitter regions 112, and an upper portion of the insulating layer 114 to form the n ⁺ collector region 108 and the p-type base region ( 110, and a metal wiring layer 116 connected to the n ⁺ emitter region 112.

The isolation region 106 is formed by diffusing the pn junction and is subjected to reverse bias.

Brief description of the bipolar device manufacturing method according to an embodiment of the present invention described above is as follows.

First, n ⁺ buried layer 102 is formed in a predetermined region of p-type silicon substrate 100 by a predeposition method using chemical diffusion or ion implantation. Next, an n-type epitaxial layer 104 is formed on the substrate 100 on which the n ⁺ buried layer 102 is formed by an epitaxial process.

Subsequently, after an oxide film (not shown) is formed on the n-type epitaxial layer 104, the oxide film is etched to form a window. The p-type isolation region 106 is formed by predeposition of the p-type impurity through the window and diffusion of the p-type impurity through a drive-in process. As a result, the n-type island 104 which is a semiconductor region electrically isolated from the p-type substrate 100 is formed by the p-type isolation region 106.

Subsequently, n ⁺ collector regions 108, p type base regions 110, and n ⁺ emitter regions 112 are sequentially formed on the surface of the n-type island 104 through an impurity diffusion method. In this case, the n ⁺ collector region 108 is formed in contact with the n ⁺ buried layer 102.

Next, after the insulating layer 112 is formed on the entire surface of the resultant, the insulating layer 112 is etched to expose the n ⁺ collector region 108, the p-type base region 110, and the n ⁺ emitter region 112, respectively. Form contact holes. Subsequently, a metal such as aluminum is deposited on the entire surface of the resultant, and then patterned to connect to the n ⁺ collector region 108, the p-type base region 110 and the n ⁺ emitter region 112 through the contact holes. The wiring layer 116 is formed.

Hereinafter, the modeling of the bipolar device having the above-described structure will be described in detail with reference to FIG. 1.

In bipolar integrated circuits, the width of the isolation region 106 most affects the size of the chip. In particular, in the case of junction-isolation bipolar devices, side diffusion of the isolation region 106 directly affects layout rules.

Reducing the width of these isolation regions 106 to increase the density degrades the electrical properties between the islands 104 and causes problems. Therefore, in order to set the minimum width of the isolation region 106, an organic relationship between the electrical characteristics and the layout rule between the islands 104 must be secured.

The electrical characteristic that most clearly represents the interference between the islands 104 is the breakdown voltage characteristic between the islands 104. The breakdown voltage is an electrical characteristic value representing the allowable limit potential difference between the islands 104 and is a response that is a reference when designing a circuit. Further, the distance from the edge of the buried layer mask of the island 104 to the edge of the emitter mask of the adjacent island 104 is also one response for reducing the size of the chip.

Accordingly, in the present invention, the above-described electrical characteristic value is defined as the breakdown voltage between the islands 104, and variables (layout rules) influencing the breakdown voltage are determined. Preferably, the variables are the spacing between emitter region 112 and isolation region 106, the spacing between bottom layer 107 and buried layer 102 defined at the bottom of isolation region 106, and The width of the isolation region 106 was determined.

Subsequently, a change in the breakdown voltage with respect to the change of the three variables is modeled as a quadratic equation, and each parameter used in the equation is extracted through simulation.

At this time, in order to obtain the maximum information with the minimum simulation, the variable array corresponding to the main points of the variable coordinate system is selected. The main points are determined based on the order of the modeling equation, and the variables for finding the minimum width of the isolation region 106 and the assigned variable array are as follows.

<Variable>

W1: 3, 4, 5, 6, 7 μm

W2: 4, 5, 7, 8, 9 μm

W3: 1, 2, 3, 4, 5㎛

(Width of bottom layer: 1, 2, 3, 3, 3 μm)

Where W1 represents the spacing between emitter region 112 and isolation region 106, W2 represents the spacing between buried layer 102 and bottom layer 107, and W3 represents the width of isolation region 106. Indicates.

Where W1 represents the spacing between emitter region 112 and isolation region 106, W2 represents the spacing between buried layer 102 and bottom layer 107, and W3 represents the width of isolation region 106. Indicates.

<Variable array>

Center point (1): (5, 7, 3)

Vertex (8): (4, 5, 2)

(6, 5, 2)

(6, 8, 2)

(4, 8, 2)

(4, 5, 4)

(6, 5, 4)

(6, 8, 4)

(4, 8, 4)

Face point (6): (3, 7, 3)

(7, 7, 3)

(5, 4, 3)

(5, 9, 3)

(5, 7, 1)

(5, 7, 5)

The modeling formula of the present invention for the correlation of the breakdown voltage between the island 104 for the variable and the variable array described above is as follows.

BV _CEO = a ₀ + a ₁ W1 + a ₂ W2 + a ₃ W3 + a ₁₁ W1 ² + a ₂₂ W2 ² + a ₃₃ W3 ² + a ₁₂ W1W2 + a ₂₃ W2W3 + a ₃₁ W3W1

W _m = b ₀ + b ₁ W1 + b ₂ W2 + b ₃ W3 + b ₁₁ W1 ² + b ₂₂ W2 ² + b ₃₃ W3 ² + b ₁₂ W1W2 + b ₂₃ W2W3 + b ₃₁ W3W1

Here, the BV _CEO represents the breakdown voltage between the islands 104, and W _m represents the distance from the edge of the buried layer mask of the island 104 to the edge of the emitter mask of the adjacent island 104.

In addition, a and b are constants, and the constants are extracted by comparing actual measured values with values obtained through simulations.

As described above, according to the present invention, the electrical characteristic value representing the interference between the islands is most clearly defined as the breakdown voltage between the islands, and the variables affecting the breakdown voltage are determined to modify the change of the breakdown voltage with respect to the change of the variables. Model with. Preferably, the spacing between the emitter region and the isolation region, the spacing between the bottom and buried layers defined at the bottom of the isolation region, and the width of the isolation region are defined as variables influencing the breakdown voltage.

In addition, we select the variable array that corresponds to the main points of the variable coordinate system to obtain the maximum information with the minimum simulation.

Therefore, by presenting a modeling of the relationship between the layout of the isolation region and the circuit characteristics that greatly affect the size of the chip, it is possible to establish an organic relationship between the process and the circuit design to set the minimum width of the isolation region.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art various modifications of the present invention without departing from the spirit and scope of the invention described in the claims below And can be changed.

Claims (2)

A substrate of a first conductivity type, a buried layer of a second conductivity type formed on top of the substrate, an island of a second conductivity type formed on top of the buried layer, isolation of the first conductivity type to isolate the island from the substrate In the modeling of the bipolar device having a region, and the collector region of the second conductivity type, the base region of the first conductivity type and the emitter region of the second conductivity type formed on the surface of the island, The parameters affecting the breakdown voltage between the islands are determined by the spacing between the bottom layer and the buried layer defined at the bottom of the emitter region and the isolation region, and the width of the isolation region, The change of the breakdown voltage with respect to the change of the variables is modeled as a quadratic equation, The method for modeling a bipolar device, characterized in that for extracting by comparing the actual measured values and the values obtained through the simulation for each parameter used in the equation. The method of claim 1, wherein the simulation is performed on a variable array corresponding to main points of a coordinate system of the variable determined based on the order of the equation.

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