KR100248584B1 - Discreet cosine transform processor - Google Patents

Abstract

The present invention relates to a Discreet Cosine Transform (DCT) processor which is applied as a compression / extension processing device of a video signal. A conventional DCT processor using up / down scaling is fixed regardless of the size of input data. As the number of bits is scaled (up / down shifted), when the maximum value of the input data is smaller than the allowable value, the utilization efficiency of the internal data processing path is relatively low, and the error occurrence rate is increased. will be. The present invention is to detect the size of the input data value, and to apply the up / down scaling value in accordance with the detection result to perform the FDCT and IDCT processing to increase the data processing efficiency and reduce the occurrence of errors, such as TV, VCR, etc. Applied to video signal processing equipment.

Description

Discrete Cosine Transform Processor

The present invention relates to a block unit conversion processor such as a Discrete Cosine Transform (DCT) processor which is applied as a compression / extension processing device of an image signal. The present invention relates to a block-based conversion processor that can reduce data processing errors by variably controlling a value to be scaled according to the size of.

As shown in FIG. 1, the video encoder to which the DCT processor is applied forwards the video data of the image data source 1 to be processed in units of 8 × 8 blocks. ) And the cosine transformed data in the forward DCT 3 are quantized by the quantizer 5 with reference to the quantization table 4, which refers to the entropy table 6 and entropy encoder 7. In order to output the compressed image data 8 by encoding, the decoder recovers the original signal by performing an inverse process of the encoder by applying an inverse DCT.

Such a DCT processor applies an up / down scaling method of up / down shifting data by a certain number of bits in order to reduce processing in signal processing.

That is, according to the conventional forward DCT processor, referring to FIG. 2A, the upscaling unit 9 shifts up the data of the signal source to be processed by a predetermined number of bits, and performs a forward DCT operation of the upscaled data. An FDCT unit 10 and a down scaling unit 11 which shifts down the calculated data by the number of bits shifted up upon input and supplies the encoder to the encoder. Referring to FIG. 2B, the inverse DCT processor recovers from the decoder. The shift-up seek of the data to be processed by a certain number of bits is performed by the upscaling unit 12, the IDCT unit 13 which performs the inverse DCT operation of the upscaled data, and the number of bits shifted up when inputting the processed data. And a down scaling unit 14 for shifting down and restoring the original data.

The DCT operation processing operation by this is as follows.

When data to be processed is input to the upscaling unit 9 (12), the input data is shifted up by a predetermined number of bits, which are determined by a uniform amount regardless of the data size, and are input to the FDCT unit 13.

Accordingly, the FDCT unit 10 and the IDCT unit 13 perform the FDCT operation and the IDCT operation, respectively, and output the calculated data, which are shifted at the time of input by the downscaling units 11 and 14, respectively. It is shifted down by the number of up bits and outputted respectively.

Here, FDCT operation and IDCT operation processing means performing the following equation.

FDCT:

IDCT:

Therefore, the conventional DCT processor using up / down scaling scales (up / down shifts) to a certain number of bits regardless of the size of the input data. Therefore, when the maximum value of the input data is smaller than the allowable value, the internal data processing path The utilization efficiency of the is relatively low, there is a problem that the error occurrence rate is increased.

For example, in the case of a codec of the JPEG standard, although the allowable range of the input data value is 0 to 255, if the actual input data is within the range of 0 to 127, the MSB is not used on the internal data processing path. When the data is input, the processor utilization efficiency is lowered, thereby increasing the data processing error.

The present invention provides a DCT processor that detects the size of an input data value and variably applies up / down scaling values according to a detection result to perform FDCT and IDCT processing, thereby increasing data processing efficiency and reducing error occurrence. For the purpose, the following description of the configuration of the present invention with reference to the accompanying drawings.

1 is a block diagram of a video encoder to which a DCT processor is applied.

2a and b are block diagrams of a conventional DCT processor.

3a, b are block diagrams of the DCT processor of the present invention;

First, referring to FIG. 3, the DCT processor of the present invention includes a maximum value retrieval unit 15 for retrieving a maximum value of input data to be processed, and a decoder 16 for decoding output data of the maximum value retrieval unit 15. ), An upscaling selection unit 17 for selecting a scaling value according to the maximum value detection result in the decoded data as a corresponding processing path, an upscaling unit 18 for performing data shift-up with the selected upscaling value, and scaling A conversion unit 19A (19B) for block-by-block conversion of data, a downscaling selection unit 20 for switching the converted data into a processing path corresponding to a pre-selected scaling value, and data with the selected downscaling value. It is composed of a down scaling unit 21 for performing the down-sight, a diagram is applied to the encoder, b diagram is applied to the decoder, 19A is a FDCT operation, 19B is an IDCT operation .

Referring to the operation of the DCT processor of the present invention configured as described above are as follows.

The maximum value retrieval unit 15 decodes the input data value to retrieve the maximum value, and supplies the retrieved maximum value information to the decoder 16 together with the input data.

The decoder 16 decodes the input information and supplies it as scaling value selection control information according to the size of the data value currently input to the upscaling selection unit 17. The upscaling selection unit 17 supplies the input information (data value magnitude). Select the value to scale.

In the case of FDCT operation, the scaling value is determined by the number of scaling bits = the number of data paths that can be processed-the number of bits (data in 8 x 8 blocks) -3 of the input data maximum value, and in the case of IDCT operation The number of scaling bits is determined as the number of bits of the data processing path-input data maximum value that can be processed.

The data shifted up by the upscaling unit 18 according to the scaling value determined in this way, that is, the number of data bits to be shifted, is converted into FDCT operation and IDCT operation processing by the conversion unit, that is, the FDCT unit 19A or the IDCT unit 19B, respectively. Will go through.

The downscaled value to be shifted down by the number of bits selected by the upscaling selector 17_ in the downscaling selector 20 is selected by the downscaling selector 20. The shifted down data is output to complete the DCT processing operation.

As described above, according to the present invention, since signal processing according to the data size of the DCT processor is made variable, it is possible to reduce the occurrence of data errors, thereby providing precision and reliability in signal processing, and improving the data processing efficiency. This can increase the performance.

Claims (2)

A block unit conversion processor applied to a video signal compression / extension processor, the maximum value retrieval unit 15 for retrieving the maximum value of the input data to be processed and the maximum value retrieval unit 15 for decoding the output data. A decoder 16, an upscaling selector 17 for selecting a scaling value according to the maximum value detection result in the decoded data as a corresponding processing path, a data shift upscaling unit 18 at the selected upscaling value, and scaling data A conversion unit 19A (19B) for block unit conversion processing of the downlink, a downscaling selection unit 20 for switching the defense or processed data to a processing path corresponding to a predetermined scaling value, and the selected downscaling path data. Discrete cosine transform (Discrete Cosine Transform) processor, characterized in that the down scaling unit 21 for performing a shift down. The method according to claim 1, wherein the selection of the scaling value (number of scaling bits) in the upscaling selecting section (17) is, in the case of an FDCT operation, the number of bits of the maximum value of the input data in the number of processable data processing paths (8x). Discrete cosine transform, characterized by subtracting '3' and data from 8 blocks, and in the case of IDCT operation, the number of processable data processing paths is determined by subtracting the number of bits of the maximum input data. Discrete Cosine Transform processor.