KR100247003B1 - Phase locked loop by using dual loop filter for digitalized rf communication system - Google Patents

Abstract

The present invention relates to a double loop filter phase locked loop circuit for a digital wireless communication system. The dual loop filter phase locked loop circuit of the present digital wireless communication system having a voltage controlled oscillator and a loop filter is connected between a phase detector, one output terminal of the phase detector, and an input terminal of the loop filter to form a broadband loop. A phase-synchronized loop frequency synthesizer having an internal charge pump, and coupled between the first and second phase detectors of the phase detector and an input terminal of the loop filter, to form a narrow band loop to form the first and second phases. And an external charge pump which reduces the amount of current output to the detection terminal to reduce the amount of current provided to the loop filter.

Description

PHASE LOCKED LOOP BY USING DUAL LOOP FILTER FOR DIGITALIZED RF COMMUNICATION SYSTEM}

According to the present invention, a channel is allocated by a frequency division multiple access (FDMA) scheme in a digital wireless communication system and transmitted and received by a time division duplex (TDD) scheme. The present invention relates to a switching system, and more particularly to a double loop (broadband loop and narrowband loop) filter type phase locked loop (hereinafter referred to as PLL).

PLL in the RF field is considered as an important core technology for implementing a wireless communication system. Typically, a PLL is composed of a crystal oscillator, a divider, a phase detector, a loop filter, a voltage control oscillator (hereinafter referred to as a VCO), and the like.

In operation, the phase detector compares a signal divided by a crystal oscillator and a reference divider with a signal fed back through a loop filter, a VCO, and a main divider in the phase detector. It catches this match and sends this captured state to the output of the VCO.

However, there are two loop filters of the PLL, which are a wideband loop filter and a narrowband loop filter. The wideband loop filter is advantageous because the lock-up time must be fast in the initial state. However, it is advantageous to use a narrowband loop filter once it is locked. This is because the broadband loop filter has a fast lock-up time, but it is difficult to expect accurate modulation characteristics due to phase noise.

1 shows a conventional loop filter switching circuit, which is disclosed in US Pat. No. 5,175,729 with respect to a specific configuration and operation thereof. This loop filter switching circuit can be used to switch between a wideband loop filter and a narrowband loop filter.

FIG. 2 is a block diagram illustrating an inside of a PLL to which the loop filter switching circuit of FIG. 1 is applied. Specifically, the portion consisting of the phase detector 21 and the first and second charge pumps 22 and 23 is a simplified illustration of the MC12202 (Serial Input PLL Frequency Synthesizer) manufactured by MOTOROLA.

The first charge pump (pin 5 of the MC12202: D ₀ ) 22 is connected to a narrow band loop filter suitable for low phase noise and stable modulation characteristics, and the second charge pump (pin 13 of the MC12202: BISW) 23) connects a wideband loop filter suitable for fast lock-up times. One of the two charge pumps is enabled depending on whether the state of the LEI (load enable, pin 11 of the MC12202) provided by the controller (not shown) is high or low. )do. That is, when the LEI is in the high state, the second charge pump 23 is enabled to operate the wideband loop filter. When the LEI is in the low state, the first charge pump 22 is enabled to operate the narrowband loop filter. Done.

According to the above-described configuration, in the conventional loop switching, as shown in FIG. 1, an analog gate, a so-called switch 214 is turned on and controlled by the control signal D1 in an initial state in which a fast lock-up time is important. Since the switch 210 is turned off by the signal D2, two capacitors of the narrowband loop filter are connected in parallel and thus cannot function as LPF, and the broadband loop filter is connected with two capacitors and one resistor. It acts as a broadband loop filter. In contrast, when a stable modulation characteristic with low phase noise is required, the switch 214 is turned off and the switch 210 is turned on so that the narrowband loop filter operates normally as an LPF. At this time, the broadband loop filter does not operate.

As shown in FIG. 2, when the second charge pump 23 is enabled, it is connected to the second LPF 25 immediately to form a broadband loop. On the contrary, when the first charge pump 22 is enabled, the second charge pump 22 passes through the first LPF 24 and then the second LPF 25 is removed. As a result, a narrowband loop is formed. In this case, however, isolation is not completely performed between the two loops, which affects the loops. In general, a resistor is connected at the connection of two loops for the isolation of the two loop filters. The resistance of the two loops is good when the resistance is large enough. However, if the resistance is too large, it will limit the current strength, which will not provide the current required for basic loop operation, and will also cause problems with the filter characteristics. Therefore, the experiment selects the most appropriate resistance value. However, although the optimum resistance value was set, there was a limit to complete isolation. In addition, by connecting the charge pump from the outside to arbitrarily control the amount of current to adjust the loop gain to complement the existing method, such a simple control method according to the time slot (envelop) according to the time slot (slot) It was difficult to overcome the low frequency characteristics formed by the components, and it was difficult to prevent the degradation of the VCO modulation characteristics due to the data pattern of the digitized RF.

Accordingly, an object of the present invention is to design a double loop filter type phase synchronization loop circuit for a digital wireless communication system so as not to affect each other between two loops.

It is another object of the present invention to provide a phase locked loop circuit that appropriately controls the switching time of a narrowband loop and a wideband loop to have a stable modulation characteristic for any data pattern in a digital wireless communication system to increase call quality.

According to an aspect of the present invention, there is provided a phase locked loop circuit of a double loop filter type phase synchronization loop circuit in a digital wireless communication system including a voltage controlled oscillator and a loop filter. A phase-synchronized loop frequency synthesizer having an internal charge pump connected to an input terminal to form a wideband loop, and between the first and second phase detection terminals of the phase detection unit and an input terminal of the loop filter, To reduce the amount of current to be output to the first and second phase detection terminal to form an external charge pump to reduce the amount of current provided to the loop filter.

1 is a view showing a conventional loop filter switching circuit

2 is a block diagram showing an internal configuration of a phase locked loop to which a conventional loop filter switching circuit is applied.

3 is a detailed configuration diagram of a double loop circuit according to an embodiment of the present invention

4 is a block diagram showing an internal configuration of a phase locked loop to which the double loop circuit of FIG. 3 is applied.

5 is a control timing diagram in handset outgoing-call mode.

6 is a control timing diagram in base station outgoing call mode.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. Also, in the following description, many specific details such as components of specific circuits are shown, which are provided to help a more general understanding of the present invention, and the present invention may be practiced without these specific details. It is self-evident to those of ordinary knowledge in Esau. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

3 is a view showing a specific configuration of a double loop circuit according to an embodiment of the present invention, Figure 4 is a block diagram showing the internal configuration of a phase synchronization loop to which the double loop circuit of Figure 3 is applied.

R 및

P를 가지는 직렬 입력 위상동기루프 주파수합성기 100과, VCO 26과, 저역통과필터로서 위상동기루프의 동기 특성이나 응답 특성을 결정하며 상기 VCO 26의 입력단에 접속되는 루프필터 60과, 상기 위상검출부 21의 제1 혹은 제2위상검출단자

R 및

P에 각각 연결되는 제1 및 제2저항 R1, R2, 각각 베이스가 상기 제1 혹은 제2저항 R1, R2에 연결되어 콜렉터 전류가 각각 상기 제1 혹은 제2저항 R1, R2의 크기(실제로 제작할 때 사용하는 저항의 크기)에 종속되는 제1 및 제2트랜지스터 Q1, Q2, 상기 제1 및 제2트랜지스터 Q1, Q2의 콜렉터와 상기 루프필터 60의 입력단 사이에 각각 접속된 제1 및 제2루프 저항 R3, R4, 상기 제2트랜지스터 Q2의 베이스와 접지 사이에 접속된 캐패시터 C를 가지는 외부 챠지펌프 22A로 구성된다. 도시하지는 않았으나 상기 VCO 26의 출력은 위상검출부 21로 제공된다.Specifically, one internal charge pump 23B, phase detection unit 21, first and second phase detection terminals

R and

A series input phase locked loop frequency synthesizer 100 having P, a VCO 26, a loop filter 60 which is connected to an input of the VCO 26 and determines the synchronous or response characteristics of the phase locked loop as a low pass filter, and the phase detector 21 Phase 1 or 2 phase detection terminal

R and

Each of the first and second resistors R1 and R2 connected to P, respectively, and the base are connected to the first or second resistors R1 and R2, respectively, and the collector current is the magnitude of the first or second resistors R1 and R2, respectively. First and second transistors Q1 and Q2, which depend on the size of the resistor used when the first and second transistors Q1 and Q2 are connected between the collectors of the first and second transistors Q1 and Q2 and the input terminals of the loop filter 60, respectively. An external charge pump 22A having resistors R3, R4, and a capacitor C connected between the base of the second transistor Q2 and ground. Although not shown, the output of the VCO 26 is provided to the phase detector 21.

R 및

P핀으로 대체하고 그 출력에 바이폴라(bipolar) 트랜지스터 Q1, Q2를 연결하여 구성한다. 또한 상기

R 및

P핀에 각각 저항 R1, R2를 연결하여 위상검출부 21의 출력 전류량을 감소시킨다. 이렇게 되면 상기 각 저항 R1, R2에 연결된 트랜지스터 Q1, Q2의 콜렉터(collector)를 통해 상기 루프필터 60에 인가되는 전류량을 감소시키게 되는 바, 루프의 전체 이득을 줄여줌으로써 협대역 루프필터의 역할을 하도록 할 수 있는 것이다.Compared with FIG. 2 described above, the BISW pin connected to the wideband loop is left as it is, but the D ₀ pin connected to the narrowband loop is

R and

It is replaced by the P pin and configured by connecting bipolar transistors Q1 and Q2 to the output. Also above

R and

Resistor R1 and R2 are connected to P pin to reduce the amount of output current of phase detector 21, respectively. This reduces the amount of current applied to the loop filter 60 through the collectors of the transistors Q1 and Q2 connected to the resistors R1 and R2, thereby reducing the overall gain of the loop to serve as a narrowband loop filter. You can do it.

5 is the hand ?? This is the control timing diagram in the outgoing-call mode.

(5a) is a waveform showing the frequency synthesizer enable signal SYN / LE. The illustrated reference symbol t1 is a lock detection check point. (5b) shows a waveform in which the transmission control signal has a transmission time of 10 ms and a reception time of 4 ms. At this time, the handset uses MUX3 of the TDD signal layer. Reference numeral 5c denotes a waveform of a channel marker signal using MUX2 in the TDD signal layer. Specifically, when the terminal receives the call signal from the base station, the terminal detects the channel indication signal in the synchronization channel of the MUX2 and then transitions from the high state to the low state, which means that the terminal transmits to the MUX2. The illustrated reference symbol t5 indicates a time point for detecting a synchronization word transmitted from the base station, which means that frame synchronization is performed at the same time as detecting the channel indication signal.

6 is a control timing diagram in the base station outgoing call mode.

6a shows a waveform of a channel display signal using MUX2 in the TDD signal layer. The illustrated reference symbol t3 denotes an end of full packet of valid data. 6b is a waveform showing the frequency synthesizer enable signal SYN / LE. A wideband loop is formed when the waveform is high and a narrowband loop is formed when the waveform is low. As a result, the frequency synthesizer enable signal SYN / LE serves to switch wideband and narrowband. The illustrated reference symbol t4 is the lock detection check time. When the frequency synthesizer enable signal SYN / LE is high in the initial power-on or channel scanning mode, that is, in the case of a wideband loop, it is meaningless and does not perform a lock detection check, but the frequency synthesizer enable signal SYN / LE is low. If a narrowband loop is formed, the lock detection check is performed 20 ms later. This is because when the frequency synthesizer enable signal SYN / LE is low, it can communicate with stable modulation characteristics in a narrowband loop. In other words, the signal patterns of MUX3, MUX2, and MUX1 are transmitted when forming a narrowband loop with good modulation characteristics. 6c is a waveform showing the transmission control signal. At this time, the base station uses MUX2 of the TDD signal layer.

When explaining the embodiment of the present invention in detail based on the above configuration as follows.

In the initial state for catching a channel, a wideband loop is formed, resulting in fast lock-up. However, in a steady state in which actual data is applied, the loop bandwidth is reduced by controlling the output current of the phase detector 21 by acting as an external charge pump as a bipolar transistor circuit to obtain a faithful modulation characteristic for a low data rate. So that a narrowband loop is implemented.

R,

P는 위상검출부 21의 출력 핀과 연결된 저항 R1, R2의 값에 의해 트랜지스터의 베이스 전류를 조절하게 되고, 이것에 의해 콜렉터 전류도 조절할 수 있게 된다. 즉, 상기 저항 R1, R2에 의해 베이스 전류 및 콜렉터 전류가 작아지고, 이와 연결된 루프전류 또한 작아져서 루프 이득(gain)이 줄어들고 루프 대역폭도 작아져서 협대역 루프가 형성된 것과 같은 효과가 있다.Terminal of PLL IC 100 in Figure 3

R,

P adjusts the base current of the transistor by the values of the resistors R1 and R2 connected to the output pins of the phase detector 21, thereby adjusting the collector current. That is, the base current and the collector current are reduced by the resistors R1 and R2, and the loop current connected thereto is also reduced, so that the loop gain is reduced and the loop bandwidth is reduced, thereby forming a narrow band loop.

R과

P의 값에 따른 트랜지스터의 출력값에 의해 좌우되기 때문에 광대역 루프와 협대역 루프간의 상호 간섭을 해결할 수 있다. 뿐만 아니라, 저항을 이용하므로 그 값을 적절히 선택함으로써 원하는 만큼의 루프전류를 생성시킬 수 있고 그에 따라 루프 대역폭도 원하는 정도로 만들 수 있는 것이다.Transistors Q1 and Q2 and peripheral resistors R3, R4, R5 and capacitor C shown in FIG. 3 act as external charge pumps. This behavior

R and

Since it depends on the output value of the transistor according to the value of P, it is possible to solve the mutual interference between the wideband loop and the narrowband loop. In addition, the use of resistors allows the proper selection of the value to generate as many loop currents as desired and thus the desired loop bandwidth.

The case where the present invention is actually applied to CT2 will be described as an example.

Set the values of the two resistors R1 and R2 to 6.8kΩ and set the loop bandwidth at 50Hz, which is about 10 times lower than 500Hz, which is the TDD frequency of CT2, under normal conditions. This is because the modulation characteristics are affected by the loop bandwidth, so that the loop bandwidth should be designed to be 5-10 times lower than the lowest data rate in order to obtain faithful modulation characteristics even at a low data rate. Therefore, when configuring the external charge pump 22A including the bipolar transistors Q1 and Q2, the initial transient state is reduced by appropriately selecting the values of the two resistors R1 and R2 to reduce the amount of current applied to the broadband loop filter to reduce the overall gain of the loop. After fast lock-up at, the narrowband loop of about 50Hz is formed in the normal state where the actual data is applied.

In addition, the CT2 having a channel division scheme of FDMA and a transmission / reception switching scheme of TDD have various data patterns appearing in the signal layers MUX1, MUX2, and MUX3 according to TDD while repeating transmission and reception by 50% for a time slot of 2 msec. The VCO included in the RF portion of the CT2 is a local oscillator, which is commonly used as a time division across the transceiver mixer to realize low cost, small size, and low power. Therefore, the VCO has very low data rate unnecessary modulation characteristics among various data patterns appearing in the signal layer according to TDD. For example, in the handset outgoing-call mode, as shown in FIG. 5, in case of MUX3 transmission control including handshake information for initial link establishment, the transmission time Tx is 10 ms and the reception time ( If Rx) is 4ms, the transmission / reception period is 14ms, which is a very low frequency (about 71.4Hz) in terms of frequency. This low frequency reduces the modulation current because of the large phase noise when using a wideband loop, thereby reducing the loop current, thereby causing load enable timing such as (5b) and (6b) of FIG. 20ms) to form a narrowband loop to improve the modulation characteristics for low frequencies.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, the present invention not only facilitates the switching of the two loops by eliminating the mutual loop interference between the wideband and narrowband loops of the PLL, but also provides a low data rate that may occur in digital systems such as CT2. There is an effect that can compensate for the degradation of the modulation characteristics. In addition, since the wide loop or narrow band loop is automatically selected and operated according to the load enable timing in data patterns having various data rates, modulation characteristics at low data rates are improved and convenient.

Claims (6)

In a dual loop filter type phase locked loop circuit of a digital wireless communication system having a voltage controlled oscillator and a loop filter, a broadband loop is connected between a phase detector and one output terminal of the phase detector and an input terminal of the loop filter. A phase-synchronized loop frequency synthesizer having an internal charge pump, and coupled between the first and second phase detectors of the phase detector and an input terminal of the loop filter, to form a narrow band loop to form the first and second phases. And an external charge pump which reduces the amount of current supplied to the loop filter by reducing the amount of current output to the detection terminal. According to claim 1, wherein the external charge pump, the first and second resistors respectively connected to the first or second phase detection terminal, respectively, the base is connected to the first or second resistor, respectively, the collector current is the first First and second transistors depending on a first or second resistance value, loop resistors connected between the collector of the first and second transistors and the input terminal of the loop filter, respectively, between the base and ground of the second transistor. A circuit characterized by consisting of connected capacitors. 3. The method of claim 2, wherein the first and second resistors reduce the amount of output current of the phase detector to reduce the amount of current applied to the loop filter through the collectors of the first and second transistors, thereby reducing the overall gain of the loop. And a value that enables the formation of a narrowband loop filter. The phase synchronizing loop frequency synthesizer of claim 1, wherein the phase-synchronizing loop frequency synthesizer inputs a frequency synthesizer enable signal for switching broadband and narrow bands to a load enable terminal, and according to the signal, first and second phase detection terminals of the phase detection unit. A circuit, characterized in that for determining the output of. 5. The method of claim 4, wherein a predetermined time has elapsed when the frequency synthesizer enable signal transitions to a second state when the frequency synthesizer enable signal maintains a first state and a wideband loop is formed. Next, the circuit is characterized in that whether or not the lock. 6. The circuit according to claim 5, wherein the channel allocation is performed in a frequency division scheme, and the transmission and reception switching is performed in a time division duplex scheme.

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