KR100246183B1 - Serial access interfacing method and flash chip architecture - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fresh memory system comprised of a microcontroller and a stage device. In particular, a predetermined number of control transfer paths, addresses or commands are selected between the microcontroller and the stage device to select a clock pin adjustment for driving the device. And data transmission paths for data input and paths for data output, wherein the stage device includes: a general register capable of storing data according to input of a control signal and a data signal through the paths; An address register for storing the address in a signal, a data register for storing the data in an input signal, a command register for storing the command in an input signal, and an error state in each input signal According to the ECC, and the control signal that flows through the control transmission channel for correcting relates to a fresh chip structure and different methods of operation thereof, it characterized in that it comprises a multiplexer for selecting the respective register.

Description

Serial access interface method and fresh chip structure

The present invention relates to a structure of a fresh memory used as a storage device in a central processing unit and another access method thereof. In particular, it is possible to induce a reduction in the number of chip pins through serial access and is convenient for a user who wants to control a memory chip. It relates to a serial access interface method and a fresh chip structure to provide a.

In addition, the present invention is to increase the life time of the chip using the ECC.

In general, as shown in FIG. 1, in order to perform an operation of writing or reading data from the microprocessor 10 to the storage device 20 composed of memory elements, that is, to perform an access operation. In order to supply the voltage indicated by VPP, VDD, VSS, etc. in FIG. 1 from the outside of the storage device 20, or by using an internal voltage pumping circuit with an internal voltage pumping circuit with a capacitor depending on the outside. High voltage such as VDD and VDD should be used.

Therefore, in recent years, the chip density in the same area has been greatly improved due to the reduction of design rules. However, in the conventional method as described above, since the internal voltage pumping circuit must occupy a certain area regardless of the density of the memory cells, the chip density is considerably increased. There was a problem that affects.

In addition, there is a problem that the reliability may be deteriorated in the stability when using a voltage introduced from the outside.

An object of the present invention for solving the above problems is to induce a reduction in the number of chip pins through serial access and serial access interface method and fresh chip structure to provide convenience to the user who wants to control the memory chip To provide.

In addition, the present invention is to increase the life time of the chip using the ECC.

1 is an exemplary configuration diagram for a conventional fresh chip access.

2 is an exemplary configuration diagram for a fresh chip access according to the present invention.

3 is an exemplary fresh chip configuration according to the present invention.

A feature of the present invention for achieving the above object is a fresh memory system comprising a microcontroller and a stage device, wherein a predetermined number of control transmission paths for selecting a clock pin adjustment for driving a device between the microcontroller and the stage device are provided. And data transmission paths for address, command and data input and paths for data output, wherein the stage device can store data along the control signal and data signal input through the paths. A general purpose register, an address register for storing the address among the input signals, a data register for storing the input data, a command register for storing the command among the input signals, and a respective one of the input signals. In accordance with a control signal that flows through the ECC, and the control for correcting the transmission path to restore the state to contain the mux to select the respective registers.

Another feature of the present invention for achieving the above object is a predetermined number of control transmission paths for selecting a clock pin adjustment for driving a device between a microcontroller and a stage device, and data transmission for address or command and data input. A method of operating in a fresh memory system configured to be connected to paths and paths for outputting data, the method comprising: a first process of generating data in a serial manner together with a control signal from the microcontroller; A second process of recognizing a bit signal having a predetermined size among serial data as a selection signal of a specific memory chip; and a predetermined size of data continuously input through the first process after recognizing a specific memory chip through the second process A third process of recognizing a bit signal of a specific command; A fourth step of recognizing a specific command in step 3 and recognizing a bit signal having a predetermined size depending on the size of the stage device among the data continuously input through the first step as an address signal, and the fourth step And a fifth process of recognizing the address through the first process and recognizing a bit signal having a predetermined size as data among the data continuously input through the first process.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a proposed embodiment according to the present invention, and is largely composed of a microcontroller 100 and a stage device 200. The stage device includes control pins OS0 to OS2 for selecting a clock pin adjustment (operation) for driving the device, an address, a command (command), and pins P0 for data input. ~ P7) and pins D0 and D1 for data output.

As shown in FIG. 3, the internal configuration of the stage device 200 includes a mux 210 for selecting each register according to a control signal flowing through the control pins OS0 to OS2. do.

The mux 210 transmits data to the chip select register 220, the address register 230, the command register 240, and the data register 270 according to data flowing through the control pins OS0 to OS2. It forms a path for transmission and enables the ECC 260. On the other hand, there is a general-purpose register 290 capable of storing data along the input of the control signals OS0 to OS2 and the data signals P0 to P7.

Looking at the configuration in which the path according to the data transmission is formed by the mux 210 to operate, the first operation register is a chip select register 220 is composed of 8-bit. Also, the second operation register is the command register 240, which is also composed of 8-bits. The third operation register is an address register 230, the size of which is dependent on the size of the stage device. The fourth operation register is the data register 270, which is entirely dependent on the design and has no size limit.

On the other hand, a high voltage pumping part is provided inside the stage device to generate a voltage necessary for storage and deletion.

Referring to the operation of the fresh chip structure according to the serial access interface method according to the present invention configured as described above, the driving of the stage device starts from the chip selection.

The microcontroller 100 sets the signal level supplied to the control pins OS0 to OS2 (hereinafter omitted) to (1,1,1) to select the stage devices 200A-200N and simultaneously the data input pins P0 to Set the chip select address in P7).

Data entered through the control pins and the data input pins are stored in the general register 290. The chip select register 220 is selected by a portion of the data stored in the general register 290 (control signal data), and the chip select address 220 is stored.

As described in the above operation, a clock select cycle is required for the chip select register to be selected and the chip select address to be transferred. In order to select a specific register from the general purpose register and to transmit data, one clock cycle is necessary. Recall that the mux 210 has been operated to establish a path to the chip select register. Two cycle clocks are always required to select one stage device. The operation performed after two clock cycles is an error correction code (ECC) related operation.

The ECC is a Reed-solmon ECC.

An ECC related operation is an operation of determining (n, k, t). The control signal is (1, 1, 0). n is the data length in which read / write data includes an equivalent value, and k is the length of read / write data. In addition, t is a factor that determines the ECC's calibration capability.

In the present invention, t = 1 is determined. In addition, the default configuration of length is limited to 8-bit.

Therefore, with reference to the operation of the ECC, the first operation is to determine n. Data is arbitrarily inputted to the control pins (1, 1, 0) and the data input pins P7 to P0. For example, if data enters input pins (0,0,0,1,0,0,0,0), then n = 16 (= 2 ⁵ ).

The second action is to determine k. The control pin will contain (1,1,0) and the data input pin will contain random data. K must always be 2 less than n.

Therefore, t is determined as in the equation

Since t is defined as 1 in the present invention, the size must be smaller than the input data to determine n. Therefore, if n = 16 is determined as described above, the data input for determining k should be (0, 0, 0, 0, 1, 1, 1, 0). That is, k = 14.

With respect to ECC, n and k are limited by the value of the data input pins (P7 to P0). In addition, the clock required in ECC is a total of four cycles. Also, n and k are limited by system configuration or stage device data register size. When the operation is completed in relation to ECC, an operation of applying an address is performed. (1,0,1) is applied to the control pin to apply the address.

The address entered through the data input pins is passed to the address register. The size of the address register is determined by the density of the stage device. The number of cycles associated with the address is determined by the number of address register bits. If the address register size is 20 bits, the clock needs 6 cycles. Thus, the address bit size entering through the data input pin for six cycles is 24 bits. The most significant bit (= MSB) is ignored.

As a result, 4 bits are ignored from the MSB and only 20 bits are valid. The next step is to select the command register and issue the command, with the control signal at (1,0,0). All possible branches of a command are 256 (= 2 ⁸ ), but not many commands are actually used.

The command consists of user commands and feature commands. The main user commands are Lead Program (= Write) and Delete. The stage device operates according to the instruction register. Depending on the command, the output buffer may be enabled and the high voltage pumping circuit may operate.

The code for the command will be determined by the design.

After entering the command, three modes are entered. The first mode is the lead mode. The read operation is performed internally by the read command. The second mode is the program mode. After the instruction is leaked, save the data to the data register. The size of the data register was not determined.

The data register size depends on the interface. The control signal must be (0,1,1) to load the data to be stored into the data register. On the other hand, the third mode is the delete mode. The mode at this time is the same as the read mode.

The command code must be (1,1,1,1,1,1,1,1) for the operation to start after the read, program, and delete commands are leaked. No operation will be performed in order for the start command 1,1,1,1,1,1,1,1 to flow out.

If the control signal is (0,0,0), all registers are reset.

ECC hardware, on the other hand, works only in read and program modes. On the other hand, there are two data output pins. The reason for limiting the data pins to 2 pins is that they are associated with the interface. For example, if the data register consists of 258-bits, data can be read in synchronization with the clock in 2-bit increments up to the last bit. However, if it is more than 4 pins, the true mode must be done in the last bit unit registered in the clock. That is, data 257 and 258 are read in the last cycle. At that time, the dummy bits 259 and 260 are also read together, which are bits not present in the actual data register.

Providing the serial access interface method and the fresh chip structure according to the present invention operating as described above, the design density has been reduced recently, the chip density in the same area has been improved a lot, but in the conventional method the internal voltage pumping circuit is a memory cell It is necessary to occupy a certain area regardless of the degree of integration, so that the problem of significant influence on chip density can be solved.

Claims (4)

A fresh memory system comprising a microcontroller and a stage device, comprising: a predetermined number of control transfer paths for selecting a clock pin adjustment for driving a device between the microcontroller and the stage device, and for address, command, and data input. And a general purpose register capable of storing data in accordance with input of a control signal and a data signal through the paths, and storing the address among the input signals. An address register for performing; A data register for storing the data among the input signals; A command register for storing the command among the input signals, an ECC for restoring and correcting an error state among the respective input signals, and a mux for selecting each register according to a control signal flowing through the control transmission paths. Fresh chip structure comprising a. The fresh chip structure of claim 1, wherein a high voltage pumping part is provided in the stage device to generate a voltage necessary for storage and deletion, and the high voltage pumping part operates under control of the ECC. The fresh chip structure of claim 1, wherein the mux forms a transmission path of information through various registers provided and enables the ECC. The connection between the microcontroller and the stage device consists of a predetermined number of control transmission paths for selecting clock pin adjustments for driving the device, data transmission paths for address or command and data input, and paths for data output. A method of operating in a fresh memory system, comprising: a first process of generating data in a serial manner together with a control signal from the microcontroller; A second process of recognizing a bit signal having a predetermined size among serial data generated in the process as a selection signal of a specific memory chip; A third process of recognizing a specific memory chip through the second process and recognizing a bit signal having a predetermined size among data continuously input through the first process as a specific command; A fourth process of recognizing a specific command through the third process and recognizing, as an address signal, a bit signal having a predetermined size depending on the size of the stage device among data continuously input through the first process; And a fifth process of recognizing an address through the fourth process and recognizing a bit signal having a predetermined size as data among the data continuously inputted through the first process.

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