KR100244507B1 - Real time/equivalent time analysis circuit for dut - Google Patents

Abstract

The present invention relates to a technology for analyzing a clock output from a device under test (DUT) in real time or at an equivalent time, and outputs the data from DUT to DC without sequentially performing real time analysis and synchronous time analysis. In order to perform a real time analysis or a synchronous time analysis according to the comparison result by comparing the clock signal with the reference signal, the de-utility (1) for generating a clock signal (CLK) having an arbitrary cycle as a test equipment to be measured. )Wow; Analysis of the DCP 2A that reads the clock signal CLK at a predetermined DCP rate, the real time analyzer 2B and the DCP 2A that check the analysis result of the DCP 2A in a real time domain. In Deuit's analysis circuit comprising an equivalent time analyzer (2C) that checks the result in the equivalent time domain, the clock signal (CLK) is counted for a predetermined time, and the count value is compared with a preset reference value. Accordingly, the real time analyzer 2B includes a real time / equivalent time analysis determining unit 3 that enables the real time analyzer 2B or the equivalent time analyzer 2C.

Description

Deuit's real-time / equivalent time analysis judgment circuit

The present invention relates to a technique for analyzing a clock output from a device under test (DUT) in real time or at an equivalent time. Particularly, a clock signal generated in a deuite is compared with a reference signal in a determination circuit, and the comparison result. The present invention relates to Deity's real-time / equivalent time analysis judgment circuit for determining whether to perform real-time analysis or equivalent time analysis based on the above.

FIG. 1 is a block diagram of Deuit's real-time / equivalent time analysis determination circuit according to the prior art. As shown in FIG. 1, Deuit (1) generating a clock signal CLK having an arbitrary cycle as a test equipment to be measured. )Wow; A digital capture processor (DCP) 2A which reads the clock signal CLK at a predetermined DCP rate; A real time analyzer 2B for checking the analysis result of the DC 2A in a real time domain; It is composed of an equivalent time analyzer 2C for checking the analysis result of the DC 2A in the equivalent time domain, the operation thereof will be described with reference to FIGS. 2 to 4 as follows.

When the clock signal CLK having an arbitrary cycle is output from the clock output pin of the deut 1, the DC2A reads the clock signal CLK at a predetermined DCP rate.

For example, FIG. 2A shows a clock signal CLK having a cycle time of A. FIG. 2B shows that the DC 2A sets the data value of the clock signal CLK to 5 ns. It was read at DCP rate. In this case, the DC 2A reads a data value of "1" or "0" every 5 ns. In this case, when the DCP rate is set to 5 ns time, the read data has an error region of 5 ns time.

If A has a sufficient cycle time (i.e. the output frequency is low), then real-time analysis such as the above method is not greatly affected. For example, if the DCP rate is 5ns and 20,000 pieces of data are obtained, the cycle of the clock signal CLK is 100. μs (10 KHZ), and an error region of 5 ns is not a limitation in determining the cycle of the clock signal CLK.

However, if A has a short cycle time (i.e., the output frequency is high), then the equivalent time analysis must be captured by capturing the data in consideration of the time resolution of the DeU 1. For example, assuming a DCP rate of 5 ns and 10 1-period data are obtained, the cycle of the clock signal CLK has a value of approximately 50 ns (20 MHz), where 5 ns of the error region represents the clock signal CLK cycle. There is a limit to the decision.

Thus, as shown in FIG. 3, one data is sampled every "per cycle time + test equipment time resolution time" as shown in FIG. 3, and the sampled data is brought to the equivalent time domain to analyze the output clock signal CLK. do.

(A) and (b) of FIG. 3 show an example in which the DCP rate is set to 50 ns (assuming 10 are obtained) + 100 PS (time resolution of arbitrary Deuity), and FIG. 4 shows the DCP rate in the equivalent time domain. Each sampled data is shown.

However, in the conventional DUTTI clock signal analysis technique, the analysis of the equivalent time domain is performed when the analysis of the clock signal cycle is difficult by performing the real time domain analysis first. There was a hassle along.

Therefore, the technical problem to be achieved by the present invention is to compare the clock signal output from the deuit with the reference signal in the real-time / equivalent time analysis determiner, and to perform a real-time analysis or equivalent time analysis according to the comparison result It is to provide a real-time / equivalent time analysis judgment circuit of Deuty.

1 is a block diagram of Deuit's real time / equivalent time analysis determination circuit according to the prior art.

Figure 2 (a), (b) is a waveform diagram of an embodiment of the clock signal, DCP sampling clock signal in Figure 1;

3A and 3B are other exemplary waveform diagrams of a clock signal and a DCP sampling clock signal in FIG. 1;

4 is an exemplary diagram of data sampled for each DCP rate in the equivalent time domain in FIG. 1; FIG.

Figure 5 is an exemplary block diagram of a real-time / equivalent time analysis determination circuit of the present invention Deuity.

FIG. 6A is a waveform diagram of a clock signal in FIG. 5; FIG.

6B is an output waveform diagram of the monostable multivibrator in FIG. 5.

*** Description of the symbols for the main parts of the drawings ***

1: DIUT 2: DC Skin

2A: DC 2B: Real Time Analyzer

2C: Equivalent Time Analyzer 3: Real-time / Equivalent Time Analysis Determination Unit

3A: Monostable Multivibrator 3B: N-Bit Counter

3C: Comparator 3D: Flip-Flops

FIG. 5 is a block diagram illustrating an exemplary real-time / equivalent time analysis determination circuit of Diuity for achieving the object of the present invention. As shown in FIG. Deuit (1) generating (1); A DC2A for reading the clock signal CLK at a DCP rate of a predetermined time; A real time analyzer 2B for checking the analysis result of the DC 2A in a real time domain; An equivalent time analyzer 2C for checking an analysis result of the DC 2A in an equivalent time domain; Real time / counting the clock signal CLK for a predetermined time, comparing the count value with a preset reference value, and enabling the real time analyzer 2B or enabling the equivalent time analyzer 2C according to the comparison result. Equivalent time analysis determination section (3) was configured.

The real time / equivalent time analysis determining unit (3) includes a monostable multivibrator (3A) for outputting a "high" signal for a predetermined time in synchronization with the clock signal (CLK); An N-bit counter (3B) for counting the number of clocks of the clock signal (CLK) while the "high" signal is output from the monostable multivibrator (3A); Compares the count value CNT of the N-bit counter 3B with a preset reference value Ref, and outputs a "high" signal when the count value CNT of the N-bit counter 3B is equal to or greater than. A comparator 3C for outputting a "low" signal when not in use; It consists of a flip-flop 3D which enables the equivalent time analyzer 2C or enables the real-time analyzer 2B according to the output signal of the comparator 3C and the output signal of the monostable multivibrator 3A. When described in detail with reference to Figure 6 attached to the operation of the present invention configured as described above are as follows.

A clock signal CLK as shown in FIG. 6A output from the deety 1 is supplied to the DC unit 2 on the one hand, and the clock signal CLK to which the DC 2A is input is predetermined. Will be read at the DCP rate.

On the other hand, the clock signal CLK is supplied to the trigger input terminal TRI of the monostable multivibrator 3A and the clock terminal CK of the N-bit counter 3B.

)와 플립플롭(3D)의 리세트단자(

)측으로 출력하게 되는데, 그 "하이" 구간(T)은 내부의 저항과 콘덴서 값을 조정하여 조절할 수 있다.Accordingly, the monostable multivibrator 3A generates a signal having a "high" section for a predetermined time T as shown in FIG. 6B in synchronization with the clock signal CLK, and the N-bit counter (3B) clear terminal (

) And reset terminal of flip-flop (3D)

), And the "high" section (T) can be adjusted by adjusting the internal resistance and capacitor values.

For this reason, the N-bit counter 3B counts the clock signal CLK output from the de utility 1 during the "high" period T, and the count value CNT of the comparator 3C is counted. Supply to the inverting input terminal.

The comparator 3C compares the count value CNT of the N-bit counter 3B with a reference value Ref supplied to the inverting input terminal, and the count value CNT is greater than or equal to the reference value Ref. In the same case, a "high" signal is output to the set terminal S of the flip-flop 3D. Otherwise, a "low" signal is output.

)와 등가시간 분석기(2C)의 인에이블단자(EN)에 각기 공급되고, 이에 의해 그 등가시간 분석기(2C)가 인에이블된다. 따라서, 이때, 상기 디씨피(2A)의 클럭신호(CLK) 분석결과를 등가시간 분석기(2C)가 체크하게 된다.Accordingly, when the count value CNT is greater than or equal to the reference value Ref, a "high" signal is output from the output terminal Q of the flip-flop 3D, so that the real-time analyzer 2B in the DC skin 2 is output. Enable terminal (

) And the enable terminal EN of the equivalent time analyzer 2C, respectively, thereby enabling the equivalent time analyzer 2C. Therefore, at this time, the equivalent time analyzer 2C checks the clock signal CLK analysis result of the DC 2A.

However, when the count value CNT is smaller than the reference value Ref, since the "low" signal is output from the output terminal Q of the flip-flop 3D, the real time analyzer 2B is enabled at this time. The real time analyzer 2B checks the clock signal CLK analysis result of the DCP 2A.

Thereafter, when the "low" signal starts to be output from the monostable multivibrator 3A, the N-bit counter 3B is thereby cleared, and the flip-flop 3D is reset.

As described in detail above, the present invention does not sequentially perform real-time analysis and synchronous time analysis, and compares a clock signal output from DC to DC with a reference signal to perform real-time analysis or synchronization according to the comparison result. By doing time analysis, the analysis can be simplified.

Claims (2)

A test equipment to be measured, which comprises: a deity 1 for generating a clock signal CLK having an arbitrary cycle; Analysis of the DCP 2A that reads the clock signal CLK at a predetermined DCP rate, the real time analyzer 2B and the DCP 2A that check the analysis result of the DCP 2A in a real time domain. In Deuit's analysis circuit comprising an equivalent time analyzer (2C) that checks the result in the equivalent time domain, the clock signal (CLK) is counted for a predetermined time, and the count value is compared with a preset reference value. Deuit's real-time / equivalent time analysis determination circuit comprising a real-time / equivalent time analysis determining unit 3 for enabling the real-time analyzer 2B or enabling the equivalent time analyzer 2C. . 2. The apparatus of claim 1, wherein the real-time / equivalent time analysis determiner (3) comprises: a monostable multivibrator (3A) for outputting a "high" signal for a predetermined time in synchronization with the clock signal (CLK); An N-bit counter (3B) for counting the number of clocks of the clock signal (CLK) while the "high" signal is output from the monostable multivibrator (3A); Compares the count value CNT of the N-bit counter 3B with a preset reference value Ref, and outputs a "high" signal when the count value CNT of the N-bit counter 3B is equal to or greater than. A comparator 3C for outputting a "low" signal when not in use; A flip-flop 3D which enables the equivalent time analyzer 2C or enables the real time analyzer 2B according to the output signal of the comparator 3C and the output signal of the monostable multivibrator 3A. Deuit's real-time / equivalent time analysis judgment circuit.

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