KR100243507B1 - Clock recovery circuit using digital loop - Google Patents

Abstract

The present invention is configured to operate at 0.5 times the clock frequency for each of the signals read from the magnetic recording and tape using two digital loop loops, reducing the computational burden and wide lock range and input signal due to the extended linear phase characteristics You will not be affected by the power.

Description

Clock Recovery Circuit Using Digital Tan Loop

1 is a circuit diagram showing a conventional clock recovery.

2 is a circuit diagram showing a clock recovery according to the present invention.

<Explanation of symbols for main parts of drawing>

1: input signal part 2: first threshold detector

3: first sampler 4: phase shifter

5: second sampler 6: first phase detector

7: first threshold detector 8: third sampler

9: fourth sampler 10: first phase detector

11: loop filter 12: digital clock generator

13: delay unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit using a digital tango loop. In particular, a digital tango loop that is not affected by the power of an input signal is used to correct data by using the input as it is without taking the square or absolute value of the input signal. A clock recovery circuit using a digital loop loop for detecting at a time point.

In general, in order to recover a clock using a signal read from a magnetic recording tape and a signal recorded using the PR4 method, a baseband signal is used to demodulate a baseband signal among frequency-modulated carriers by taking a square value or an absolute value of an input signal. Clock recovery is performed using the feedback loop as a phase locked loop input. In addition, clock recovery is performed by using two threshold detectors and a phase detector in order not to take the square or absolute value of the input signal.

FIG. 1 is a circuit diagram showing a conventional clock recovery, in which each signal passing two thresholds is divided into a + signal and a-signal, and passes through an edge detector and a phase detector. Through the charge pump to amplify the oscillation frequency by the voltage signal of the loop filter (loop filter) acts as an input signal of the voltage controlled oscillator (Volco Controlled Oscillator, VCO) that is an oscillator whose oscillation frequency changes with the change of the applied voltage. Data is detected at the correct time by using the clock signal generated by the voltage controlled oscillator.

In the magnetic recording channel, the power of the reproduction signal decreases rapidly as the data recording speed increases. Therefore, since the conventional clock recovery apparatus is affected by the power of the input signal, there is a limit to the clock recovery performance in the case of high density recording. In addition, clock recovery is performed by using two threshold detectors and a phase detector to avoid square or absolute value of the input signal, but it is sensitive to power change due to mutual interference of the input signal in high density recording.

In order to solve the above problems, an object of the present invention is to reduce the burden of digital operation by using two digital loop loops without a circuit taking an square or an absolute value of an input signal for clock frequency generation.

The present invention provides a first threshold detector for passing a positive signal in an input signal unit for inputting a signal, and a first sampler used as an input of a first phase detector in the first threshold detector. A phase shifter for shifting a phase in the first threshold detector, a first phase detector for adding a second sampler used as an input of a first phase detector in the phase shifter, and a signal of the first sampler and the second sampler; A second threshold detector for passing a negative signal through the input signal unit, a phase shifter for shifting a phase in the second threshold detector, and a third sampler used as an input of a second phase detector in the phase shifter; And a fourth sampler used as an input of a second phase detector in the second threshold detector, a second phase detector that sums signals of the third sampler and the fourth sampler, and the first phase. And a loop filter for adding signals from a detector and a second phase detector, a digital clock generator for generating a digital clock in the loop filter, and a delay unit for generating a rising edge signal by delaying data in the digital clock generator. do.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a circuit diagram illustrating a clock recovery according to the present invention, which is used as an input of a first phase detector through a first threshold detector 2 for passing a positive signal in an input signal section 1 for inputting a signal. It is output to the first sampler 3. The signal is shifted by 90 ° by a phase shifter 4 which shifts the phase, and passes through a second sampler 5 used as an input of the first phase detector. The signal of the first sampler and the second sampler is summed. It is output to the first phase detector 6. Next, the phase shifter 4 shifts the phase by 90 ° through the second threshold detector 7 through which the negative signal is passed by the input signal unit 1 to the input of the second phase detector. Output to the third sampler 8 used. The first phase by a second phase detector 10 which sums the signals of the third sampler and the fourth sampler through a fourth sampler 9 used as an input of the second phase detector in the third sampler 8; It passes through the loop filter 11 that sums the signals of the detector and the second phase detector, and outputs the delayed signal 13 to the delay unit 13 where the rising edge signal is generated by delaying the data through the digital clock generator 12 in which the digital clock is generated. .

The present invention is not affected by the power change due to the interference of the input signal which is prominent in the high density recording, and detects the data at the right time by using the input as it is without taking the square or absolute value of the input signal. In addition, two digital tango loops are used to operate at 0.5 times the clock frequency for each, reducing the computational burden of the digital tango loops, and the digital tango loops have a wide lock range input signal due to the extended linear phase characteristic. Because it is not affected by the power and has robustness against the noise of the input signal, it can show better performance than using a digital phase locked loop (DPLL).

Claims (3)

A first threshold detector for passing a positive signal in an input signal section for inputting a signal, a first sampler used as an input of a first phase detector in the first threshold detector, and a phase in the first threshold detector A phase shifter for moving a signal, a first phase detector for adding the signals of the first sampler and the second sampler, the second sampler used as an input of the first phase detector, and a negative signal at the input signal part A second threshold detector for passing a phase, a phase shifter for shifting a phase in the second threshold detector, a third sampler used as an input of a second phase detector in the phase shifter, and a second threshold detector A fourth sampler used as an input of a second phase detector, a second phase detector that sums the signals of the third sampler and the fifth sampler, and a signal of the first phase detector and the second phase detector And a digital clock generator for generating a digital clock in the loop filter, and a delay unit for generating a rising edge signal by delaying data in the digital clock generator. . The clock recovery circuit according to claim 1, wherein the phase of the phase shifter is shifted by 90 degrees. The clock recovery circuit of claim 1, wherein the delay unit delays by 1/2 times a bit duration.