KR100242843B1 - Apparatus and method for coding error generated while processing sync. signal - Google Patents

Abstract

The present invention relates to an error operation encoding apparatus and method generated during synchronization signal processing. The present invention relates to a horizontal sync signal and a vertical sync signal output from a video card, and to a resolution determined by receiving an applied horizontal sync signal and a vertical sync signal. Micom with a built-in sync signal error processing program that codes an error signal generated when an error occurs in the discrimination operation, and occurs when a sync signal error occurs in the micom. Compatibility of video card and display monitor which is composed of an error code part to receive and store the error code that is output by coding the error signal that has been output. The reason for the cause of the sync signal error is that the error generated when the sync signal error occurs can be coded and output. There is a more effective for efficiently resolved.

Description

An apparatus and method for encoding error behavior generated during synchronization signal processing

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error operation encoding apparatus and method generated in synchronizing signal processing, and more particularly to an error caused by a problem with compatibility with a display monitor receiving and processing a synchronizing signal for synchronizing image data generated from a video card. The present invention relates to a coding apparatus and a method capable of monitoring an error factor generated by coding a content.

In general, a display monitor is designed to process data generated from a personal computer (hereinafter, referred to as a PC) as an image signal and maintain compatibility with a video card that generates and outputs a synchronization signal for synchronizing the processed image signal. . In other words, the video cards currently in use vary greatly in their types and manufacturers, and display monitors must be compatible with all these video cards to perform normal operations. When the display monitor and the video card are not compatible with each other, the microcomputer configured in the display monitor cannot handle this, and a lot of time and effort have been required to review and prepare countermeasures. Furthermore, there is a problem that the dissatisfaction factor of the product occurs in the display monitor product market due to the delay in establishing such measures.

Therefore, in order to solve the above-mentioned problem, the present invention utilizes a microcomputer installed in a display monitor to convert an error history according to a compatibility problem generated when a compatibility-related problem occurs with a video card to generate an error code. It is an object of the present invention to provide an apparatus and method for encoding an error operation generated during synchronization signal processing for reading a code.

In order to achieve the above object, the present invention provides a horizontal synchronizing signal and a vertical synchronizing signal output from a video card, and receives an applied horizontal synchronizing signal and a vertical synchronizing signal to determine a resolution and an error occurs in a discrimination operation. The microcomputer has a built-in synchronization signal error processing program that codes the error signal generated when the error signal is generated, and an error signal generated when a synchronization signal error occurs in the microcom It is characterized in that it consists of an error code (Error code) for receiving and storing the error (Error) to be output by the code).

Another feature of the present invention is an error code analysis step of analyzing an error generated when a PLL does not operate normally in a PLL normal operation determination step or a signal cable is normally connected in the signal cable connection determination step. And an error code generation step of generating a code when an analysis of an error generated in the error code analysis step is completed, and an error code generation step of generating an error code. It consists of an error code storage step for storing the error code (Error code).

1 is a block diagram of an internal circuit of a display monitor to which an error code unit according to the present invention is applied.

FIG. 2 is a detailed circuit diagram of an error code section shown in FIG.

3 is a flowchart illustrating an error codeization method according to the present invention.

The present invention will be described with reference to the accompanying drawings.

As shown in FIG. 1, the error operation coding apparatus according to the present invention includes a CPU 11 that executes a program and generates data according to the result of execution, and data that is applied with data generated from the CPU 11 To generate and output a horizontal synchronizing signal H-SYNC and a vertical synchronizing signal V-SYNC for synchronizing the image signals R, G, and B to synchronize the processed image signals R, G, and B. The resolution of the image signals R, G, and B is determined by receiving the video card 12 and the horizontal sync signal H-SYNC and the vertical sync signal V-SYNC outputted from the video card 12. When an error occurs during the discrimination operation, the microcomputer 21 incorporating a synchronization signal error processing program that codes the generated error signal into a code, and is output from the microcomputer 21. Horizontal and vertical oscillation by receiving horizontal and vertical reference oscillation signal and phase adjustment signal A horizontal and vertical oscillator 22 for outputting a pulse and a horizontal and vertical oscillation pulse output from the horizontal and vertical oscillator 22 are detected, and a state of the detected oscillation pulse is applied to the microcomputer 21 so as to be horizontal. And a phase-locked loop state detector 23 for correcting and outputting a vertical reference oscillation signal, and horizontal and vertical oscillation pulses output from the horizontal and vertical oscillator 24. Coded and output the error signal generated when the synchronization signal error occurs in the microcom 21 and the horizontal and vertical deflection unit 24 for generating the horizontal and vertical sawtooth wave currents. An error code unit 25 for receiving and storing the received error code, general OSD data output from the microcomputer 21, or an error output from the error code unit 25; Code OSD The OSD unit 26 for receiving the data and processing the applied OSD data to output an OSD gain signal, an OSD gain signal output from the OSD unit 26 and an image signal R output from the video card 12. And a video circuit 27 for selectively amplifying and outputting G, B), an image signal R, G, B and an OSD gain signal output from the video circuit 27, and receiving the horizontal and vertical signals. It consists of CRTs 28 which display images in synchronization with the horizontal and vertical sawtooth wave currents output from the deflection section 24.

Referring to the operation according to the configuration as follows.

The CPU 11 of the PC 10 executes a program according to a user's command and applies data to the video card 12 according to the result of the execution. The video card 12 receiving the data generated by the CPU 11 processes the applied data into the image signals R, G, and B and outputs the processed result. At this time, the video cards R, G, and G output horizontal and vertical synchronization signals H / V-SYNC for synchronizing the image signals R, G, and B.

The horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V-SYNC output from the video card 12 of the PC 10 are received and processed by the microcomputer 21 mounted in the display monitor 20. The microcomputer 21 receives the applied horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V-SYNC, and determines information included in the image signals R, G, and B output from the video card 12. Therefore, various phase adjustment signals and horizontal and vertical oscillation signals according to the resolution of the image signals R, G, and B are output.

The phase adjustment signal output from the microcomputer 21 is converted into an analog signal through a means (not shown) for converting a digital signal into an analog signal and applied to the horizontal and vertical oscillator 22. The horizontal and vertical oscillator 22 receiving the phase adjustment signal converted into the analog signal receives the horizontal and vertical reference oscillation signals applied from the microcomputer 21 to output the horizontal oscillation pulses and the vertical oscillation pulses.

At this time, the output state of the horizontal and vertical oscillation pulses output from the horizontal and vertical oscillator 22 is detected by the PLL state detector 23. The PLL state detection unit 23 that detects the output states of the horizontal and vertical oscillation pulses corrects and outputs the horizontal and vertical reference oscillation signals output from the microcomputer 21 to stabilize the output of the detected horizontal and vertical oscillation pulses. do. Horizontal and vertical deflection parts receiving horizontal and vertical oscillation pulses output from the horizontal and vertical oscillation parts 22 that receive and process the horizontal and vertical reference oscillation signals output from the microcomputer 21 when the output of the horizontal and vertical oscillation pulses changes. Reference numeral 24 generates a sawtooth wave in accordance with the applied horizontal oscillation pulse and the vertical oscillation pulse.

On the other hand, the video signal (R, G, B) output from the video card 12 of the PC 10, the video circuit 27 amplifies the applied video signal (R, G, B) to the CRT (28) Will be authorized. The video circuit 27 that receives and amplifies and outputs the image signals R, G, and B is selected by the microcomputer 21 and processed by the OSD unit 26 when normal OSD data is generated. The video circuit 27 receiving the OSD gain signal output from the OSD unit 26 output when the OSD is selected, amplifies the applied OSD gain signal and applies it to the CRT 28.

Amplifying the OSD signal and the image signal (R, G, B) through the video circuit 27, the CRT 28 receives the applied OSD signal and the image signal (R, G, B) horizontal and vertical deflection ( It is displayed according to the OSD by deflecting according to the sawtooth current generated and applied in 24). At this time, if the video card 12 mounted in the PC 10 and the display monitor 20 are not compatible with each other, the horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V- outputted from the video card 12 are not compatible with each other. When the SYNC is processed in the microcomputer 21 mounted in the display monitor 20, a synchronization signal processing error occurs. The generated error is coded for the generated error by executing the synchronization signal error processing program stored in the microcomputer 21.

For example, when the video card 12 which processes data generated in the PC 10 as an image signal is not compatible with the display monitor 20, the display monitor 20 may display an error when the system is installed. Is generated.

As such, an error generated by the incompatibility between the video card 12 and the display monitor 20 is generated in the microcomputer 21. The microcomputer 20 executes the synchronization signal error processing program according to the generated error. When the synchronization signal error processing program is executed, an error signal generated by the microcomputer 20 is converted into a constant format. That is, it converts the error signal to binary or other data storage code.

The code corresponding to the converted error signal is applied to the error code unit 26 and stored. The stored error code applies an error code from the OSD unit 26 according to a read control signal applied through the microcomputer 21 during A / S. The OSD unit 26 receiving an error code signal outputs an OSD signal according to an error code by processing the applied error code. The OSD signal according to the output error code is amplified by the video circuit 27 to display an image through the CRT 28.

The OSD information according to an error code displayed on the screen of the CRT 28 may be displayed using its own raster. In this way, the OSD screen displayed on the CRT 28 screen makes it easy to analyze the cause of the error generated in the microcomputer 21. The error code unit 25 will be described in more detail with reference to the accompanying drawings.

As shown in FIG. 2, the horizontal sync signal H-SYNC and the vertical sync signal V-SYNC output from the video card 12 (shown in FIG. 1) are applied and the horizontal sync signal H-SYNC is applied. ) And a horizontal sync signal output from the buffer stage 21a for shaping the waveform of the vertical sync signal V-SYNC or removing noise. (H-SYNC) and vertical sync signal (V-SYNC) are applied to determine the resolution and if an error occurs during the discrimination operation, a sync signal error (Code) of the generated error signal (Code) Error) The microcomputer 21 incorporating the program and the horizontal and vertical oscillator 22 which outputs the horizontal and vertical oscillation pulses by receiving and processing the horizontal and vertical reference oscillation signals and the phase adjustment signals output from the microcomputer 21. ) And the horizontal and vertical output from the horizontal and vertical oscillator 22 The PLL state detection unit 23 detects the state of the vertical oscillation pulse and applies the state of the detected oscillation pulse to the microcomputer 21 to correct and output horizontal and vertical reference oscillation signals. An error code storage unit 27-1 and the error code for receiving and storing an error code that is output by encoding an error signal generated when a signal error occurs. Error code An error composed of a communication port 27-2 that receives and outputs a read control signal output from the microcomputer 21 when an error code stored in the storage unit 27-1 is required. It consists of an error code part 27, control diodes ZD1 and ZD2, and a plurality of resistors R1-R4.

Referring to the operation according to the configuration as follows.

First, the horizontal synchronizing signal H-SYNC output from the video card 12 is corrected to a signal of a predetermined level through the control diode ZD1 and the resistor R1, and thus the buffer stage 21a. Is applied. In addition, the vertical synchronizing signal V-SYNC is corrected to a signal of a predetermined level through the zener diode ZD2 and the resistor R2 and applied to the buffer stage 21a. The buffer stage 21a receiving the horizontal and vertical synchronization signals H / V-SYNC is formed by shaping the applied horizontal and vertical synchronization signals H / V-SYNC and removing noise. Organic to (R3, R4) is applied to the microcomputer 21. The microcomputer 21 receiving the horizontal and vertical synchronization signals H / V-SYNC determines the resolution of the image signal by determining the frequency according to the applied signal.

The microcomputer 21 for determining the resolution of the video signal outputs various phase adjustment signals according to the determined resolution. In addition, horizontal and vertical oscillation signals are generated and output together with the phase adjustment signal. The output phase adjustment signal and the horizontal and vertical reference oscillation signals are output from the horizontal and vertical oscillation units 22 by generating horizontal and vertical oscillation pulses according to the applied signals. At this time, in order to stabilize the output horizontal and vertical oscillation pulses, the PLL state detection unit 23 applies the microcom 21 to the correction signal according to the abnormal variation when an abnormal variation occurs in the output horizontal and vertical oscillation pulses. do.

The microcomputer 21 receiving the correction signal according to the abnormal variation output from the PLL state detection unit 23 corrects the reference oscillation signal according to the applied correction signal and outputs the corrected horizontal and vertical reference oscillation signals to output horizontal and vertical signals. The pulse output through the oscillator 22 is stabilized.

On the other hand, if an error occurs during synchronization signal processing due to PC system installation or program execution, the error signal generated by the synchronization signal error processing program stored in the microcomputer 21 is executed. Code). When the error generated by the synchronization signal processing is coded, the completed code is an error code storage unit of the error code unit 27 according to a storage control command. 27-1). When the storage is completed in the error code storage unit 27-1, the error code stored in the A / S is read. In order to read the error code stored in the error code storage unit 27-1, the microcomputer 21 outputs a read control signal. The output read control signal is applied to the communication port 27-2.

The communication port 27-2 receiving the read control signal reads an error code stored in the error code storage unit 27-2 according to the read control signal. Will print. The output error code is OSD processed through the OSD unit 26 (shown in FIG. 2) and displayed on the CRT 28 (shown in FIG. 2). The OSD information displayed on the CRT 28 makes it easy to find the cause of the error because the cause of the error due to the synchronization signal processing generated in the microcomputer 21 is displayed.

The operation of the synchronization signal error processing program stored in the microcomputer 21 will now be described in detail with reference to FIG. 3.

As shown in FIG. 3, an error code method according to the present invention includes a start step (S11) of executing a PC system installation or a program and generating a video signal according to the result of the execution, and the start. (Start) When the video signal is generated in step S11, the horizontal and vertical synchronization signal checking step (S12) for checking whether a horizontal and vertical synchronization signal for synchronizing the generated video signal has been generated, and the horizontal and vertical synchronization signal checking When the check of the horizontal and vertical synchronization signals is completed in step S12, the normal synchronization signal input determination step S13 for determining whether the normal horizontal and vertical synchronization signals have been input, and the input in the normal synchronization signal input determination step S13 A horizontal and vertical synchronizing signal output enable step (S14) for enabling the output of the horizontal and vertical synchronizing signals if the synchronized signal is a normal synchronization signal; In the horizontal and vertical synchronizing signal output enable step S14, when the horizontal and vertical synchronizing signals are output, the PLL operation state checking step S15 for checking the operation of the PLL and the PLL operation state checking step S15. PLL normal operation determination step (S16) for determining whether the PLL operates normally when the PLL operates, and normal for displaying image data generated by a computer system when the PLL operates normally in the PLL normal operation determination step (S16). It consists of a normal operation step S17 which performs an operation.

At this time, if the normal sync signal is not input, the flow of the operation of connecting the signal cable normally, when the normal sync signal is not input in the normal sync signal input determination step (S13) disables the output of the horizontal and vertical sync signal (Disable) When the horizontal and vertical sync signal output disable step S18 and the output of the horizontal and vertical sync signal are disabled in the horizontal and vertical sync signal output disable step S18, A signal cable connection determination step (S19) for checking whether the signal cable for transmitting the synchronization signal is normally connected, and a message for checking the signal cable if the signal cable is not connected in the signal cable connection determination step (S19) is displayed. Signal cable check output step S20 to output and OS output in the signal cable check output step S20 When the signal cable is normally connected according to the instructions on the screen, the first return step S21 returns to the horizontal and vertical sync signal checking step S12 to check whether the horizontal and vertical sync signals have been input. )

In such a configuration, if an error occurs because a normal synchronization signal is not input even though the signal cable is normally connected, the flow of operation for coding the generated error is the normal operation of the PLL. An error code analysis step S22 for analyzing an error generated when the PLL does not operate normally in the determination step S16 or the signal cable is normally connected in the signal cable connection determination step S19; When the analysis of the error generated in the error code analysis step (S22) is completed, an error code generation step (S23) that generates a code (Code) and the error code (Error code) ) An error code storage step S24 for storing an error code generated in the generation step S23, and an error generated in the error code storage step S24. Code (Co de) when the storage is completed or when the normal operation is executed in the normal operation step S17, the normal synchronization signal is input again or the reprocessing of the synchronization signal is performed again. It is comprised by the 2nd return step S25 which returns to a vertical synchronizing signal inspection step S12.

Through these steps, when the code according to the sync signal error generated when the PC system is installed or the program is executed using the PC is completed, an error code generated when the sync signal is processed is outputted. (Error) It consists of a user interface step S26 which analyzes a cause.

Referring to the flow of operation according to the configuration in more detail as follows.

First, in a start step S11, a user installs a PC system or executes a desired program using a PC. When the user installs the PC system or executes the program using the PC, the synchronization signal error processing program stored in the microcomputer 21 (shown in FIG. 2) is executed by default. As the synchronization signal error processing program is executed by default, the horizontal and vertical synchronization signal checking step S12 checks whether the horizontal and vertical synchronization signals have been generated in the PC 10 (shown in FIG. 2). Done.

When the check is completed, the normal sync signal input determination step S13 determines whether the horizontal and vertical sync signals applied to the display monitor 20 (shown in FIG. 2) are normal sync signals. That is, it is determined whether the horizontal and vertical synchronization signals are compatible with the display monitor 20 or are properly input through the signal cable. As a result of the determination, when the input synchronization signal is normally input, the horizontal and vertical synchronization signals are enabled through the microcomputer 21 by enabling the horizontal and vertical synchronization signals in the horizontal and vertical synchronization signal output enable step S14. And a phase adjustment signal and a horizontal and vertical oscillation signal according to the vertical synchronization signal.

The horizontal and vertical oscillation signals output from the microcomputer 21 are applied and processed by the horizontal and vertical oscillator 22 (shown in FIG. 1) to generate and output horizontal and vertical oscillation pulses. The horizontal and vertical oscillation pulses output are detected in the PLL operation state checking step S15. That is, when the output of the horizontal and vertical oscillation pulses varies, the microcomputer 21 is controlled to output a correction reference oscillation signal according to the output variation. At this time, when the PLL operates normally in the PLL normal operation determination step S16, the image signal generated by the PC 10 is transferred to the CRT 28 (shown in FIG. 2) through the normal operation step S17. Is displayed.

If the normal sync signal is not input in the normal sync signal input determination step (S13) during this operation, the horizontal and vertical sync signal outputs are disabled (Disable) in the step S18. Let's go. When the horizontal and vertical synchronization signals are disabled in the microcomputer 21 in the display monitor 20 in the horizontal and vertical synchronization signal output disable step S18, the signal cable connection determination step S19 is performed. It is checked whether the cable for transmitting the horizontal and vertical synchronization signals output from the PC 10 operates normally.

That is, as the horizontal and vertical synchronization signals are not normally applied, the signal cable determines the connection state or the error of the signal cable. As a result of the determination, when the signal cable is connected and its own error occurs, if the signal cable is normally connected through the signal cable check output step S20 or an error occurs due to a defect of the signal cable itself, The OSD will prompt you to replace it. When the signal cable check operation is completed, the signal returns to the horizontal and vertical sync signal check step S12 through the first return step S21 to check whether an error occurs in the sync signal again. .

In addition, when the PLL does not operate normally or the signal cable is normally connected in the PLL normal operation determination step S16 or the signal cable connection break step S19, the video card 12 (shown in FIG. 2) and the display are displayed. An error occurs due to an incompatibility with the monitor 20 or a defect of the synchronization signal. The generated error is analyzed through an error code analysis step S22. In this case, the error is analyzed according to the type of error generated using a conversion table. When the analysis of the generated error is completed, an error code is generated according to a storage format through an error code generation step S23.

If the code according to the generated error is generated in accordance with the format for storing the data, the error code storage unit 27-1 through the error code storage step S24. (Shown in Figure 3). When the error code is stored in the error code storage unit 27-1, the second return step S25 returns to the horizontal and vertical synchronization signal checking step S12. To check the horizontal and vertical sync signals. This operation is completed and the cause of the synchronization signal error generated in the display monitor 20 is displayed by displaying an error code through the user interface step S26. Find the cause.

That is, an error code stored in the error code storage unit 27-1 is processed as an OSD signal through the communication port 27-2 (shown in FIG. 3) and output through an OSD screen or other error. Output through the display means for displaying the code (Error code) to more easily analyze the error (Error) cause of the synchronization signal.

As described above, the present invention codes and outputs an error generated when a synchronization signal error occurs in a compatibility between a video card and a display monitor that receive data and process the image signal. By doing so, there is an effect of solving the analysis of the cause of the synchronization signal error more efficiently.

Claims (4)

An apparatus for encoding an error operation generated during synchronizing signal processing, comprising: receiving a horizontal synchronizing signal and a vertical synchronizing signal output from a video card, and receiving an applied horizontal synchronizing signal and a vertical synchronizing signal to determine a resolution and an error during a discriminating operation A microcomputer incorporating a synchronization signal error processing program that codes an error signal generated when an error occurs, and an error code that receives and stores the error code. and an error operation coding apparatus generated during synchronization signal processing. According to claim 1, The error code (Error code), Error code (Error code) storage unit for storing the error code (Error code) output from the micom, The error code (stored) stored in the error code (Error code) storage unit An error operation coding apparatus generated during synchronization signal processing, characterized by comprising a communication port (27-2) for outputting an error code. A method of encoding an error operation generated during synchronization signal processing, the method comprising: analyzing an error generated when a PLL does not operate normally in a PLL normal operation determination step or a signal cable is normally connected in the signal cable connection determination step. An error code analysis step, an error code generation step that generates a code when an analysis of an error generated in the step is completed, and an error code generated in the step Error code (Error code) storage step for storing the error signal (Error code), characterized in that consisting of the step of storing a). The method of claim 3, wherein when the code of the synchronization signal error is completed in the error code storage step, the stored error code is output when the synchronization signal error is stored. Error) An error operation coding method generated when processing a synchronization signal, characterized by further adding a user interface step of analyzing a cause.

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