KR100241333B1 - T1/e1 frame relay interworking module - Google Patents

Abstract

The present invention relates to an ATM / frame relay (FR) interworking device capable of implementing the same interworking function at a low cost while accommodating four T1 / E1 links, wherein the present invention relates to a FR connection part (FAP) of a FR interworking module (FRIM) in an ATM switch. As applied, the physical layer connection unit 301 for the physical connection with the four T1 / E1 links and the processor unit 303 directly connected thereto are configured with two processors to accommodate the two T1 / E1 links. In order to temporarily store the frame data received by the processor unit, the packet memory 302 is connected to the system memory 309 through the buffer 304. The FIRL unit 305 is provided for IPC communication and cell bus matching for communication with the multiplexer (MDP) 308 to communicate with the IPC communication unit 306 and the FIFO 307. Accordingly, since the present invention can be implemented at one board level, it is effective for the integration of the entire system, and a relatively inexpensive device can be implemented with a simple circuit configuration, which is low cost and facilitates the development process.

Description

Four T1 / E1 frame relay interlocks in an asynchronous transfer switch

The present invention relates to a subscriber or network matching function implementation technology in an ATM switch, and more particularly, performs an interworking function between a frame relay (hereinafter referred to as "FR") network and an ATM (asynchronous transfer method) network. The present invention relates to a 4 T1 / E1 frame relay interworking device in an ATM exchange that accommodates four T1 / E1 links, which is superior in performance and cost compared to existing interworking devices.

In the early stages of the introduction of ATM into the national network, interworking between ATM networks and existing networks has emerged as an important issue. Among the existing networks, FR networks are used in various fields such as file transfer, database access, e-mail, banking, and video data transmission to provide various bandwidths from 45 Kbps to 45 Mbps, and simple protocol. Compared with ATM, the service has the advantage of being able to provide high speed service at a much lower cost. Accordingly, the FR network is considered as an optimal network as a service providing network that responds to an increase in natural user demands in the intermediate evolutionary stage from the existing network to the ATM network.

However, existing interworking devices accept two T1 / E1 links and are relatively expensive, such as processors, high-speed data link controllers (HDLC), and ATM adaptation layer 5 (AAL5) controllers, to handle the traffic generated. There is a problem that many of the elements must be used.

Therefore, in order to solve the above problems, the present invention is superior in performance and low in cost while accommodating four T1 / E1 links, compared to an existing relatively high cost and ATM / FR interworking apparatus that accommodates two T1 / E1 links. The purpose is to provide an ATM / FR interlock.

1 is a configuration diagram of a frame relay interworking module (FRIM) in an ATM switch to which the present invention is applied;

2 is a block diagram of a conventional interlock device;

3 is a block diagram of a 4 T1 / E1 frame relay interlock according to the present invention;

4 is a detailed block diagram of FIG. 3.

<Explanation of symbols for main parts of drawing>

301: physical layer connection unit 302: packet memory

303: processor unit 304: buffer

305: FIRL unit 306: IPC communication unit

307: FIFO 308: multiplexer (MDP)

309: system memory

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 shows a FR Relay interworking module (FRIM) structure in an ATM switch according to the present invention.

In the FR interworking module 101, the FR connection unit to which the present invention is applied (FAP; FR Access Part) 102 functions to match the T1 / E1 105 and a function of transmitting / receiving a FR frame for each channel and the same. The AAL5 processing function for converting to ATM cell is the main function. The ATM cell is transmitted to the multiplexer through the cell bus 107, and the maintenance information, FR subscriber registration / deletion, FR PVC (permanent virtual access) setting / release, etc. The information communicates with the multiplexer (MDP) 103 via the IPC bus 107 using DPRAM. In the case of SVC (Switched Virtual Connection), the call processing signal is easily distinguished from the user information because DLCI = 0 is input from the FR. The call processing message is also treated as an IPC message and transmitted to the multiplexer through the IPC bus. The multiplexing unit converts the UPC (User Parameter Control) function, VPI (Virtual Path Identifier) / VCI (Virtual Channel Identifier) function, inserts routing information, IMI (module-to-module connection) 108), the function of multiplexing / demultiplexing cells, OAM processing, and the like are the main functions to control the FR connection, and become the IPC master of the FRIM with respect to the upper processor 110. The multiplexer 103 is connected to a connection exchange subsystem (ALS) 109 via IMI. The module clock distribution unit (CDP) 104 receives a network synchronizer clock and generates and distributes a clock required by the multiplexer and the FR connection unit. The function is connected to the ALS using a small coaxial cable.

FIG. 2 shows a block diagram of a FR connection 102, i.e., an existing ATM / FR interlock that accommodates two T1 / E1 links.

A physical layer unit 201 composed of a transformer, a line connector, a frame configurator, and the like for physical connection with two T1 / E1 links and an HDLC processing unit 202 connected thereto are constituted by an HDLC controller, an HDLC control memory, and the like. The processor unit 203 for controlling the entire interlock device uses the Motorola CPU series MC68040 and MC68360 in a peer mode, and is composed of an EPROM, a local SRAM, and the like. A buffer 204 is used to distinguish input and output ports at the processor unit, and a packet memory 205 for storing frame data is connected through the buffer. In addition, a segmentation and reassembly (SAR) processing unit 207 for disassembling or assembling frame data input through the buffer into an ATM cell includes an AAL5 controller, a control memory, a system memory, and the like. There is a bus arbiter 206 for preventing and controlling a collision in the use of a system bus such as the processor unit, the HDLC processor, and the SAR processor. A FIRL (FMDA Interface Reset Logic) for cell communication with the multiplexers 103 and 211 of FIG. There is a unit 209, a FIFO 210, and the like, and there is an IPC communication unit 208 configured as DPRAM for IPC communication with the multiplexing unit.

3 is a block diagram of an interlock device proposed in the present invention.

3 is an interworking device between the ATM network and the FR network applied to the frame relay connection unit (FAP) 102 in the structure of the frame relay interworking module (FRIM) 101 in the ATM switch. Its configuration is to separate high-speed data by separating the four T1 / E1 links connected to the transformer and the physical layer connecting portion 301 for physical connection, and the four T1 / E1 links directly connected to the connecting portion 301 for input. A processor unit 303 for link control, a packet memory 302 for temporarily storing and processing frame data and cell data input and output to the processor unit 303 through a system bus, a processor unit 303 and a FIRL unit ( A buffer 304 for temporarily storing control information input and output to the 305 and a FIRL unit 305 for communicating with the multiplexing unit (MDP) 308 according to the control signal of the processor unit 303. And inter-processor communication (IPC) for communication between the system memory 309 storing control information transmitted between the buffer 304 and the FIRL unit 305, and the FIRL unit 305 and the multiplexer (MDP, 308). ; IPC communication unit 306 and cell bus for inter-processor communication It consists of a first-in first-out buffer (FIFO) 307 for matching.

As shown in FIG. 3, a physical layer connection unit 301 including a transformer, a line interface unit (LIU), a frame configurator, and the like, for physical connection with four T1 / E1 links, and its The processor unit 303 which is directly connected to uses the Motorola Power PC series MPC860SAR. In order to temporarily store the frame data received by the processor unit, the system memory 309 is connected through the buffer 304 with the packet memory 302. A FIRL unit 305 is provided for IPC communication and cell bus matching for communication with the MDP 308 to communicate with the IPC communication unit 306 and the FIFO 307.

4 is a detailed block diagram of the embodiment of FIG. 3.

The physical layer connection unit 301 described above includes first and second line connectors (LIUs) 401 and 411 which are directly connected to a transformer for connecting two T1 / E1 links (that is, 64 channels). And first and second frame configurators 402 and 412 which are connected to form frame data. The processor unit 303 uses the first and second processors 404 and 414 using the MPC860SAR of the Motorola powerPC series to accommodate the four T1 / E1 links. Each processor 404, 414 then first and second time slot assigners 403, 413 for connecting 24 or 32 timeslots in the T1 / E1 link to the SCCs 421, 415, respectively. First and second serial communication controllers (SCCs) connected to each aligner for high-speed data link control (HDLC) of 64 time slots, and first and second UTOPIAs for cell bus matching (at ATM forums). It is defined by the common matching standard between the physical layer and the ATM layer, which is a proper noun) and consists of physical matching units 405 and 416. First and second local memories 406 and 419 are connected to the first and second processors 404 and 414 to receive and store control signals through a system bus, respectively. The FIFO control logic unit 417 in the FIRL unit 305 receives data and control signals from the first and second UTOPIA physical matching units 405 and 416 to receive the reception buffer 418 and the transmission buffer 422. The simultaneous access to the multiplexer 423 is controlled, and the DPRAM control logic unit 409, which is another one, controls information between the first and second buffers 408 and 424 and the first and second EPROMs 407 and 420. In response to the path and the control signal, access to the multiplexer 423 through the DPRAM 410 is controlled.

The first and second processors 404 and 414 described above perform cell bus matching using the AAL5 function and the UTOPIA physical matching function 405 and 416.

Referring to the operation and operation of the present invention according to the above configuration as follows.

Frame data input to the T1 / E1 lines connected to the LIUs 401 and 411 through the transformer pass through the frame configurators 402 and 412. The input frame data is passed through the time slot aligners 403 and 413 to be delivered to the SCCs 421 and 415 responsible for HDLC functions in the processor MPC860SAR 404 and 414. The frame data transferred to the SCC is temporarily stored in the local memory 406 and 419 via the system bus and decomposed into cells by the SAR function in the processor, and the FIFO control logic unit 417 via the UTOPIA physical matching function 405 and 416. The control is transmitted to the transmission FIFO 422 and then transmitted to the MDP side 423. The cell data received from the MDP side 423 in the reverse direction is controlled by the FIFO control logic unit 417 and input through the UTOPIA physical matching functions 405 and 416 in the processor through the reception FIFO 418. The input cell data is reassembled by the SAR function and stored in the local memories 406 and 419 in the form of frame data, and if necessary, the frame data is manipulated and then the SCCs 421 and 415, the frame configurators 402 and 412, and The LIUs 401 and 411 are sent to the T1 / E1 line. S / W to be performed is mainly stored and operated in the EPROM (407, 420), IPC data to be delivered to the MDP side is transmitted and received through the DPRAM (410) under the control of the DPRAM control logic (409, 417).

The present invention as described above is an ATM / FR interworking device that can accommodate 4 T1 / E1 link. In particular, the device can be implemented at a single board level, which is effective for the integration of the entire system, and a relatively inexpensive device can be implemented in a simple circuit configuration, thereby making it low-cost and easy to develop.

Claims (7)

In the interworking device between the ATM network and the FR network applied to the frame relay connection (FAP) 102 for communication with the multiplexing unit (MDP) 103 in the structure of the frame relay interworking module (FRIM) 101 in the ATM switch. , A physical layer connection 301 connected to the transformer for physical connection with four T1 / E1 links; A processor unit 303 for high speed data link control by separating four T1 / E1 links that are directly connected to the connection unit 301 and input; A packet memory 302 for temporarily storing and processing frame data and cell data input / output to the processor unit 303 through a system bus; A buffer 304 for temporarily storing control information input and output to the processor unit 303 and the FIRL unit 305; A FIRL unit 305 for transmitting and receiving data according to a control signal of the processor unit 303 and communicating with a multiplexer (MDP) 308; A system memory (309) for storing control information transferred between the buffer (304) and the FIRL section (305); And An IPC communication unit 306 for inter-processor communication (IPC) for communication between the FIRL unit 305 and the multiplexing unit 308 and a first-in first-out buffer (FIFO) 307 for cell bus matching. 4 T1 / E1 frame relay interlock at the ATM switch. The method of claim 1, The processor unit 303 is 4 T1 / E1 frame relay interworking device in an ATM exchange comprising two first and second processors (404, 414) for controlling four T1 / E1 links (64 channels). The method of claim 1, The FIRL unit 305 is A FIFO control logic section 417 connected to a control signal of a UTOPIA physical matcher of each processor to control simultaneous access to the FIFO section 307 of each processor; And a DPRAM control logic section (409) for controlling access of the processor section (303) to the IPC communication section (410) through the buffer (304). The method of claim 1, The packet memory (302) is composed of two local memory 4 T1 / E1 frame relay interworking apparatus in the ATM switch. The method of claim 1, And said system memory (309) is comprised of two EPROMs. The method of claim 1, The buffer 304 is a 4 T1 / E1 frame relay interworking apparatus in the ATM exchange, characterized in that consisting of two buffers. The method according to claim 1 or 2, The physical layer connection unit 301 is composed of two line connectors 401 and 411 and a frame configurator 402 and 412 for connecting a link to each of the processors. Relay interlock.

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