KR100240732B1 - Methods and apparatus for implementing a media access control/host system interface - Google Patents

Abstract

The present invention relates to an interface system for transferring information between a local area network and a memory system associated with a station attached to the network. The interface system includes a bus interface unit for implementing the transfer of information between the interface system and the memory system. The indicator module transmits the information received by the interface system from the network to the memory system via the bus interface unit. The request module sends the information received by the interface system from the memory system via the bus interface unit to the network. A status generation / space management module connected to the indication module and the request module monitors the status of the indication module and the request module, generates a corresponding status signal, and transmits information between the network and the memory system via the interface system. Manage the allocation of storage space in the memory system.

Description

METHOD AND APPARATUS FOR IMPLEMENTING MEDIA ACCESS CONTROL / HOST SYSTEM INTERFACE {METHODS AND APPARATUS FOR IMPLEMENTING A MEDIA ACCESS CONTROL / HOST SYSTEM INTERFACE}

The present invention relates to a data communication system, and more particularly, to a method and apparatus for implementing an interface between a local area network media access control (MAC) function and a host station attached to the network.

Communication between stations in a data transmission network occurs through the transmission of a series or 'frame' of information characters, with adjacent frames separated by an explicit or implicit start-stop pattern. By using a unique start pattern ('start delimiter') and a unique stop pattern ('end delimiter'; end delimiter), the receiving station can distinguish between the exact start and the exact end of each frame.

One popular type of network is the token ring. A basic token ring network consists of several repeater nodes, each of which is connected by a unidirectional transport link to form a closed loop ring. The information frames are sequentially transported one bit around the ring from one repeater to the next, with each repeater regenerating and retransmitting each bit.

In addition to serving as a retransmission element, each repeater on the ring also acts as a host station attachment point for inserting and retrieving information by the host station. When the information frame is cycled past the repeater on the ring, the destination address field of the frame is compared with the destination address field of the attached host. The host copies a frame when the destination address is recognized as its own.

Certain types of token ring networks are defined by the Fiber Distributed Data Interface (FDDI) protocol. The FDDI protocol is a United States Standard (ANS) data transmission format that applies to 100 Mbit / sec token ring networks using fiber optic transmission media. The FDDI protocol was designed as a high performance interconnect between multiple host computer systems and between computers and associated mass storage subsystems and other peripherals.

As William Stalling wrote in Howard W. Sims & Company's 1987 Handbook of Computer-Communication Standards, Volume 2, pp. 177-179, the FDDI token ring technology provides a ring when all stations are idle. It is based on the use of small token frames to circulate around. The station wishing to transmit must wait until it detects a passing token. The station then captures the token by giving up the token transfer as soon as the available token is recognized. Once the token is acquired, the station is given transmission medium control functionality up to a specified maximum time, during which it can transmit one or more frames on the ring.

Information is transmitted on an FDDI ring in a frame consisting of a series of 5-bit characters or 'symbols', each symbol representing four data bits or control codes. Information is typically transmitted in symbol pairs or 'bytes'.

1 shows the fields used in the FDDI frame and token format. A preamble field (PA) consisting of a series of idle line-state symbols precedes each transmission. The start delimiter field SD is composed of two control symbol start delimiter pairs that are uniquely recognizable regardless of the symbol boundary. As described above, the start delimiter byte sets the boundary of the information that follows. The frame control field FC defines the frame type and its characteristics, which distinguish synchronous and asynchronous transmissions, define the length of the address, and identify the frame type. The frame control field uniquely distinguishes tokens. The ending delimiter field (ED) of the token consists of two end delimiter control symbols and completes the token. The destination address (DA) and source address (SA) fields contain the destination and source address of the transmitted frame. The destination address field and the source address field are two bytes or six bytes long, as determined by the frame control field. The destination address may be an individual address or a group address. The frame check sequence field (FCS) is four bytes long and contains a cyclic redundancy check using the ANS standard polynomial. The information field is composed of only data symbols like all fields included in the frame check sequence field. The end delimiter of a frame has a frame status field (FS) consisting of three control indicator symbols indicating whether the addressed station has recognized its address, the frame has been copied, or which station has detected an error within the frame. It is one end delimiter symbol T that follows. The 'T' followed by three control indicators represents the minimum end delimiter required by the FDDI protocol for non-token frames. The protocol allows control in the end delimiter with additional odd number of control symbols followed by additional pairs of symbols or one last 'T' symbol. All means of execution that follow this rule must be able to process these extended end delimiters without truncation. The end delimiter symbol T and the two control symbols R and S are uniquely encoded and distinguishable from normal data or idle symbols.

2 shows an entity of a component for a necessary station conforming to the FDDI protocol. It includes a station management function (SMT) residing at each host station on the network that will control all the operations of the station to ensure proper operation as the absence of the required component rings. Physical Layer Medium Dependent (PMD) functionality provides an optical fiber link between adjacent stations on a ring. Physical layer protocol (PHY) functions provide encoding, decoding, clock, and synchronization functions. The media access control (MAC) function controls access to the transmission medium, and also transmits and receives frames from the function with the media access control function of another station. The PHY function receives and transmits simultaneously. The transmit logic of the PHY function accepts symbols from the media access control function, converts these symbols into 5-bit code groups, and transmits an encoded serial stream to the medium using the PMD capability. An encoded serial stream is received from the medium via the PMD, the symbol boundary is set based on the recognition of the start delimiter symbol pair, and the decode symbol is sent to the associated media access control function.

Additional information regarding the FDDI protocol can be found in the 'FDDI-an Overview', Digest of Papers, Computer Soc., Incorporated herein by reference to provide additional background information related to the present invention. Intl. Conf. Compcon '87, pp. Floyd Lee at 434-444. Provided by Floyd E. Ross.

3 illustrates a series of elements that coalesce to provide an integrated interface between FDDI token ring and MAC functionality.

The clock recovery device 10 extracts a 125 MHz clock from an incoming serial bit stream placed on an FDDI fiber optic transmission medium by an upstream station on the ring.

From the 12.5 MHz crystal reference, the clock distribution device 12 synthesizes the various clocks required by the physical layer controller (Player) 14 and the basic medium access controller (BMAC) 16. The player 14 converts the 12.5 Mbyte / sec stream retrieved from the BMAC 16 and decodes the incoming 4B / 5B data into an internal code.

The BMAC 16 controls the transmission, reception, relay, and stripping of FDDI tokens and frames.

As shown in FIG. 4, the BMAC 16 includes a ring engine 18, a control interface 20, a PHY interface 22, and a MAC interface 24.

The ring engine 18 is the heart of the BMAC 16 and performs the ANS X3T9.5 MAC protocol for transmitting, receiving, relaying and stripping frames on the FDDI ring.

The control interface 20 provides an interface to the control bus (FIG. 3), which initiates, monitors and diagnoses the operation of the BMAC 16 via the control bus.

The PHY interface 22 provides a byte stream to the player 14 via a PHY request bus, and receives a byte stream from the player 14 via a PHY indicator bus.

MAC interface 24 provides an interface to the external buffering and control logic of the station. The byte stream is provided to the buffering and control logic with the appropriate control signals via the MAC indicator bus. The byte stream is provided to the MAC interface with the appropriate handshake control signal via the MAC request bus.

Referring to FIG. 5, the ring engine 18 includes two main blocks, the receiver 26 and the transmitter 28, which share the MAC parameter RAM 32 with the timer / counter logic 30.

Receiver 26 verifies information from the FDDI ring, detects errors and failures, and generates appropriate control signals and flags used by transmitter 28 and provided to MAC interface 24. Receiver 26 also draws frames, tokens, and fragments from the received byte stream on the PHY indicator bus based on the identification of the start and end delimiters.

MAC parameter RAM 32 is a dual-port RAM that contains parameters such as the address of the associated station as implied. Receiver 26 uses the value stored in parameter RAM 32 to compare its address with the received address. The transmitter 28 also uses the parameter RAM 32 to generate the source address SA of every frame generated by the host station.

The transmitter 28 relays frames from other stations on the ring and inserts frames from the associated host station into the ring according to the FDDI time-token MAC protocol. Transmitter 28 uses the information provided by receiver 26 to decode whether to relay, strip, or generate a frame. Transmitter 28 continues to relay frames until transmission requests are forwarded to ring engine 18 by the host station.

The transfer request includes the requested class of service (ie, synchronous or asynchronous) and the type of token to be captured or emitted. As described above, the station acquires a transmission right by capturing a token. Once the token is captured, ring engine 18 waits until data is ready to be sent by the station. As the frame is transmitted, the frame passes along the ring, and each sequential station examines the frame one byte at a time. The frame is relayed at every station and eventually stripped by the station that originally sent the frame.

As also shown in FIG. 5, transmitter 28 includes a transmitter state machine (TSM) 34, an FCS generator 36, a ROM 38 and a multiplexing logic 40 for controlling the generation of data to the ring. Include.

Transmitter state machine 34 provides sequencing through the fields of frames to be sent to the ring.

FCS generator 36 calculates a 32-bit CRC and appends it to the information from the data stream.

ROM 38 is used to generate control symbol pairs to be sent with the frame as end delimiter and frame status fields.

Output multiplexer 40 is used to select the source of information to be loaded on the PHY request bus. As noted above, this information is generated independently by the associated station or relayed from the PHY indicator bus. Information may be generated from data stream, ROM 38, FCS generator 36 or parameter RAM 32.

The timer / counter block 30 includes all the timers and various event counters required to implement the ANS X3T9.5 MAC standard. It also includes token timing logic required for the performance of the FDDI time-token protocol.

Referring to Figure 6, token timing logic 42 is controlled by transmitter 28.

Token Rotation Timer (TRT) 44 is used to time the token rotation from arrival to arrival on the ring. The longer the rotation time, the greater the load on the ring. The timer in token timing logic section 42 shown in FIG. 6 is performed as an up-counter incrementing every 80 ns. The counter is reset by loading the binary complement of the threshold. This allows a simple carry to indicate timer termination.

The token hold timer (THT) 46 is used to limit the amount of ring bandwidth used by the station for asynchronous transmission after the token is captured by the station. Before each frame is sent, the value of THT is used to determine if the captured token is still available for transmission. If the THT has not reached the selected threshold, the token is available for asynchronous traffic.

Four asynchronous thresholds are supported by the BMAC 16, three are programmable and one is fixed to the compromise target token rotation time (TTRT). A request for sending a frame at one of the priority thresholds is satisfied if the token retention timer 46 has not reached the selected threshold. When the TRT reaches zero, a delay flag is set indicating that the token is late. While the delay flag is set, asynchronous frames cannot be transmitted and the token is available for synchronous transmission.

On early arrival of the token, i.e. when the token arrives but no delay flag is set, the TRT is loaded and counted up with the compromise target token rotation time TTRT. On delayed arrival of the token, i.e. when the token arrives and the delay flag is set, the delay flag is cleared and the TRT continues counting. When the TRT ends, the delay flag is not set, the delay flag is set, and the TRT is loaded into the TTRT. The accumulated delay is performed exactly as defined in the ANSI X3T9.5 MAC standard.

THT follows the value of the TRT until the token is captured. Once the token is captured, the TRT is reloaded into the TTRT, and the THT continues counting from the previous value (THT does not wrap around). THT is increased when enabled. An increase in THT is, for example, disabled during synchronous transmission. THT is used to determine if a token is available for asynchronous requests. For this purpose, the token is considered to be one-byte delayed before it is actually delayed (to promote interoperability, even for careless performance).

Asynchronous threshold comparisons are pipelined, so threshold crossings may not be detected immediately. However, the possible error is part of the threshold accuracy.

While the delay flag is set, the TRT is loaded into TMAX and the recovery process is invoked. The recovery request state also occurs one byte after the end of the TRT to promote interoperability even in somewhat inadvertent performance. When the TRT ends and the ring is not active, the TRT is loaded at TMAX. The TRT is also loaded into TMAX at reset.

Additional information regarding the BMAC 16 was provided in the following pending United States patent applications, each of which was jointly assigned to National Semiconductor Corporation with this application. The pending application

1. United States Patent Application No. 436,212 filed on Nov. 14, 1989, relating to a device and method for RAM-Based Events Counter;

2. US Patent Application No. 445,964, filed December 4, 1989, by Perloff on Apparatus and Method for Accessing a Cyclic Redundancy Error Check Code Generated in Parallel,

3. United States Patent Application No. 444,628, filed December 1, 1989 by Grow et al. On Asynchronous Priority Select Logic;

4. United States Patent Application No. 444,537, filed December 1, 1989, with respect to Ring Latency Timer.

The four patent applications are incorporated herein by reference to provide additional background information related to the present invention.

The present invention provides an interface between a medium access control (MAC) function of a local area network and a host system attached to a network medium via a MAC. The interface performs the transfer of information between the host memory system and the MAC for both frames received from the MAC receiver and frames provided by the host for transmission to the medium.

The interface according to the invention comprises two pipeline data paths. The indicator module sends the received frame from the MAC receiver section to the host memory via the integrated bus interface unit. The request module receives a frame from the host via the bus interface unit for transmission to the MAC transmitter section. The status generation / space management module shared by the indication and request modules monitors the transmission status required for frame delivery and manages storage space allocation in host system memory. The control bus interface provides host access to control the registers in the interface.

In a conventional interface where the receive frame state is passed from the MAC interface to the system interface in a path parallel to the receive data flow, only one end-of-frame (EOF) at a time is received FIFO (first). in fisrt out. This generates a dropped received frame.

According to one aspect of the invention, the MAC interface in EOF adds one final word as the frame state and places the state word behind the data into the receive FIFO. The system interface reads data and writes EOF state descriptors before processing the state. Data / state synchronization is automatic and no other communication between the MAC interface and the system interface is required. This allows any number of frames to be placed within the receive FIFO without complicated data / state synchronization. This allows full use of the FIFO when receiving many small frames, thus reducing the possibility of drop frames due to long-term bus delays. This allows for design flexibility in that the receiving FIFO can be at any depth.

In a conventional interface, all received frames are copied into a single space in the host memory system described by a single list of pool space descriptors.

According to one aspect of the invention, multiple channels are provided for received frames, the channels for incoming frames being selected depending on the program sort mode and whether the frame FC and the MAC or external address comparison hardware indicate a destination address match. do. Each channel has its own full space descriptor queue indicating where frame data is to be copied in system memory and a status queue for fully independent host processing.

In a conventional interface, the entire received frame is copied to one host memory buffer area. When operating the protocol, fast access is only required in the header portion of the frame, and the header must be processed earlier than the frame data. Header buffer space must be recycled sooner. Header processing cannot continue when data buffer space is exhausted and loses the ability to maintain handshake or flow control.

According to one aspect of the invention, the interface determines one or more points in the frame where separation of the preceding and subsequent bytes may occur. This mechanism may be a counter or incorporate a state machine that responds to data values or external stimulus in the information stream. At the split point, consecutive information bytes are copied to a separate memory area in system memory. The buffer management plan provides separate management for each memory area. The states can be written to one combination memory area, and thus the states can be grouped by the host for easier processing and management.

This frame segmentation mechanism allows the header to be placed in a separate memory region rather than data. It also allows separate buffer management for headers and data. The header can be processed even when the data buffer space is exhausted.

FDDI MAC frames are generated in the form of long bursts of the same frame. When all such frames are copied, they consume buffer space and processing overhead. Moreover, FDDI frames can occur in bursts. Typically, one interrupt is given per frame. This results in ineffective processing due to the per-interrupt overhead that occurs in each frame.

According to one aspect of the present invention, MAC frames are filtered, so that only frames containing new information are copied. The state (interrupt) is provided to the host only at breakpoints for new information. In addition, transmit and receive frames are transmitted in bursts, and status summaries are provided only at the burst boundary, further minimizing the number of host interrupts. Host programmable options are provided for burst boundary selection.

Conventional interfaces used a fixed burst size or transaction for all bus accesses. This wastes bus cycles whenever the burst size does not match the required data access.

In accordance with one aspect of the present invention, the system interface uses data pointers and counts to calculate the bus transactions most effective for performing fetching / storing in the fetching / storing of the required data.

Long bursts are more effective only when 'sufficient' bytes are required. By updating the pointers and counters for each bus transaction, the most effective transaction is calculated dynamically. Thus, the interface uses the minimum burst cycles possible to carry the required data and minimizes the bus bandwidth requirements of the system interface.

Conventional interfaces lose pre-empted transfer requests, cause the host to reorder the requests, and waste host CPU time.

According to one aspect of the invention, the system interface leaves the address of the first output data unit descriptor blank for each frame transmitted on the preemptive channel. If a preemption occurs, the interface exchanges channels in order to meet higher priority requests. When the higher priority request is completed, the interface returns back and returns the request processing to the descriptor address that was left empty.

Conventional uninterface commands have not been passed that are not associated with data. Therefore, the command had to be delayed until the data was ready.

According to one aspect of the invention, the interface scans the byte count field on each newly fetched data unit descriptor. If the byte count field is zero, the descriptor is not validated at all, no data fetch is requested, and descriptor processing continues. Without this check, the interface must wait until the described data is fetched before processing continues. However, no fetch can occur with a zero byte count. Thus, a restriction will be imposed that all data units must have data. The interface according to the present invention allows zero-length descriptors in the descriptor structure and does not waste time for the host software to remove the descriptors and to tie the non-zero length descriptors together.

The interface recognizes that the first descriptor of the request object describing the zero frame is a token capture request. Subsequent descriptors of the same object describe the frame data. Also, if the last descriptor of an object contains zero frames, this is a token release request. These descriptors can be ordered regardless of frame data availability. This mechanism allows the host to request acquisition of any service class token without necessarily preparing the data, and allows token release after all data has been sent through the descriptor stream interface.

In a conventional interface, a single descriptor flag that marks the end of an object does not provide consistency checking and redundancy and therefore does not provide fault detection. All sequences appear to be legitimate. Thus, the error propagates to the ring.

According to one aspect of the invention, the descriptor includes a 'first' flag and a 'final' flag to distinguish the boundary of the object. Descriptors without either flag are 'medium', and descriptors with both flags are 'unique'. 'First' or 'unique' must follow 'final' or 'unique' and 'first' or 'middle' must precede 'final'. Otherwise, a consistency failure is detected. This mechanism allows for descriptor consistency check, so that frames described by bad descriptors are not sent to the ring.

In a conventional interface, the bridging software must generate a transport data descriptor before processing the received data descriptor and processing the request for the transport interface.

According to one aspect of the invention, the receiving interface points to input data unit descriptors (IDUDs) indicating the FC bytes immediately preceding the frame DA for IDUD.Fs (also directly pointing to the data unit start for IDUD.noFs). Generated in the same two word format (ODUSs) allowed by the transport interface with byte counts, data pointers and F / L flags. This transmit and receive data descriptor format compatibility allows the host to retransmit frames by simply pointing to the transmitter for descriptor purposes without moving / modifying data or descriptors. This reduces host processing overhead when retransmitting received information.

The FDDI standard defines the significance of bits in each byte of the source and destination addresses in the reverse order of those in the Ethernet protocol.

According to one aspect of the invention, the MAC interface bytewide bit inversion multiplexer is located in both the transmit and receive data paths. The control logic determines when the address requires translation and when the address byte passes through the multiplexer, and drives the control signal to select between the normal path and the inverted path. This relieves the bridging software from the time consuming conversion of FDDI addresses to and from Ethernet addresses.

The features and advantages of the invention will be better understood with reference to the accompanying drawings which illustrate embodiments in which the principles of the invention have been employed and the detailed description set forth below.

1 is an explanatory diagram of an FDDI frame and token format

2 is a block diagram showing components required for a station to comply with the FDDI protocol.

3 is a block diagram illustrating elements configured to provide an integrated interface between a host station and an FDDI token ring.

4 is a block diagram illustrating components of one embodiment of a FDDI Basic Media Access Control (MAC) function.

5 is a block diagram illustrating one embodiment of a BMAC ring engine.

6 is a block diagram illustrating one embodiment of a BMAC asynchronous priority selection logic.

7 is a block diagram illustrating one embodiment of a BMAC system interface (BSI) in accordance with the present invention.

8 is a block diagram illustrating a BSI connected directly to a host system bus.

9 is a block diagram illustrating a BSI using shared memory.

10 is a schematic diagram illustrating output requests of two frames;

11A-11E are schematic diagrams showing the five descriptor forms recognized and / or generated by the BSI.

12 is a block diagram showing the structure of an indicator module;

13A is a block diagram illustrating the general structure of a request module.

13B-13F are block diagrams illustrating the structure of various components of the request module.

14 is a status generation / space management module

15aaa to 15dddd are block diagrams showing the structure of a bus interface unit module.

16 is a schematic diagram illustrating a request data structure.

17 is a schematic diagram illustrating an indicator data structure;

18 is a schematic diagram showing a space data structure;

19 is a schematic diagram illustrating a minimum memory layout;

20 is a logic schematic diagram illustrating a two-level attention structure;

21 provides a table providing a list of control and configuration register sets.

22 provides a table providing a list of PTR RAM register sets.

23 provides a table providing a list of limit RAM register sets.

24 is a state diagram of the request machine.

25 is a stable diagram for a BTU state machine.

26 is a timing diagram showing a waveform for DBus single read.

Fig. 27 is a timing diagram showing a waveform for ABus burst reading.

28 is a timing diagram showing a waveform for ABus single recording

29 is a timing diagram showing a waveform for ABus burst writing;

30A-30CCC illustrate a pinout arrangement for an interface system in accordance with the present invention.

The present invention provides an interface between the basic medium access control (BMAC) function described above and a host system attached to the FDDI token ring, which interface is referred to herein as a BMAC system interface or a BSI.

The following conventions are used to describe the BSI.

Byte and bit ordering rules

1. BSI can be operated as a 'little-endian' or 'big-endian' system. All descriptors handled by the BSI are two 32-bit words at consecutive word-aligned addresses. This means that the descriptors will look the same way regardless of the 'endian-ness' of the system. But the byte stream looks different. The description below defines how the BSI addresses the memory.

The word is 32 bits. The 31st bit is the most significant bit and the 0th bit is the least significant bit. One word consists of four bytes. The bytes are addressed in such a way that they increase from byte address 0 to byte address 3 in one word. The small-endian and the large-endian differ from each other as shown in Table 1 below in which word bits correspond to which byte addresses.

Any information that is not a network data byte (that is, a descriptor) is considered a word, not a byte. Network data is a stream of bytes ordered for relative time shifts on the ring. Table 1 shows time ordering in small-endian and large-endian systems. The bytes are sent on the FDDI ring or received from the FDDI ring in alphabetical order starting with byte A.

Table 1

2. All control bus (CBus) registers have 8 bits accessed at a time. The register uses the following bit-order rule.

Bit 7-> MS byte, low byte address--> Bit 0

Bit 7-> LS byte, high byte address-> Bit 0

Introduce

BSI Overview

The FDDI BMAC System Interface (BSI) 10 according to the present invention shown in block diagram form in FIG. 7 realizes an interface between the BMAC and the host system. It is designed to effectively provide a high performance low cost interface for various hosts, but especially for high performance virtual memory systems. The BSI 10 may operate on a system bus connected to main memory or external shared memory. As described in more detail below, the BSI 10 has multiple DMA channels with transmit and receive state machines to move data and descriptors.

The BSI 10 may operate in any combination of cached / non-cached, paged or non-paged memory environments. When operating in a paged environment, the BSI 10 uses 4K byte page size. To provide this capability, all data structures are contained within pages, and bus transactions never cross a page. This additional capability is not required in non-paged environments. The BSI 10 performs all bus transactions in ordered blocks to facilitate the interface to the cached environment.

The BSI 10 has two bus interfaces, a datapath bus and a control bus.

The main datapath bus is a 32-bit multiplexed address / data memory interface called ABus. The BSI structure supports up to 30-bit real addresses, but provides a 28-bit implementation address in practice.

ABus supports burst mode transfer to allow the use of nibble-mode / static column / page mode DRAMs or static RAMs. The ABus can be operated with a virtual or real address generated by the BSI 10. When operated with a virtual address, the BSI 10 emits a virtual address, which is translated by an external MMU (or simpler mapping logic) and driven on the address bus. Even in both addressing modes, the BSI 10 can be operated in a multi-master environment.

The control bus is an 8-bit non-multiplexed bus called CBus. This uses a simple asynchronous strobe and acknowledgment protocol.

To provide maximum performance and system flexibility, the BSI 10 uses two independent clocks, one for the MAC interface (i.e. ring) and one for the system / memory bus (i.e. ABus). will be. The BSI 10 implements and provides a fully synchronized interface between these two timing domains.

8 shows a BSI 10 connected directly to a host system bus for best performance. 9 shows a BSI 10 using shared memory for local buffering.

The BSI 10 provides an interface to a data structure and a MAC data service that uses external memory for most communication. The BMAC decodes the symbol stream and event state provided by the player and signal frame boundaries. The BSI 10 maps the BMAC data stream into external memory.

The BSI 10 accepts a request from an associated host to send multiple frames (SDUs, defined below) from system memory to the network. The BSI 10 unpacks 32-bit wide memory data at the time of transmission and sends it to the BMAC one byte at a time. The BSI 10 receives a byte stream from the BMAC upon receipt, packs it into 32-bit words and writes it to system memory. The host software and the BSI 10 communicate via an external memory base queue that can be synchronized by interrupts.

Justice

The following terms will be used in the detailed description of the invention.

Signal state

The signal has two logical states and three physical states. The three physical states are high, low and tri-states. High state is a higher voltage level. Lower states are more negative voltage levels. Tri-states exist when the output is not actively driven to high or low states.

There are two logical states of true and false. To avoid confusion, the terms 'assertion' and 'negation' are used to indicate the logical state of a signal. The hypothesis is used to represent the signal in true state. Negation is used to indicate a false signal.

Since there is both positive and negative logic, the signal can be either true high or true low. Assumptions and negation are independent of whether the signal is active-high or active-low. The active-low signal is indicated by an underscore at the end of the signal name, eg, underscore in low_signal_.

'Reset' is used to refer to the initialization of the BSI 10 (or its logic) as a result of asserting an external RST pin or asserting a software master reset bit.

Storage allocation

The BSI 10 interfaces to byte-addressable memory, but always conveys information as words. The BSI 10 uses a word width of the number of bits in which 32 data bits and 4 byte-parity bits are added. Parity may be ignored.

To maximize bus efficiency, BSI always carries a burst of information. Delivery is always aligned with burst-size boundaries. The BSI 10 uses a burst-size of one word for control information transfer, and dynamically serializes the interface to a 1, 4 or 8-word burst for data transfer.

The invitation 'unit' of contiguous storage allocation in external memory is the 'page'. The BSI 10 uses a page size of 1K or 4K bytes (256 or 1K words, host-selectable) for the control information space, and a page size of 4K bytes (1K words, fixed size) for the data space. do. Data objects (ie, SDUs / frames) may include multiple disjoints or adjacent pages.

The address memory uses a 'pointer' containing a 1-bit page number and a 12-bit 'offset'. This provides 28 bits of virtual real addressing capability. When passing data unity, the pointer is incremented until it meets the page boundary, and when it encounters the boundary, a new page is used. When sending the control unit, the pointer is incremented up to page bound and then wraps back to that page start point. This special structure is called a queue.

Information system

The BSI 10 and the host system interact by exchanging two kinds of 'objects'.

1. The control object is interpreted by the BSI 10 and can change its operation.

2. The data object is not interpreted by the BSI 10 and passed to or from the BMAC.

Control and data objects remain separated in external memory. Each object always has a single owner and enables reliable synchronization across the ABus interface.

An object may consist of one or more 'parts' in external memory. Each part of an object must be contiguous and fully contained within a memory page.

'Single-part' objects

1. Consists of only one part,

'Multi-part' objects

1. With one first part

2. the middle part of 0 or more

3. It consists of one final part.

The object parts are identified by a 2-bit tag field that uses the first bit (one in bit [31]) and the last bit (one in bit [30]). The results are shown in TABLE II below.

TABLE 2

First final Descriptor form and use 1001 0011 Only part that is the first and last part in the first part object in the first part object in the first part object in the object

Each part of the object is described by a 'descriptor'. According to one aspect of the invention, the descriptor accepts a first flag and a final flag to distinguish between objects. Descriptors without any flag set are 'medium', and descriptors with both flags are 'only'. 'First' or 'only' must appear after 'final' or 'only' and 'first' or 'middle' must precede 'final'. Otherwise, a consistency failure is detected. This mechanism allows descriptor coherency checking, so that frames described by bad descriptors are not sent to the ring.

'Stream' is a flow in one direction of logically related information. The object is passed between the BSI 10 and the host in the form of a stream. There is a separate kind of stream for each kind of object.

Descriptors that point to a portion of a data object or control stream include a location field and a 'size' field. The location is in memory, the portion of which is the address of the first byte. The size is the length of the portion of the memory (in bytes for the data unit portion and in words for the control stream portion).

A message is a control object that contains a series of commands or status parameters. The message does not have a location and size fields, because the message does not point to information but contains information.

A frame or 'service data unit (SDU)' is a unit of data transfer between a service user and a service provider. The BSI 10 carries MAC SDUs, i.e., MAC frames, between the BMAC and the external memory. The frames may be contiguous in external memory, or the frames may include a number of distinct portions. Each frame portion is called a 'data unit'. There is a 'data unit descriptor (DUD)' for each data unit. There are first, middle, last and only DUDs depending on which part of the SDU is being described. There are data units and descriptors for input and output, each type being named an input data unit (IDU), an output data unit (ODU), an input data unit descriptor (IDUD), and an output data unit descriptor (ODUD).

As an example, Figure 10 shows an example of an output (output to ring) request of two frames, each frame consisting of two parts. This will have the following structure:

REQ descriptor that points to two ODU descriptor objects (one for each frame)

2. Here each includes an ODU descriptor object ODUD first and ODUD final.

3. Each ODUD here points to an ODU part.

4. Here each of the four ODUs (parts) contains part of the frame.

There are five descriptor types that are recognized and generated by the BSI 10. These are shown in FIG. 11 and listed below.

1. DUD: The data unit descriptor describes the position and size of the data unit. ODUDs are closed on the output channel. Thus, the frame portion can be assembled for transmission. IDUDs are generated on the input channel to describe where each BSI 10 has written each frame portion.

2. REQ: The request descriptor passes the operating parameters and commands to the BSI.

3. CNF: Acknowledgment status message (descriptor) describes the result of the request operation.

4. PSP: Full Space Descriptor describes the location and size of the area of free memory space.

According to one aspect of the invention, the receiving interface has an F / L flag of the same two word format that the transport interface accepts (ODUDs), a byte count and a data pointer, and a data unit for IDUD.Fs (also IDUD.no Fs). Generate input data unit descriptors (IDUDs) that point to the FC byte preceding the frame DA for direct start). This send and receive data descriptor format capability allows the host to retransmit frames by pointing the transmitter in the descriptor list without moving / modifying data or descriptors. This reduces host processing overhead when retransmitting received information.

SAPs and Channels

The BSI 10 provides an interface to a MAC data service for one or more BMAC users. In other words,

1. The SMT entity is a MAC user (at all stations).

2. The LLC entity is a MAC user (at the end station)

3. The relay entity is a MAC user (at the bridge).

In accordance with an aspect of the present invention, each MAC user accesses a MAC data service via one or more 'service access points (SAPs)'. MAC users can use more than one SAPs, but SAPs are not shared by more than one MAC user. The BSI 10 provides five SAPs, two requests (output to the ring) RSAPs and three indicators (input to the host) ISAPs. These SAPs can be assigned as follows:

1. RSAP_0 and RSAP_1 on the output for synchronous and asynchronous transmission respectively

2. ISAP_0, ISAP__1, ISAP_2 on input for MAC-SMT synchronous and asynchronous transmission respectively.

The BSI 10 provides four different options for SAP assignment to provide appropriate support for various applications. The four options are basically synchronous / asynchronous, high / low priority asynchronous, internal / external address (for bridging applications) and header / reminder (for fast protocol processing).

The BSI 10 provides five 'channels'. The channel controls the transfer of related objects between the BSI 10 and the external memory. Channels are used to realize SAPs. Each SAP has one channel. Using multiple channels, each SAP appears to be independent and concurrent (with some limitations).

Each channel has direct memory access (DMA) capability via a subchannel that controls the transmission of a single form of related object within one channel.

The request channel has four subchannels: an output data stream, an ODU descriptor stream, a CNF message stream, and a REQ descriptor stream.

The indicator channel has three subchannels, that is, an input data stream, an IDU descriptor stream, and a PSP descriptor stream.

Attention / Notification

The BSI 10 may operate in a fold or interrupt-driven environment. Interrupt schemes are designed to minimize the number of interrupts given to the host. The BSI 10 generates an interrupt called 'attention' by setting the appropriate event attention bit in the event register. The host enables this attention to generate an interrupt (i.e. disable the mask) by setting the corresponding 'Notify' bit.

At set bits and resets, some attention bit is a signal. The BSI 10 sets a bit to send an attention signal to the host. The host resets the bit to signal completion / acknowledgement to the BSI 10. This may cause the BSI 10 to take some processing action (eg, mailbox reading).

details

Referring back to FIG. 7, the BSI 10 generally includes the following five modules: an indicator (receive) module 12, a request (transmit) module 14, a state generation / space management module. 16, the bus interface unit module 18 and the control bus (CBus) interface module 20. The indicator and request modules 12, 14 are independent and pipelined machines. Each pipeline includes a BMAC interface, data FIFOs 12A, 14A, burst FIFOs 12B, 14B, and state machines 12C, 14C.

Each data FIFO 12A, 14A is 64 bytes deep and is arranged in 16 words, each word being 42 bits wide. Within the indicator data FIFO 12A, one word is 32 data bits, four parity bits (one per byte), the receive channel (ISAP) where the word is converted into system memory, and the 'shape' of the word (ie A 4-bit tag that identifies uncomitted, committed, and state, and two unused bits. Within the request data FIFO 14A, one word is 32 data bits, 4 parity bits. And 6-bit tags (described below). Data FIFOs 12A and 14A are designed to accommodate bus waits.

According to one aspect of the invention, in EOF, the MAC interface tags one final word as the frame state and places the state word after the data in the indicator data FIFO 12A. The system interface reads the data and writes the EOF status descriptor before processing the status. The EOF status descriptor identifies the EOF status, includes an EOF indicator (ie error, copy) and sets a breakpoint (described below). Data / state synchronization is automatic and no other communication between the MAC interface and the system interface is required. This allows any number of frames to fit within the indicator data FIFO 12A without complex data / state synchronization. This also reduces the possibility of drop frames due to long bus latency by allowing secure FIFO use when receiving many small frames. This also allows design flexibility in that the indicator data FIFO 12A can be at any depth.

The indicator data FIFO 12A can reset its write pointer to remove unwanted data.

Each burst FIFO 12B, 14B must maintain a complete bus burst and is arranged in 16 words of 32 bits. Because bursts are a maximum of eight words, burst FIFOs 12B and 14B are used in a 'ping-pong' manner to provide two banks of 0.1 each holding one burst. As described, BIU module 18 reads or writes the complete burst into one bank. The indicator state machine 12C or the request state machine 14C reads the appropriate number of bytes from the bank.

That is, according to one aspect of the present invention, as also described in more detail below, data pointers and counts are used to calculate the most efficient bus transaction to perform upon fetching and storing the necessary data. Longer bursts are more effective, but only when 'sufficient' bytes are required. By updating the pointer and counter with each bus transaction, the most efficient transaction is calculated dynamically. Thus, the smallest burst cycle possible is used to transmit the necessary data, minimizing the bus bandwidth requirements of the system interface.

For example, only five bytes of burst may be valid at the time of last writing a frame to memory. In this case, indicator machine 12C writes only five significant bytes into the bank, while BIU module 18 writes the complete bank. This is acceptable because all frames received as described above are aligned on a burst-size boundary, and the written DUD will contain a count of the actual number of valid bytes in the frame.

Burst FIFOs 12B and 14B are also used as an asynchronous boundary between other low-level logic operations on the ring clock and BIU logic operations according to the system bus clock.

State machines 12C and 14C are described in more detail below.

The status generation / space management module 16 is shared between the request and the indicator pipeline.

BIU 18 handles all ABus traffic and CBus interface 20 accesses event / attention control.

BIU interface 18 is a 32-bit memory bus port used to pass all datapath information to and from BSI 10. This includes data, descriptors, and states. The bus uses 32-bit multiplexed addresses and data and provides burst transfer capability at full bandwidth.

The host uses the CBus 20 to access BSI internal registers and manage the attention / notification logic.

A more detailed description of the indicator module 12 is provided in FIG.

Further details of request module 14 are provided in FIGS. 13A-13F.

A more detailed description of the status generation / space management module 16 is provided in FIG.

A more detailed description of the bus interface unit module 18 is provided in FIG.

The remainder of the detailed description of the invention will appropriately refer to these modules.

Data structure

The BSI 10 uses a simple data structure that can be easily mapped to any higher level interface via a software driver. As differs from one feature of the invention and described in further detail below, the data unit structure is basically symmetrical in input and output.

The BSI 10 divides the memory into fixed size pages. This provides ideal support for the virtual memory environment and reduces the amount of logic used for DMA management (pointer).

Data type

The BSI 10 handles data units, data unit descriptors (DUDs), request descriptors (REQs), acknowledgment messages (CNFs), and full space descriptors (PSPs). As mentioned above, the descriptor may be a multi-part object, with each part identified by the first-last tag.

IDU.ODU (Input / Output Data Unit)

An IDU / ODU is a group of contiguous bytes that form all or part of a service data unit (SDU). Each IDU / ODU may be all or part of a page, but always fits within the page. There are data units for input and output, i.e. IDUs and ODUs, respectively. (Request) ODUs are stored in a memory area defined by the host. The BSI writes IDUs within (indicated) memory regions separated by full space descriptors (PSPs). Each ISAP fetches PSPs as required from its own PSPs queue.

Data Unit Descriptors (DUDs)

DUDs (IDU / ODU Descriptors) are two-word entities that describe IDUs or ODUs, which are location and size fields. The location field contains the number of pages and the offset within the page. The size field limits the number of bytes in the data unit. The page may include one or more data units (depending on the frame size) on the SAP. DUDs are written to status queues, 1 or 4K byte queues, located anywhere in memory (aligned within a 1 or 4K byte boundary). There are input and output DUDs, i.e. IDUDs and ODUDs, the formats of which are shown in Figs. 11B and 11C, respectively.

The IDUD also contains states for the frames they describe. For multi-part IDUD, the IDUD final descriptor contains a valid final state for the frame. The IDUD is written to the indication status queue.

REQ (REQ descriptor)

The REQ descriptor is a two-word entity that points to a part of the ODUD object stream. These include the location and size fields. The location field indicates the start address (aligned word) of the portion of the ODUD stream. The count field defines the number of frames represented by the ODUD stream portion (ie, the ODUD descriptor with the last bit set). REQ is fetched from the 1 or 4K byte queue. The request descriptor format is shown in d of FIG.

CNF (Confirm Status Message)

CNF is a two-word acknowledgment status descriptor stored in the request status queue. In indication, IDUD is a combination of descriptor and status message. The confirmation descriptor format is shown in FIG.

Full Space Descriptor (PSP)

PSP is a two word descriptor for the free-space area available for writing indicator data. This includes location and implicit size. Since there is a fixed 4K byte data page size, the PSP has an implicit count of up to 4K bytes. The location field contains the number of pages and the offset. Typically the offset will be 0 (lower (burst) bit must be 0), and space management only handles the entire sorted 4K memory page. The PSP is fetched from a 1 or 4K byte queue. The PSP descriptor format is shown in FIG. 11A.

Request

Referring to Figure 12, request SAPs (RSAPs) use a three-level structure to define the output SDU.

Each SDU is described by an ODU Descriptor (ODUD) object. Each ODUD identifies an ODU that fits entirely within a memory page. Multiple ODUD objects (multiple SDUs) can be grouped adjacently to be described by a single REQ descriptor part. Multiple REQ descriptors (parts) may be grouped as one request descriptor object by the host software. Each REQ portion is fetched by the BSI 10 from the REQ queue using the Req? _Req_ptr subchannel of the RSAP channel. Each RSAP processes one request descriptor object per RSAP, per service opportunity, that is, up to a REQ descriptor with a final set of tag bits.

Request status (confirmation) is generated as a single confirm object per request object. Each acknowledgment object contains one or more CNF messages. Each RSAP has a 1 or 4K byte acknowledge status queue in which the CNF is written.

Indicator structure

Referring to Figure 17, the indicator SAP (ISAP) generates a two-level structure (compatible with the RSAP structure).

Each SDU is stored in the current IDU page. If the SDU fits completely within the page, IDUD. Only descriptors are written to identify SDUs. If more than one page is written, the multi-part IDU descriptor object is written. The intermediate state is written into each IDUD, and when a state event occurs, the defined state is written into the final IDUD and an attention is generated. Status events are host-defined.

The three ISAPs each have their own status and data PSP queues. The queues can all be 1K or 4K bytes. Each queue can be located anywhere in memory (aligned to a 1K or 4K byte boundary). Each ISAP writes data into its own memory page obtained from its own PSP queue.

Full-space structure

18 shows the structure of an ISAP PSP queue. The queue describes a pool of available space for writing incoming data on the ISAP. The queue is 1K or 4K bytes. Since it is 8 bytes per PSP, the queue maintains 128 or 512 PSPs (up to 0.5 to 2 M bytes of free space per ISAP).

Control memory allocation

The BSI 10 allows each queue to be anywhere in memory as long as it is aligned with the queue size boundary. As mentioned above, the host has two choices for queue size, namely 1K or 4K. The mode register bit sets all cue sizes to the selected value. There are a total of 10 queues. In order to use the minimum amount of control memory, a 1K queue size is selected and the 1K byte state, REQ and PSP queues are grouped into pages (10K consumption). Other spaces are needed for ODUD.

Figure 19 shows how the control memory requirements for the minimum system are matched in two 4K pages. In this case, only two ISAPs are used, namely ISAP_0 and ISAP_1. The BSI 10 is placed in an internal / external sorting mode, and external addressing is not used. This means that ISAP_0 copies MAC-SMT frames and ISAP1 copies everything else.

BMAC support

Errors and exceptions

An 'exception' is a recoverable anomaly that does not cause a condition, modify its processing, or require special host intervention. On the other hand, an 'error' is an unrecoverable anomaly, in which case the BSI 10 is not guaranteed to generate a state, and therefore the error requires special host processing. An example error is an ABus transaction error when writing a state.

Request

As mentioned above, the BSI 10 provides two requests SAP, RSAP_0 and RSAP_1 and high priority and low priority. Typically, high priority is used for synchronous traffic and low priority is used for asynchronous traffic, but nothing in the BSI 10 constrains this relationship. However, RSAP_0 is not serviced after RSAP_1 within one service opportunity.

Each RSAP generally has the same function. Only one (multi-part) request object is served per RSAP for each service opportunity. However, the request object includes a number of service opportunities. Of course, this function must meet standard usage. For example, if THT is disabled (synchronous traffic), the request should contain only one service opportunity, otherwise the request will be errored due to exceeding synchronous bandwidth allocation.

Prestage, staging and preemption

Request state machine 14C (FIG. 7) handles prestaging, staging and preemption. It is 'staging' when RSAP begins fetching data for the next frame into the request burst FIFO 14B once the current frame has been performing transmission and its end byte is in the FIFO.

Prestaging is when the next frame is staged before the token arrives. Prestage does not apply to requests that have an immediate request / release level (i.e. no tokens exist).

Preemption is when a higher priority RSAP preempts a (non-committed) frame of a lower priority RSAP that is already in the FIFO (BSI allows RSAP_0 to selectively suspend RSAP). The effect of this is to cause the BSI-MAC to release tokens and then reorder the priorities among the service opportunities.

In accordance with one aspect of the present invention, the BSI 10 leaves the address of the first ODUD blank for each frame transmitted on the preemption channel. If an outage occurs, the BSI 10 switches the request channel to service higher priority requests. When the higher priority request is completed, the BSI 10 returns the request processing to the descriptor address that was switched back and stored.

The BSI 10 always stages an SDU. Prestage is a user-programmable option for RSAP_1 and is always enabled for RSAP_0 only.

The BSI 10 prioritizes active requests within the start state (usually between service opportunities). Active RSAP_0 requests will always be serviced first, typically RSAP_0 will be serviced first during service opportunities and then RSAP_1. Once preemption is enabled and the request is (free) staged, RSAP_1 can be preempted. This will occur when RSAP_0 becomes active. Incorporated RSSP_1 SDUs already in the request FIFO are removed and refetched after servicing RSAP_0. The frame is transmitted once, the FIFO threshold is reached, or the end of the frame is in the FIFO and the BMAC is ready to transmit.

Confirm

There are three alternatives to acknowledgment: nonconfirmation, transmitter acknowledgment or complete acknowledgment.

When confirmation is needed, the BSI 10 typically only writes the confirmation status at the end of the request object. If the request includes multiple service opportunities, a multi-part acknowledgment state object may be written and one partial service for every service opportunity. For transmitter verification, the request state machine 14C confirms that the SDU was sent correctly. For complete verification, the request machine 14 C verifies that the SDUs were sent correctly, and that the 'correctly' confirmed SDU number is equal to the transmitted SDU number. An 'exactly' frame is generally a frame with a matching FC, local source address (when SA transparency is not selected), matching expected E, A and C indicators, valid data length and valid FCS.

Indicator

The BSI 10 provides three indicator SAPs, namely ISAP_0, ISAP_1 and ISAP_2, all of which have the same priority. According to one feature of the invention, incoming data is sorted on three ISAPs according to several indicator configuration bits. Further details regarding the sorting logic are given in the service interface described below. There are two bits that determine the main sorting mode, which is Sort_Mode (1: 0). Table 3 below shows the effect of these two bits.

Table 3

SM1.SM0 ISAP＿2 ISAP＿1 ISAP＿0 00011011 Asynchronous external information L-asynchronous Synchronous Internal Header Hip-Asynchronous MAC-SMTMAC-SMTMAC-SMTMAC-SMT

ISAP_0 always receives SMT and MAC SDU. The other two SAPs receive SDUs according to the BSI 10 sort mode.

In mode 0, ISAP_1 receives synchronous frames and ISAP_2 receives asynchronous frames. This mode is for use in end stations that support synchronous traffic.

In mode 1, ISAP_1 receives a frame that matches an internal address (in MAC), and ISAP_2 receives a frame that matches an external address (when an EA input is asserted). This mode is for bridge or ring monitors with external address matching circuits and using ECLP / EA / EM pins.

According to one aspect of the invention, one or more points at which separation of preceding and subsequent bytes within a frame may occur is determined in mode 2. This mechanism may be a counter, or it may incorporate a state machine that responds to data values in an external stream or information stream. At the break point, the consecutive information bytes are copied to a separate memory area in system memory. The buffer management scheme provides separate management for each memory area. Status can be written to a combination memory area that is grouped by the host for easier processing and management.

Thus, in mode 2, ISAP_1 and ISAP_2 receive all non-MAC / SMT frames to be copied, but separate the header and information (rest) in between. ISAP_1 copies the initial byte until the host-defined 'header length' is reached. The rest of the frame bytes are copied onto ISAP_2. Only one IDUD stream is generated (on ISAP_1), but both PSP queues are used to determine where the IDU will be written. This mode is for high performance protocol processing applications.

Mode 3 sorts the high priority asynchronous frames on ISAP_1 and the low priority asynchronous frames on ISAP_2. The most significant bit of the 3-bit priority field determines the high / low priority.

ISAP writes indicator data separately to separate memory pages and has its own PSP queue. This allows for a variety of full space management schemes, including three orderings. Each ISAP writes a state (ISUD) in its own state queue.

External memory interface (ABus)

The BSI 10 uses a multiplexed address and a data bus ABus. This performs a 32 bit wide data transfer and provides a 28 bit address.

The BSI 10 operates in one of two ABus modes, which is a virtual or real addressing. In virtual addressing, an external memory management unit (MMU) provides address translation for the BSI 10. The BSI outputs channel information on the top four address bits, and a more sophisticated external addressing scheme can be supported. By way of example, control information may be stored in one memory and data information may be stored in another memory (ie, an external FIFO). The BSI 10 also outputs three demultiplexed address bits during one burst. This indicates which words in the bus are accessed.

External memory accessed via ABus can be static or dynamic. To effectively support DRAM, the BSI 10 uses burst mode transfer and transmits 4 or 8 words (corresponding to 16 or 32 byte bursts) in one burst. Actual DRAM address multiplexing, refreshing, and the like must be handled by an external DRAM controller, such as the DP9420 DRAM controller available from National Semiconductor Corporation.

The BSI 10 operates in a multi-master environment because it uses a simple bus-request / bus grant signal pair for arbitration for arbitration.

The bus supports several types of transactions. Simple read and write involves single address and data transfer. Burst reads and writes include a single address transfer followed by multiple data transfers. The BSI 10 provides address bits that increase during the burst transaction. The burst is always 16 or 32 bytes aligned to the modulo 16/32 byte address boundary. In addition, the BSI 10 never emits a burst to wrap in order to coexist in a system that performs an implicit wrap-around for an address in the burst.

The default addressable amount is bytes, for example, the request data can be arbitrarily aligned in memory. However, all the information is accessed in 32 bit words, and the BSI 10 ignores unused bytes at the time of reading. The BSI 10 always writes every byte of a word, thus aligning all indicator data. Burst read / write data must be burst-sized in ordered modules. In data read / write, single word, 16 byte and 32 byte burst transactions are used when required for maximum efficiency.

Parity

The BSI 10 provides two options for parity, one for systems that use parity and the other for systems that do not use parity. When parity is used, it operates in flow-through mode on the main datapath. All parity interfaces use odd parity and have their own attention.

The BSI 10 always generates parity on each of the three output buses, which are the ABus interface, the CBus interface and the BMAC interface.

If (flow-through) parity is enabled, the BSI 10 does not check or generate parity on the data at the ABus interface. Instead, it flows between the ABus and BMAC interfaces. Since parity is generated on the address when the address is stored in the BSI 10, the BSI 10 does not generate parity on the released address. CBus and BMAC databus parity are checked and generated.

If parity checking is not possible, the BSI 10 fails to check parity on information from the ABus, CBus or MAC interface.

Queue management

The BSI uses 10 queues, six on indicators (two per ISAP) and four on requests (two per RSA). Each ISAP has a status and a PSP queue. Each RSAP has a CNF and REQ queue.

As mentioned above, the host programs all queues to be 1K or 4K bytes. The BSI 10 manages all queues by keeping a pointer to the next free entry in the queue compared to a register holding the limit of the queue. The queue pointer is incremented after each read / write. When the pointer reaches the upper queue bound (end of page), the pointer wraps back to the lower bound (start of page). Holds the limit of the queue as the offset value in the unit of the queue limit register 1 descriptor (8 bytes).

Although data space flow control is more accurate, the host provides flow control over ISAP by limiting the data or state space.

Status queue

The BSI 10 stores a two-word descriptor (message) in a status queue. The limit register defines the position of the penultimate (just before the end) at which state is to be written. Each word is written to an address in the queue pointer register, which is later incremented. This causes the 'No_status_space' attention when the BSI 10 writes to the queue entry before the host-defined limit. The BSI 10 writes up to two descriptors due to pipelining. More complete details are given in the service interface mentioned below. When there is no state space, RSAP does not process any further requests, and ISAP does not copy any more frames.

Data space queue

The BSI 10 loads a two-word PSP descriptor from the PSP queue. The limit register defines the last valid PSP written by the host. Each ISAP has a DMA subchannel running its own PSP queue. The PSP is fetched from the location referenced by the PSP pointer, which is later incremented. If the PSP is (pre) fetched from the limit of the queue (as defined in the limit register), a 'Low_Data_Space' attention is generated for that ISAP. This will occur on the second PSP at the end in the queue if the queue does not have only one PSP when an attention occurs when PSP is prefetched. The host will add more PSPs to the tail of the queue and update the limit registers. As long as the host maintains enough PSP entries, adequate space is available for ISAP to continue copying.

Request operation

The BSI 10 loads a REQ descriptor from the REQ queue. The limit register (described below) defines the last valid REQ written by the host. For transmission, all SDUs with a common service type, frame control, and expected-state are gathered together in one request object. The host programs the Req? _Cfg (request configuration) register, adds the REQ descriptor to the REQ queue, and then updates the limit register of the queue.

As long as the REQ queue pointer does not reach the limit of the queue, the RQSTOP bit is reset to the State-attn register and there is space in the RSAP's state queue, the BSI 10 will read the REQ descriptor. Each REQ descriptor defines a frame control and class of service for several SDUs, which includes a location and a size field. The BSI 10 loads the size field into the internal frame counter and the position into the ODUD pointer register. The BSI will continue to process the REQ descriptor (processing across multiple service symbols if necessary) until the entire request object has been processed (ie, only or final descriptor is detected).

The BSI 10 processes the request object and puts a confirmation state on the current page used for the request status queue. Req? The sts_ptr register maintains the current page count and offset in the status queue.

Two RSAPs each have four DMA subchannels, each of which carries several data types: 0 = ODU, 1 = ODU, 2 = CNF and 3 = REQ.

Indicator operation

When ISAP has data and state spaces, ISAP writes incoming frames into a series of IDUs, one per memory page. The IDU is constrained to fit entirely within one page, so a multi-part IDU object may need to be written for a single frame (worst case, up to three IDUs for the maximum length frame at 4K data page size). May be used). Each IDU can be stored in any memory page. For each IDU, the ISAP writes an IDUD containing the status, size (byte count) and location. The IDUD is written to consecutive positions in the indication status queue. Each ISAP has its own status queue.

Each frame is aligned to the start of a currently-defined burst-size memory block (16 or 32 bytes). The first word contains only the FC copied into all the bytes of the first word written with the DA, SA and INFO fields aligned to the first byte of the next word.

The BSI 10 stores the frame IDU in a memory page according to the PSPs read from the PSP queue. Each ISAP takes a phase from its own PSP cue as needed. This allows the frames to be processed in random order because the space can be returned to the PSP queue in a different order than the space used by the BSI. Each PSP is loaded into the Ind? _Idu_ptr register of the ISA. Both page count and offset are loaded from the PSP. Typically the host makes the offset field zero, thus traversing the entire 4K byte page.

When each frame is received, the BSI 10 writes a series of IDUDs that distinguish each IDU, and sets a breakpoint bit in the next IDUD status field at the status breakpoint. Since the frame may potentially occupy a portion of the plurality of pages, the BSI 10 writes first, intermediate, and final IDUD. When the frame crosses the page boundary, the BSI 10 writes IDID.first. If another page turns, IDUD.middle will be filled. In the frame ??, the IDUD. Final is written. The BSI 10 writes the IDUD up to the host-defined limit for the status queue. Separate IDUD / status queues are maintained for each ISAP.

In accordance with one aspect of the present invention, the BSI 10 provides the ability to group incoming frames and generate attention at group or burst boundaries. This significantly reduces the number of host attentions (interrupts) and reduces host overhead.

To group incoming frames into bursts, the BSI 10 defines a state breakpoint. Breakpoints identify the end of a burst of related data. Attention conditions may be generated by the BSI for state breakpoints. Status breakpoints include SA change, token, SA change, DA change, MAC information change, error, and SA copied_frame_counter threshold.

Each ISAP has three DMA subchannels. Subchannel 0 is used for IDU, subchannel 1 is used for IDUD, and subchannel 2 is used for PSP. The indication command / configuration is written to the indication configuration register directly by the host (Ind_mode and Ind_cfg).

Register set

As mentioned above, the BSI 10 has two access ports, which are the ABus interface and the CBus interface. The CBus interface allows host asynchronous access to most registers at any time. The ABus interface is used by the BSI 10 to access memory-based control structures, including queues and mailboxes.

The BSI 10 has three register sets. The first set is directly accessed by the host via the CBus interface, including the control and configuration registers. The second set includes a pointer that must be accessed by sending a memory address to the BSI 10 via the CBus interface and also causing the BSI to transfer data between the memory address (mailbox) and the pointer location. The third set includes a queue limit register. The queue limit register is accessed by placing an address (also write data) in the CBus register and then causing the BSI 10 to perform data transfer as an automatic operation.

Programming interface

summary

The following describes the programmer's view of the BSI 10. Describe what registers are, what they do, and how they are accessed. That is, the functional specification for all registers has been described. More detailed information on how to actually operate the BSI 10 using these registers is provided in the service interface described later.

An overview of the programming interface is described first, followed by a detailed description.

Basic structure

The BSI 10 presents the programmer with three register sets, one mailbox, and an attention / notification mechanism. As described above, the first (and main) register set (CBus register) includes control and configuration registers accessed via the CBus interface, and the second register set (PTR register) is via an external memory-base mailbox. And indirectly host-accessed points (adjusted by the BSI), and the third register set (limit registers) includes queue limits accessed via the CBus interface. All three register sets are host-readable and writable. There are other BSI-internal operation registers but these are only accessible via scan changes.

In initialization, a configuration register, some pointer registers, and a queue limit must be loaded.

Initialization of the configuration register sets the operating conditions for the indicator state machine 12C, the request state machine 14C, and the state / space machine (see FIG. 14). The initial pointer register value defines the data structure location. The initial queue limit defines the boundary of the status queue.

Global control

As described above, the host controls the BSI 10 via the CBus register. The most important registers in this set are Master_attn and Master_notify, State attn and State_notify, Service_attn and Service_notify, and Mode registers.

Master_attn and Master_notify are high level attention registers and provide grouped information about all low level attention and notification registers. The bits in the lower level registers synchronize host-BSI mailbox traffic, queue limit updates, pointer register updates, and internal state machine reporting.

State_attn and State_notify contain an error attention and RUN / STOP bits for each BSI state machine.

Service-attn and Service_notify are used to request a pointer or limit register service.

The mode register sets the main operating parameters and is typically programmed only at power-on or after a software master reset.

Register access

Three sets of registers are accessed in each unique way. The CBus register set uses the CBus interface for access and the other two sets use the Service_attn register to synchronize the transfer between the host and the BSI 10.

CBus register

The CBus register set is used to control and configure the BSI 10. By performing the usual CBus reads and writes, the host can access any register asynchronously. The BSI CBus address space contains 32 positions, not all of which are used. Access to an undefined location does not cause any action.

PTR RAM

The pointer (PTR) register set contains 22- and 28-bit memory pointers, which are called PTR (pointer) RAMs (see FIG. 15). You can only access these registers indirectly using the PTOP function in the host Service_attn register. The PTOP service function allows both reading and writing of the PTR RAM location.

The host loads the 32-bit read / write Ptr_mem_adr register into the mailbox (memory) address where the PTR RAM data will be written or read. Since the 32-bit Ptr-mem-adr register is mapped into one 8-bit CBus address, the host loads a 2-bit byte pointer and then performs four consecutive reads or writes to the same CBus address. The 8-bit Ptr_int_adr register is loaded with the PTR RAM location (5 bits) to be accessed, in the form of a PTOP function (read or write, 1 bit), and the initial Ptr_mem_adr bytes to be accessed. The BSI stores / loads PTR RAM in or from a mailbox.

The PTR RAM address space is 32 locations, but only 22 locations are limited. Accessing an undefined location will produce undefined results.

LIMIT RAM

The third set of registers includes 10 and 9-bit queue limits, which are called limit RAMs (see Figure 15). The host can only access this register indirectly using the LMOP service function in the Service_attn register. The LMOP service function uses read and write to any of the 10 limit RAM locations. The host loads the 8-bit Limit_data register with a new 8-bit LS data value for the accessed limit RAM location. The Limit_adr register is loaded with the limit RAM location accessed (4 bits), the type of LMOP function (read or write, 1 bit), and MS data bits. The BSI 10 stores / loads a limit RAM location in and from the Limit_adr register.

The limit RAM address space is 16 positions, but only nine are defined. Accessing an undefined location will result in undefined results.

State machine control

As mentioned above, there are three state machines under host control, which are the indicator machine 12C, the request machine 14C, and the state / space machine 16. Each machine has a RUN / STOP bit in the State_attn register. Both the host and BSI 10 put the machine into STOP or RUN mode via the State_attn register bit.

The indicator and request machine is in RUN or STOP mode. The machine is in STOP mode at reset or while the STOP bit is set. When the STROP bit is cleared, it is in RUN mode. The host may set the STOP bit to stop all indicator / request operations or the BSI 10 may set the STOP bit in the event of a fatal error.

The state machine 16 is initialized at reset and then idles. While the STOP bit is set, the number of operations that can be performed from this state is limited. When the STOP bit is cleared, all operations can be performed. The host may set the STOP bit to place the machine in the limited functional mode, or the BSI 10 may set the STOP bit in the event of a fatal error. Examples of fatal errors are when an ABus transaction error occurs during the write state or when the machine detects an invalid state.

At any STOP attention, the host must service the appropriate machine and then clear the STOP bit again to resume service.

DMA

DMA is automatically operated by the BSI 10. All data structure pointers are held in PTR RAM and are therefore only accessible via mailbox.

Channel operation

Detailed descriptions and specifications of channel operation are given in the service interface described below. This section only provides a brief overview.

BSI initialization

The BSI is initialized in the following order.

1. The control and configuration registers are loaded via the CBus interface.

2. The PTR RAM is loaded into the state / space machine in 'STOP' mode.

3. The limit RAM is loaded into the state / space machine in 'STOP' mode.

4. Initial space is loaded by running the state / space machine in RUN mode.

5. The indicator machine 12C is enabled to receive incoming data.

6. Request machine 14C is enabled to service the outgoing data.

The control and configuration registers can be programmed while all internal state machines are stopped.

The PTR RAM is initialized by executing the state / space machine 16 while the STOP bit is set. In this mode, state / space machine 16 only responds to PTOP or LMOP commands.

Once the PTR RAM is initialized, the limit RAM must be initialized. This is also done when the state / space machine 16 is in 'STOP' mode. Finally, state / space machine 16 can be run with full functionality by clearing the SPSTOP bit. The state / space machine 16 prompts the host (via the attention) for initial space on all queues.

Once all the space has been initialized, the indicator machine 12C and request machine 14C can be executed.

Indicator operation (Figure 12)

To initiate input, the host sets up two ISAP configuration registers and then clears the INSTOP bit in State_attn. The indicator machine 12C will request the space, and then begin receiving.

The indicator machine 12C will wish to locate the reception. As mentioned above, although the state is written to each IDUD, attention to the host occurs only at the state breakpoint. This breakpoint is to identify the end of the burst of related data. Thus, the host is only called when there is enough work to do.

Request Operation (Figure 13A)

Request machine 14C generates an attention after the state is written. Typically this appears after the completion of the entire request object or after an exception. The host may operate request machine 14C with or without attention. If no attention is used, the host defines the order of each new request (or REQ) and checks the CNFs written to see which frames were sent.

Data space subchannel

The data space subchannels are operated by the indicator machine 12C and the state / space machine 16 in the BSI 10. The subchannel allocates memory to the PSP queue, initializes the queue with enough valid entries, loads the BSI's PSP queue pointer, loads the queue's limit register, and then sets the SPSTOP (space / state STOP) bit in State_attn. It is initialized by erasing. All of this must be done before enabling other machines.

Once initialized, the host and BSI 10 access the PSP queue independently. If the BSI 10 prefetches the PSP from the limit position, this generates a Low_Data_Space attention on its ISAP. The host reads the PSP pointer, and when more PSPs are added, the host clears the attention after updating the limit RAM. PSP prefetching resumes on that ISAP once the limit RAM has been updated.

Status subchannel

The BSI 10 writes a two-word descriptor on the request and the indicator. These are written to the status queue, and the status is queued up to the host-defined limit (potentially plus 1). No_Status_Space attention is generated when a status queue entry is written by the BSI 10 before a host-defined limit. The host updates the queue limit where more state space will be available. By the PSP, updating the limit restarts SAP operations. By the status queue, writing the limit register does not automatically resume SAP operation. The No_Status_Space attention must be cleared to restart SAP.

Register access

CBus register

The CBus register set is accessed asynchronously via the CBus interface. A single read and write is performed. Each host access is internally synchronized, forwarding is performed, and then CB_ACK_asserted. Attention register (only) is a conditional write register. The conditional writing mechanism is described in the event section below.

PTR RAM (Figure 15)

The PTR RAM operation exchanges the PTR contents with an external memory-based mailbox. The address of the mailbox is programmed by the host in the Ptr_mem_adr register. Typically, the host uses a dedicated memory location for the mailbox, so the mailbox address is only loaded once (on initialization). Thus, mailbox-address writing to the BSI 10 is not necessary for each PTR RAM access.

The mailbox address is loaded into the Ptr_mem_adr register by performing four consecutive writes to the appropriate CBus address, and then each byte of the memory address is loaded. The byte is the MS byte first written, which is written after erasing bits [7: 6] in Ptr_mem_adr to zero.

Reading from PTR RAM

The PTR RAM is read as follows. First, the host checks if the PTOP bit is set in the Service_attn register. Second, the host loads the Ptr-int-adr register into PTR RAM location (bits [4; 0]) to read and 1 in PTRW for reads (bits [5]). Third, the host sets the PTOP service bit, which causes the BSI 10 to read the PTR RAM and write the data to an external mailbox. When this operation is complete, the BSI 10 sets the PTOP attention bit again. When the PTOP attention is set, the host can read the mailbox.

Write in PTR RAM

The PTR RAM is written as follows. First, the host checks if the PTOP bit is set in the Service_attn register. Secondly, this loads the Ptr_int_adr register into the PTR RAM location to be written (bits [4: 0]) and zeros in the PTRW bit for writing (bits [5]). Fifth, the host loads an external mailbox with new PTR RAM data. Fourth, the host sets the PTOP service bit, which causes the BSI to read the specified memory location, write data into the PTR RAM, and then set the PTOP attention bit.

Limit RAM (Figure 15)

Limit RAM is accessed via two CBus registers. One is used to hold the limit address to be accessed, and the other is used to exchange data with the limit RAM.

Read from limit RAM

The limit RAM is read as follows. First, the host checks whether the LMOP bit is set in the Service_attn register. Second, the host loads Limit_register into the limit RAM location to be read (bits [7: 4]), one in the LMRW bit for reading (bits [3]) and zeros in the remaining bits. Third, the host clears the LMOP service bit, which causes the BSI to read the limit RAM, write the LS 8 data bits into the limit data register, write the MS data bits into bits [0] of the Limit_adr register, and then write the LMOP attention bits. Set it. Once the LMOP attention is set, the host can read the Limit_adr / data register.

Write in limit RAM

The limit RAM is written as follows. First, the host checks to see if the LMOP bit is set in the Service_attn register. Second, the host writes a Limit RAM location (bits [7: 4]) to which the Limit_adr register will be written, zeros in the LMRW bit for writing (bits [3]), MS data bits in bit [0], and the remaining bits. Load at zero. Third, the host loads the Limit_data register with 8 LS bits of new limit data. Fourth, the host clears the LMOP service bit, which causes the BSI to write a new 9-bit data value into the limit RAM and then set the LMOP attention bit.

event

The BSI 10 uses an attention / notification scheme for service event management. The BSI provides an attention / notification event going in both directions (ie from host to BSI and vice versa).

The BSI 10 generates an attention by setting the attention bit of the appropriate event in the attention register. The host can set an acknowledgment bit to enable this attention to generate an interrupt.

The particular attention bit is the set or cleared signal. The BSI 10 sets a bit to signal an attention to the host. The host clears the bits to signal BSI to complete / acknowledge. This causes the BSI 10 to take some processing action (eg, reading a mailbox).

Attention is propagated through a number of registers, so the BSI 10 provides a two-level structure for the host. This is shown in FIG. At the first (lower) level, each attention register bit is ANDed with a corresponding notification. All masked attentions are then ORed to generate register-level attentions. The Master_attn register is read to observe these register-level bits. Finally, each Master_attn bit is masked with the corresponding Master_notify, and then these are all ORed to generate the BSI INT_output pin.

In the interrupt service routine, the host must read the Master_attn register to determine which other attention registers require reading. The Master_attn register is a read-only register.

Attention Register

The low level attention register is read / written by both the host and the BSI 10 and initialized at reset. Each attention bit is set by the BSI and can be cleared by the host. All low level attention registers are conditional write registers. The event section below provides a specification of the conditional writing mechanism.

Notification register

All notification registers are read / written by the host. These are cleared to zero on reset.

Conditional entry

The host and the BSI 10 write independently to the attention register, but potentially write simultaneously. To ensure that the host does not miss an attention, the attention register uses a conditional-write mechanism.

The BSI 10 can write to the Attention Register at any time, which overwrites any host writes (this ensures that no events are lost if clearing occurs simultaneously as a set).

Each time the host reads the attention register, the reads are stored in the comparison register at the same time. Each time the host writes to the attention register, the current value of the register being written is compared to the compare register. No mismatched bits are written. State_attn if no bits are written. The CWI (Conditional Write Inhibit) bit is set. This bit is not a conventional attention bit, but reflects the result of the last read in the conditional write register. Its corresponding notification bit is always cleared.

The compare register can be written at any time by the host. This feature allows bit erase operations on the attention register.

One usage of attention might be: The host reads the attention register and stores the value. When the attention is served, the host writes the reserved value into the comparison register and the updated value into the attention register. Thus, only the serviced attention is deleted. In this case, the host ignores the CWI bit.

A simpler usage is to use bit-erase operations. The host reads the attention register at any time and does not need to specifically remember the read value. When the host wants to clear an attention, it writes all 1s in the comparison register and 0 in the attentions it wants to clear (write 1 in all other attention bits). Naturally, the CWI bit can be set but can be safely ignored.

Registers, Mailboxes, and DMAs

21, 22 and 23 show BSI registers (control and configuration register sets, PTR RAM register sets, and limit RAM register sets) grouped by pages. The first column in each table represents the register address (hexadecimal). The second column shows the register name. The third column describes the function. The fourth column shows the (initial) register value after reset. The final column indicates whether it is a conditional write register.

There are two resets in the BSI, one is a hardware reset (via the RST input) and one is a software reset (via the MRST bit in the mode register). Both produce the same effect. The single term 'reset' is used to refer to both.

Register details

This section defines the layout of each register and the functionality of each bit mode.

The read / write mode register sets the main system configuration options and does not change on reset. These bits should only be programmed on reset before BSI operation.

SMLB SMLQ VIRT BIG-END FLOW MRST FABCLK TEST

SMLB small burst. When SMLB_0, BST uses 32 bytes (8 words) burst

use. When SMLB = 1, the BSI is a 16 byte (4 word) buffer on the ABus.

Use only strings. BSI sets the indication frame to burst-size

After SMLB = 0, after the 8 word block

Writing four words in half never happens.

SMLQ Small Queue Size When SMLQ = 0, the queue size is 4K bytes.

VIRT VIRT = 0 means the actual address mode on the ABus and VIRT = 1 means the virtual address mode.

BIGEND When BIGEND = 0, it is a small-endian data format.When BIGEND = 1

There is a big-endian format.

When FLOW FLOW = 0, parity is not checked on CBus or ABus.

Parity always occurs on each of the three interfaces. FLOW = 1 day

Flow-through parity is used. When FLOW = 1 parity is

Flows between the ABus and the BMAC, and the incoming data

Unchecked, instead checked when passed to BMAC (by BMAC)

MRST master reset. This initializes the registers to the values shown in Table 7.

do. This bit is cleared after the reset is complete.

FABCLK High Speed ABus Clock. This bit is synchronized between the ABus clock and the ring clock (LBC).

Determine the metastable delay period for On reset, this bit is zero.

This selects the entire ABus clock period as the delay.

All. This bit is then set to 1, and only 1/2 of the ABus clock delay

Used. BSI is at AB_CLK = LBC (12.5 MHz, coincidence of phase), or

For proper operation at AB_CLK = 2 × LBC (i.e. 25 MHz, phase match)

Is designed. Both of these options are available on a chip set (clock distribution unit)

This is easily accomplished by selecting the available clock from.

TEST test mode. Setting this bit to 1 enables the test logic.

Let's do it.

Ptr_int_adr

The read / write Ptr_int_adr register is used to program the parameters for the PTOP PTR RAM service function.

This does not change at reset.

M1 MO PTRW A4 A3 A2 A1 A0

When M [1: 0]] writes these 2 bits, it is written to access the Ptr_mem_adr register.

The indicated byte is programmed. This means that the memory address

Four consecutive writes (MS bytes) when loaded into the Ptr_mem_adr register.

To initialize the byte pointer for

Is set. The BSI writes these bits after each write to Ptr_mem_adr.

Increase internally.

PTRW This bit determines whether the PTOP function is read or written.

When PTRW = 0, it is a write, and when PTRW = 1, it is a read.

If A [4: 0] writes these five bits, the PTR RAM address for subsequent PTOP functions

Is set.

Ptr_mem_adr

The read / write Ptr_mem_adr register is used to set the word-aligned (byte) memory address used for data transfer of the PTOP PTR RAM service function.

memory＿addr [27:24] memory＿addr [23:16] memory＿addr [15: 8] memory＿addr [7:02]

Bits [1: 0] must be zero (they are forced to zero internally).

This CBus address is a window in four internal byte registers that will be used as a memory address for transfer between the PTR RAM and external memory using the PTOP mechanism. The 4-byte register is loaded by first setting the M [1: 0] bits in the Ptr_mem_adr register and then writing continuously to this address. The byte must first load the MS byte after setting M1 = M0 = 0. The BSI increments the byte pointer internally after each write or read. This register is initialized with a silicon revision code at reset. The revision code remains until the host overwrites it.

Master_attn and Master_notify

The read only Master_attn and Read / Write Master_notify registers provide a first level view of the BSI Attention. Each bit represents a state of a second-level attention / notification register pair. The bit is set in the Master_attn register when the corresponding attention register has the assumed notifyable attention. Writing to the Master_attn register does not change its contents, but is allowed. Master_attn is cleared to zero at reset.

STA NSA SVA RQA INA Rsvd Rsvd Rsvd

The STA State_attn register has one of the attention bit sets.

The NSA No_space_attn register has one of the attention bit sets.

The SVA Service_attn register has one of the attention bit sets.

The RQA Req_attn register has one of the attention bit sets.

The INA Ind_attn register holds one of the attention bit sets.

State＿attn and State＿notify

The read / write State? Attn / notify registers provide attention to the main states in the BSI. This includes state machine state and parity errors and is initialized at reset.

ERR BPE CPE CWI CMDE SPSTOP RQSTOP INSTOP

ERR Error, cleared at reset. By the BSI in case of an unrecoverable error

Is set. An error is an ABus transaction error (ABus error)

Flow read / write data is reported in the descriptor) and internal logic

Errors and errors when the state machine enters an invalid state.

Error read / write data is reported in the descriptor) and internal logic

Errors and errors when the state machine enters an invalid state.

BPEBMAC parity error. Supported on reset. BMAC parity is always frame dynamic

Checked inside This attention is set when an error occurs. CBus L

Error. Cleared on reset. CBus when FLOW parity is used

Parity is checked. If an error occurs, this attention is set. hose

If there is a CBus parity error at the time of writing, the write will be suppressed.

No CWI Conditionalization. Cleared on reset. This bit is all conditional

Reflects the result of the last write to the input register (attention register).

I = 1 indicates that one or more bits are well written at the time of the final conditional write register.

It means that it did not match.

CMDE command error. Cleared on reset. Invalid operation performed by the host

Is set by the BSI. This is an invalid value Ind＿hdrlen regis

Occurs only when loaded into a table (INSTOP attention is also set).

Set at SPSTOP reset, or space / state error due to unrecoverable error

It is set by the BSI when a scene enters reduced＿functions＿state.

The state machine can only be in reduced＿functrions＿state

We will perform a POP or LMOP request.

RQSTOP Set under three states. First, at reset, secondly, request queue

When the machine enters an invalid state or detects an internal error,

Secondly, it is set when an ABus error occurs upon CNF writing.

INSTOP Set under three states. First, on reset, second, on indicator

The machine detects an internal error or enters an invalid state.

Third, when the host loads an illegal value into the Ind＿hdrlen register

It is set at the time.

Service＿attn and Service＿Notify

Read / Write The Service attn / notify registers provide attention to service functions. The host may set any of the attention bits to generate an attention, but does not affect the internal BSI state. Serviceattn is set to OxOf at reset and the service notification is cleared to zero.

Rsvd Rsvd Rsvd Rsvd ABRO AVR1 LMOP PTOP

ABR? RSAP? Abandon request. BSI wants to waive requests on RSA

Is deleted by the host. If RQABORT is set, this RSA

Terminate the request on the table. The host can write 1 to this bit.

This prevents the request from being abandoned or abandoned.

All. This does not adversely affect the BSI. Request to host-for

USR Attention is set when it is set (it is set at Req tattn) and

Further processing is suspended)

The LMOP BSI passes data between the limit RAM and the Limit＿data register.

Supported by the host when desired. Direction of delivery (read or note

Input) is determined by the LMRW bit in Limit_adr. Limit RAM

The dress is in Limit＿adr. While LWOP = 0, the host will enter Limit＿

Do not change the adr or Limit_data registers.

PTOP BSI will pass data between the PTR RAM and a limited memory location.

Cleared by the host when desired. The delivery direction (read or write) is

It is determined by the PRRW bit in Ptr \ mem \ adr. PTR address is

It is in Ptr＿int＿adr. While PTOP = 0, the host is Ptr＿mem＿

Do not change the adr or Ptr \ mem \ adr registers.

No＿space＿attn and No＿space＿notify

Read / Write The No? Space? Attn / notify register provides an attention that is generated when any queue comes out of space or out of a valid entry. The host can set any of the attention bits to generate an attention for test purposes only. This should not happen during normal operation. The No＿Data＿Space attention is automatically set or cleared by the BSI. The No＿Status / Space attention is set by the BSI and must be cleared by the host. At reset, No＿Space? Attn is set to Oxff, and No＿Space? Notify is cleared to zero.

NROS NRIS LIOD NIOS LI1D NI1S LI2D NI2S

NR? S RASP? No state space. At reset or BSI hosts CNF

Two limit RSAP? Set by the BSI when writing to the status queue position

do. By internal pipelining, the BSI adds two or more CNFs to the queue.

I can write it. Thus, the host has space available in the queue.

You must set one less limit. To allow this bit

Must be cleared by the host, that is, the BSI

We will not serve requests until we have space.

LI? D LOW ISAP＿ Data space. On reset or last use

ISAP? Set by BSI when prefetching PSP from PSP cue position

do. Can be set or cleared by the host for testing purposes.

If PSP fetching stops because there is no PSP entry, then the appropriate limit register

Fetching resumes automatically when is updated. This bit

Tells the PSP queue is low. The amount of warning is in the frame length

Note that it depends. Always BSI when this attention occurs

One or more pages (4K bytes) available for

to be. Another FDDI full-length frame (after the current frame)

It will not fit in space.

NI? S ISAP? No state space. On reset or ISAP＿? In the state queue

The BSI IDUD in the last available entry. To the BSI

Set by When this happens, the BSI stops copying on that ISAP.

All. This bit is set by the host to enable ISAP copying.

It must be cleared, i.e. until the BSI has space to write the DUD.

Do not copy over ISAP.

Limit＿adr

The read / write Limit_adr register is programmed by the limit RAM location, MS data bits, and the type of LMOP service function to be performed. It is not changed at reset.

A3 A2 A1 A0 LMRW Rsvd Rsvd D8

If A [3: 0] writes these four bits, the limit for subsequent LMOP service functions

The RAM address is set.

LMRW This bit determines whether the LMOP function is read or write.

When LMRW = 0, it is write; when LMRW = 1, it is read.

D8 This is the most significant data bit for swapping with addressed registers.

All.

Limit＿data

The read / write Limit＿data register is loaded with the eight lowest limit RAM data bits to be delivered by the LMOP service function. The most significant data bit is exchanged for bit [0] in the Limit # adr register.

Limit＿value [7: 0]

It is not changed at reset. For writing to the limit RAM (LMOP with LMRW = 0), this register is loaded with the new limit value written to the selected limit register. For reading from the limit RAM (LMOP with LMRW = 1), the register is loaded with the current limit in the limit register selected by the BSI. Note that all bits must be valid in the OMIT register, that is, even if a small queue is used, all bits are compared with the associated pointer.

Req＿attn and Req＿notify

The read / write Req? Attn / notify registers provide the attention generated by both RSAPs. The host can set the attention bit to generate an attention and does not affect any internal BSI state except the USR bit. At reset, Reqattn and Reanotify are cleared to zero.

USR＿0 RCM-0 EXC＿0 BPX＿0 USR＿1 RCM＿1 EXC＿1 BRK＿1

USR RSAP? Unserviceable request. When the request cannot be processed

It is set by the BSI. There are three causes, Rq＿cls

Is not suitable for the ring state (i.e. immediately after the ring is in operation,

), When there is no CNF status space, as a result of host abandonment (Service

Via ＿attn). Request while this bit is set

Tests will not be processed on that RSAP. Requests from O

Set by the BSI when the object has finished processing.

RCM_? RCA_? Request complete. The BSI is responsible for the

Set by the BSI when processing is complete.

EXC＿? RSAP? exception. RSAP? Set by the BSI whenever an exception occurs

All.

BRK? RSAP? Breakpoint. RSAP? Set by the BSI when a breakpoint is detected

All.

Req＿cfg

The read / write Req_cfg register is programmed with the operational parameters for each RSAP. Note that the reset does not affect this register. Such a register may change between requests, for example, when no request is loaded in a particular RSAP. Thus, the host must ensure that the BSI has fully processed all requests in the REQ queue (as defined by the limit), at which time the host can change this register.

TT1 TT0 PRE HLD FCT SAT VST FCS

TT [1: 0] Threshold for the output data FIFO before requesting a transmission. 00 = 8

Word, 01 = 16 words, 10 = 64 words (not applicable to Rev A), 11 = 128 words

(Not applicable to Rev A). The threshold is reached or the entire frame

Transmission is initiated when in the FIFO.

PRE preemptive / prestage. In Req0＿cfg this is a preprogrammed option

All. In Req1 \ cfg this programs the prestage option (HLD

With a bit). Preemption: When PRE = 0, the request on RSAP＿0 is RSAP＿1.

Will not preempt requests from the award. When PRE = 1, RSAP＿0

RSAP # 1 can be preempted. Prestage: When PRE = 0, the request is

It will not be prestage (when the HLD bit is 1). When PRE = 1

The RSAP'1 request will prestage. If the HLD bit is 0,

RSAP # 1 will prestage. RSAP＿0 makes immediate requests

Note that you always prestage, except.

Maintain HLD. There is an active request active on this RSAP when HLD = 0.

Service class is non-immediate, no data in FIFO, fetched into BSI

If no valid REQ is specified, the BSI terminates the service opportunity on this RSAP.

If HLD = 1, the BSI will service until the request is completed.

Will not terminate the opportunity (when TTH or TRT ends BMAC will

Ends the service opportunity). Prestage on RSAP＿1

It is also affected by. When HLD = 0, prestage is applied to the PRE bit.

Enabled regardless (but for immediate service class

Not so). When HLD = 1, prestaging is determined by the PRE bit.

All. This option may potentially waste ring bandwidth, so

This option should be used with caution. But preoccupied on RSAP＿0

Can use large buses or interrupts within the host system.

HLD will also be needed to hold the atmosphere and stop early token release

to be.

FCT frame control transparent. When this bit is set, the FC returns data (BEQ.

Not from the F descriptor. Each of the request bursts

The FC field of each frame updates the internal copy of the transmitted FC,

When fully checking, compare the FC of the received frame.

Is used. When FCT = 0, all FC bits in the received frame are 'good'

REQ <FC> must be matched for the identified frame. When FCT = 1

Only needs to match the C, L and r bits.

SAT source address transparent. SAT pins can be accessed via requests on this RSA.

It is moving. This is a BMAC SAT pin or SAIGT or both depending on the application

(SAT, STRIP, and FCST are general purpose frame-synchronous

Output pins). Full verification when SAT = 1 requires use of EM input pin

do.

VST void stripping. Strip pin is driven by request on this RSAP

do. This can also drive BMAC strip pins or SAT pins, depending on the application.

have. Invalid stripping works as follows. Current service period

At the end of the meeting, two My＿Void frames are initiated by the BMAC,

BMAC returns My＿Void frame, receives a token,

Void received or MAC frame other than My＿Claim received

Striping continues until a MAC reset occurs. This service opportunity

All the frames in are stripped using this method.

Disable RCS Frame Check Sequence. When this is set the BSI will return this RSAP

The FCST pin through the request on the board. This depends on the application

It also drives the BMAC FCST pin or the SAT or SAIGT pin. Req＿efs.FCS

Bits are independently predicated to satisfy matching frame check criteria.

Determine if any need a valid FCS. This bit is typically

Program the BMAC so that it does not connect the generated FCS to the forwarded frames.

It is used to

Req? ＿Efs

The read / write Req? Efs register defines the expected frame state for the frame identified on each RSAP. Frames must meet program criteria to be counted as matching frames. In addition to the frame parameters defined by this register, the frame must have a valid ending delimiter. This register is not changed at reset. When an unmatched frame is received, the BSI closes the request and generates RCM, EXC and BRK Attention. Any remaining REQ in the request is fetched until it encounters REQ.L or REQ.only. It will then resume at the next REQ.1 or REQ.only (another form of REQ will be a consistency failure).

VDL VFCS EE1 EE0 EA1 EA0 EC1 ECO

VDL valid data length. The acknowledgment frame received when VDL = 1 is matched to the match verifier.

It must have a valid data length that meets the criteria. When VDL = 0

It is not.

Acknowledgment frame received when VFCS valid FCS.FCS = 1 is based on matching frame acknowledgment

Must have a valid FCS to meet Yes, when FCS = 1

I can't.

EE [1: 0] Estimated E indicator selection: 00 = Anything is good, 01 = R, 10 = S, 11 = R ｜ S

EA [1: 0] Estimated A indicator selection: 00 = Anything is good, 01 = R, 10 = S, 11 = R ｜ S

EC [1: 0] Estimated C indicator selection: 00 = Anything is good, 01 = R, 10 = S, 11 = R ｜ S

Ind＿attn and Ind＿notify HA14-15

The read / write Ind_attn / notify register provides the attention generated by ISAP. The host can set any attention bit to generate an attention, but this does not affect any internal BST state. Both registers are cleared to zero upon reset.

Rsvd Rsvd ExCO BRK1 EXC1 BRK1 EXC2 BRK2

EXC＿? ISAP? exception. Cleared on reset. When an exception is thrown on this ISAP

Set by the BSI. To close the copy on the ISAP.

It can also be set by the string (Ind \ gdrlen / Ind \ threshold register

It is convenient when updating. The ISAP while it is set

Copying over is impossible.

BRK? ISAP? Breakpoint. Cleared on reset. Indicator on this ISAP

Set when a breakpoint is detected. When the host sets this bit

No action is taken either.

Ind＿Inthreshold

The Ind_threshold read / write register is programmed with the ISAP threshold counter load value. It is not changed at reset. This register can be loaded when the Ind_attn.EXC bit of the INSTOP or ISAP is set.

THR [7: 0]

THR THR = 00-FF. This value is counted in the indicator module whenever SAP changes.

It is loaded in the site. Each valid frame copied onto the SAP counts a counter.

Decrease. BOT bit is an ISAP state breakpoint when counter reaches zero

Attention is generated and the counter reloaded.

The read / write Ind_mode register defines common ISAP configuration options. It is not changed at reset. This register should only be changed when INSTOP is set. It can always be written with the same (current) current value (used to enable one shot sampling on RSAP_0).

SM1 SM0 SKIP Rsvd BOT1 BOT2 BOB BOS

SM [1: 0] sort mode, where these bits indicate that the BSI clears indicator data on the ISAP.

Decide how to do this. 00 = synchronous / asynchronous, 01 = internal / external, 10 = header

/ info, 11 = High-priority / low priority asynchronous. More details

See the Service Interfaces chapter for more information.

SKIP Skip Enable. Disable skipping on ISAP＿0 when SKIP = 0.

Skip enabled when SKIP = 1. For more details

See the Service Interfaces chapter (indicators). This regis

Writing to the data increases the skipping characteristic.

Breakpoint on the BOT threshold. Induces Frame Count Threshold Indie on ISAP

Allows you to generate a Kate breakpoint attention. BOT1 uses ISAP＿1

And BOT2 is for ISAP # 2.

Breakpoint at the end of the BOB burst. Enable burst end detection

Causes breakpoint attention. Indicate for details

See the operation section.

Breakpoints on BOS Service Opportunities. End of service opportunity indicator breakpoint

It generates an attention.

Ind＿cfg

Read / Write The Ind_cfg register sets the copy criteria for each ISAP. See the section on indicator operations (ISAP copying and sorting) in the Service Interface section below for details. It is not changed at reset.

CC7 CC6 Rsvd CC4 CC3 Rsvd CC1 CC0

CC [7: 6] Copy control from ISAP＿0 company. 00 = do not copy. 01 = address

Copy if identified and MFLAG. 10 = address is identified and OR MFLAG

If it is, copy it. 11 = Unconditional copy.

CC [4: 3] Copy control on ISAP # 1. Same as copy control on ISAP # 0.

CC [1: 0] Copy control on ISAP # 2. Same as copy control on ISAP # 0.

Ind＿hdrlen

This read / write register defines the length of the frame header in the header / Info sort mode. The 8-bit register is loaded with the number of 32-bit words in the header. Because frame FC is written in a separate word, it is counted as one. For example, when trying to separate after 4 bytes of header data in a frame having a long address, this register should be programmed to 05 (1 word FC, 1.5 DA, 1.5 SA, 1 HDR? Data). Registers should not be loaded with less than 4 values. If loaded with a value less than 4, the BSI sets the attention to CMDE and INSTOP. Setting INSTOP will stop all indicator processing. This register must be initialized before setting the sort mode to header / Info. Note that the header is always written as a full burst. It is not changed at reset. This register will stop all indicator processing when INSTOP is set. This register must be initialized before setting the sort mode to header / Info. Note that the header is always written as a full burst. It is not changed at reset. This register may be changed while INSTOP or Ind_attn.EXC is set.

Header length in words [7: 0]

Compare HAIF

The read / write compare register is used as part of the conditional write mechanism. It becomes 0 at reset.

Comparison value [7: 0]

The value in the compare register is used for comparison with the write access of the conditional write register. The comparison register is loaded on the read portion of any conditional event register or by writing directly to it. In the event of a conditional write, only the bits with the same current value as the corresponding bits in the compare register will be updated to the new value.

DMA

There are five DMA 'channels', two for sending SAP and three for receiving SAP. The software initially has to load some of the BSI registers (basically a queue pointer), but once enabled, the BSI itself loads most of the registers.

Table 4 below summarizes the enable registers used by each DMA channel.

Table 4

ch Reference Name Transmission method 0000 Req1＿odu＿ptrReq1＿dud＿ptrReq1＿sts＿ptrReq1＿req＿ptr Output Request ODUs Fetching Output Request ODUs Fetching Confirmation Save State Output Request Fetching 1111 Req0＿odu＿ptrReq0＿dud＿ptrReq0＿sts＿ptrReq0＿req＿ptr Output Request ODUs Fetching Output Request ODUs Fetching Confirmation Save State Output Request Fetching 222 Ind2＿idu＿ptrInd2＿sts＿ptrInd2＿psp＿ptr Save indicator IDUs Save indicator IDUs PPS fetch 333 Ind1＿idu＿ptrInd1＿sts＿ptrInd1＿psp＿ptr Save indicator IDUs Save indicator IDUs PPS fetch 444 Ind0＿idu＿ptrInd0＿sts＿ptrInd0＿psp＿ptr Indication IDUs Storage Indication IDUs Storage PSPs Table 3-4 Fetching DMA

All DMA operations for the ABus are prioritized. The priority of the bus request is generally: Priorities are specified from high to low.

1. Read request data

2. Write indicator data

3. Enter Indicator Status

4. Fill in the request status

5. PSP Queue Reading

6. Mailbox access

7. PTR RAM Operation

However, in order to moderate performance, the BSI dynamically changes the priority.

Service interface

The following describes the MAC user data service provided by the BSI 10. Section 1 defines a range of options for the request service, that is, defined by the host-program register and the RSAP descriptor. Section 2 describes how the host configures and operates RSAP. Sections 3 and 4 provide processing similar to that for ISAP, ie defining options and configuration / operation. The last section defines the configuration and operation of the status generation / space management module 16. As mentioned above, the BSI 10 provides five simplex SAPs. There are two RSAPs (requests) and three ISAPs (indicators). Each SAP has its own copy (ie configuration) of a particular register. In the following description, the generic name to which the SAP register is referenced is used. By way of example, each RSAP has a configuration register. The two registers are referred to as Req0'cfg (RSAP'0) and Reg1'cfg (RSAP'1). For simplicity, the following refers to registers as generic names, ie Reg? Cfg. To identify the appropriate SAP, you can substitute 0 or 1 in the name.

The request service is provided by the request machine 14C (see also FIG. 13A) realized as several cooperating state machines (see FIGS. 13B to 13F). Similarly, the indication service is provided by the indicator machine 12C, which is realized as several cooperating state machines as shown in FIG.

Request Service

There are two requests SAP, RSAP'0 and RSAP'1, each with a high priority and a low priority. RSAP is mapped in several ways. One example maps synchronous traffic to RSAP'0 to asynchronous RSAP'1, but the BSI 10 does not limit either RSAP to this purpose. Since both RSAPs have almost the same functionality, the following description applies to both. An important difference is the interaction between RSAPs due to their relative priority.

As mentioned above, the host programs the operating characteristics of RSAP via four registers. There are two configuration registers. There are ＿cfg registers (auxiliary) and Reg? Desc registers, there is an attention / notification register pair, and there are Regnattn registers and Regifynotify registers. The queue is used to transfer REQ descriptors, which are in the internal RegDesk register.

The host configures RSAP for key operating parameters by programming Reg? Cfg through the CBus interface.

Referring to FIG. 13A, to request an output request, a stream of REQ descriptors is passed to the request state machine 14C via the REQ queue. As long as the queue contains descriptors, the request state machine 14C will continue to fetch and process the descriptors.

Each REQ descriptor contains an instruction field with an output request parameter (loaded in the internal Reg? Desc register), a position field loaded in the pointer register, and a frame count field loaded in the counter. An acknowledgment state object may optionally be generated for each request object.

Attention and notification registers define the behavior of the request event.

The meaning of the output request is as follows:

Output request {

8: Req＿cfg; / * Loaded in the BSI Reg? Cfgcfg * /

8: Regefs; / * Out of frame status on Beq * /

3: Reg? Attn; / * Attention * /

3: Regnotify; / * Attention to Notify * /

REQ descriptor. F; / * REQ-first * /

REQ descriptor. M; / * REQ-middle * /

To

To

REQ descriptor. L; / * REQ-middle * /

}

Req＿cfg, efs, attn, notify {

8: rqopt; * / Request configuration option, by RSAP * /

8: Reqefs; * / Expected frame state on Req, by RSAP * /

4: Req＿attn; * / Attention on this RSAP, shared attn register * /

4: Req＿notify; * / Attention to Notify * /

REQ {

6: UID; / * User ID (copied to CNF) * /

8: size; / * Number of frames in REQ part * /

4: / Cnf＿cls / * identification rating * /

8: fc; / * Request level * /

32: loc; / * Location of ODUD stream (also F / L flag) * /

Also:

ODUD {

16: size; * / number of ODU bytes at loc (13 bits used) * /

32: loc; * / ODU and F / L Flag Positions * /

Req? ＿Cfg

TT1 TT0 PRE HLD FCT SAT VST FCS

Req? ＿Efs

VDL VFCS EE1 EE0 EA1 EA0 EC1 ECO

Req＿attn and Req＿notify

USR＿0 RCM＿0 EXC＿0 BRK＿0 USR＿0 RCM＿1 EXC＿1 BRK＿1

REQ

Rsvd UID size Cnf＿cls Rq＿cls fc loc

Rsvd bits [31:30] are reserved, must be programmed to zero.

UID [5: 0] Host (user) definition ID field. Each CNF listed is the current REQ.F

Copy the UID field from the CNF.UID field.

Count of the number of frames indicated by the ODUD stream pointed to by size [7: 0] loc.

Cnf＿cls [3: 0] Confirm＿class [RFIE]. Confirmation grade of service values are shown below

All. This field was sampled only on REQ. 1 or REQ.

The rank has four bits, repeated: when R = 0, all frames in the REQ

Fetch that; When R = 1, the transmission of the first frame of the REQ is repeated.

All. Full / Txr: when F = 0, check transmitter; When F = 1, complete expansion

sign. Medium: Intermediate CNF disabled when I = 0; Intermediate CNF is disabled when I = 1

Twill. End: When E = 0, End: CNF disabled; When E = 1, End: CNF enabled.

Table 5

Confirm rating

cnf＿cls Check requested grade x000 Invalid (consistency failure) xx10 Invalid (consistency failure) 0x00 You (unchecked, except on exc) 0001 Tend (tx check, CNF completed on exc) 0011 Tint (tx check, CNF complete on exc) 0101 Fend (enough check, complete CNF on exc) 0111 Tint (enough check, complete CNF on exc) 1100 Non-R (unchecked, except on exc, repeating frame) 1001 Tend R (tx check, CNF complete int on exc, repeat frame) 1011 Tint R (confirm tx, CNF complete on exc, repeat frame) 1101 Fend (full check, CNF complete on exc, repeat frame) 1111 Tint R (enough check, CNF complete int on exc, repeat frame)

Rq＿cls [3: 0] Request / Release＿class.

Request / release grade values are shown below.

This field is sampled only in REQ 1 or REQ. Only. Confirm

Please refer to the verification instructions for details on rating operation.

It is.

Table 6

Rq＿clsvalue Rq＿clsName Grade form THTE / D Token capture Token release 0000 None None none none 0001 Apr1 Async pri1 E non-r non-r 0010 Apr2 Async pri2 E non-r non-r 0011 Apr3 Async pri3 E non-r non-r 0100 Syn Sync D any capt 0101 Imm Immed D none none 0110 ImrnN Immed D none non-r 0111 ImmR Immed D none restr 1000 Asyn Async E non-r non-r 1001 Rbeg Restricted E non-r restr 1010 Rend Restricted E restr non-r 1011 Rcnt Restricted E restr restr 1100 Alynd Async D non-r non-r 1101 RbegD Restricted D non-r restr 1110 Rendd Restricted D restr non-r 1111 RcntD Restricted D restr restr

-enabled, D = disabled, non-r = non-restricted, restr = restricted, capt = captured

fc [7: 0] Frame control field to be used if FC transparency is not available. This field is

It is decoded to determine whether to assume OCLM or RQBCN. this

Decoding is always active regardless of frame control transparency, for example.

This field compares the received frames upon confirmation (without FC transparency).

Is used.

loc location. Bit [31] = first tag, bit [30] = final tag, bit [29:28] = reservation

Bits [27: 2] = Memory word address of the ODUD stream. Expect bit [1: 0]

00, not checked.

ODUD

rsvd size loc

rsve Reserved, unchecked.

Size [12: 0] Count of the number of bytes in the ODU (in the rate_size). Size is 0

Note that it may be.

loc position = bit [31:30] = F-L flag. Bits [29:28] = reserved. Bits [27: 0] = 0

Memory byte address.

CNF

rs fra frs tfc cfc f-1 UID fc cs Rsvd

rs [3: 0] request status, [4: code]

middle

[0000]-you

[0001]-lien

[0010]-Part＿done

Breakpoint

[0011]-Service＿loss (brkpt)

[0100]-reservation

complete

[0101]-Completed＿BC

[0110]-Completed＿OK

Exception complete

[0111]-Bad＿conf

[1000]-Underrun

[1001]-Host＿abort

[1010]-Rad＿Ringop

[1011]-MAC＿about

[1100]-timeout

[1101]-MAC＿reset

[1110]-Con＿fail

error

[1111]-Internal or fatal ABus error

fra [3: 0] frame attribute = [MFLAG AFLAG TC]. MFLAG from BMAC 0 = -mine, 1 =

ME), AFLAG (0 = -DA match, 1 = DA match) from BMAC, TC = end status

(11 = Frames Stripped, 10 = Format Error, 01 = ED, 00 = Other (i.e. MAC

Reset or token). This field is only valid for complete verification.

frs [7: 0] frame state = [VDL VFCS EAC] .VDL = valid data length, VFCS = valid FCS

, FCS, E, A, C = control indicator, 00 = non, 01 = R, 10 = S, 11 = T. this is

If the frame ends with ED, it is valid only for complete verification.

tfc [7: 0] Frame count transmitted. A program successfully sent by BSI and BMAC

Include the number of layers. This field is valid for the confirmation class.

cfc [7: 0] Count of checked frames. This field is only valid if full verification is required.

Filial

f-1 First and last tags in bits [31:30] of the second word.

The UID [5: 0] bits [29:24] are copied from the UID field of the current REQ.F / 0.

fc [7: 0] The frame control field of the last frame of the identified burst. For complete verification

Only valid.

cs [5: 0] Acknowledgment status [T R E P U F Ft]. [1: Tx class 1: Bad＿Ringop 1: exception

1: Parity＿Error 1: Unexpected frame state 1: Full＿Confirm

2: Frame＿Type]. Restrictions, such as returned by BMAC

Tx class = 0, or TxClass = 1.Bad＿Ringop bit for non-limiting

The ring is bad after transmission or before all return frames are checked

Set when in operation. If an exception is raised, the exception bit is raised

It will be set in the generated CNF.cx [] (Note, EXC Attention is also set

do). Parity error = 0, parity error for good frames

Parity error = 1 for frames received with. Parity is

Checked from the FC to ED, including the if mode. The flow is set.

When the frame state does not match the programmed expected frame state

Is set to an unexpected frame status bit (see Req? Efs).

Applies only for complete verification. Full＿Confirm Bit Request

Is set when is for full verification. Frame＿Type bit

Reflects the shape of the frame that has been fully checked, where 11 = My＿Void,

10 = Other＿Void, 01 = Token, 00 = Other.

Request operation

Configuration

In order for the request machine 14C to operate, its space subchannel had to be initialized. The request machine 14C may then be enabled by resetting the RQSTOP bit in the state attn register and the No＿State＿Space bit in the Space? Attn register. Next, when the REQ queue limit is updated, the request machine 14C has serviced RSAP. RSAP is configured by loading its Req? Cfg register. This register affects all subsequent requests on this RSAP. Each REQ.F descriptor loads a Req? Desc register on-the-fly, thus affecting only the current request object.

The following operation will start the request service.

1. Allocate memory space for the CNF and REQ queues.

2. Program the configuration register via CBus.

3. Write the initial REQ into the REQ queue.

4. Reset the RQSTOP bit in State_attn.

5. Reset the NR? S bits in Space? Attn.

6. Write to the REQ queue limit register.

The BSI 10 will then fetch and process the REQ descriptor until it reaches the REQ limit or exceeds the state space. Upon completion of each request object, an RCM? Attention is generated, and the CNF object is written (when programmed).

work

Active, valid requests

Request machine 14C processes active and valid requests. Requests are active when:

1. When the REQ queue pointer has not passed a limit.

2. When the CNF queue pointer has not reached the limit.

3. Req＿attn for RSAP. When the USR bit is zero.

Requests are valid when:

1. When the REQ parameter is acceptable.

2. Rq＿cls is compatible with the current ring state.

As each REQ is fetched, Req? Req? Prt updates the next REQ, while the current (not updated) value is compared to Req? Req? Limit. If they are the same, the final queue REQ is just fetched. Therefore, no further REQ prefetch is prohibited until the host writes to Req? Req? Limit.

When an exception is raised, request machine 14C generates a CNF and terminates the request. There must be space in the CNF queue to write the state to, or the request machine will not be able to complete the request. To avoid this problem, REQ will not be processed if there is no space in the queue to write at least two CNFs.

Once a request is out of service, the USR Attention is set to prevent subsequent requests.

1. Whenever the request object first REQ is loaded, the UID, Cnf_cls, Rq_cls and FC are loaded into an internal Req_desc holding register, thus setting these parameters for the entire request object. The second word of each REQ (part) is loaded into the Req? Dudptr register. If any of the parameters are not acceptable, the request is abandoned.

2. Request Rq_cls is checked against the current ring state, and if the class and ring state are incompatible, the request is abandoned. For example, when the ring is inoperative, the immediate Rq_cls should be indicated, and for the non-immediate Rq_cls the ring should be activated.

Request processing

Request machine 14C reads the request object and optionally generates a confirmation object. In order to maximize performance, REQ (also their associated ODUD) is prefetched by request machine 14C and charges an otherwise-idle bus cycle.

When the first REQ of the request is loaded, the request machine 14C indicates the desired RQRCLS to the BMAC, which instructs the BMAC to capture the appropriate token. On the other hand, the first ODUD is prefetched and loaded into the Req? Odu? Ptr (PTR RAM) and Req? Frm? Cnt internal registers. When prestaging is possible or a service opportunity arrives on this RSAP, the data from the first ODU is fetched into the request burst FIFO and the request machine 14C requests transmission from the BMAC. When transmission begins (frame is committed). The ODUD is marked invalid / used and the next ODUD is fetched. This continues until all frames on the request object have been sent or an exception is thrown that terminates the request incompletely. The CNF object will be written if it is programmed in Cnf_cls or an exception occurs. The request may be serviced over one or more service opportunities depending on whether or not the THT has expired.

The request machine processes requests on two RSAPs simultaneously. Their interaction is determined by the HLD and PRE configuration bits.

Null Object

According to one feature of the invention, any object with a zero size field is supported by the request machine 14C. The request can have zeros in the frame count. This is typically used to terminate a request without necessarily sending data. As an example, to terminate a restrictive conversation, REQ.L with a frame count of zero may be queued. This will cause the request machine 14C to instruct to capture and release tokens of the grade specified in the BMAC. This is summarized below.

1. REQ with size = 0. 1: The BSI 10 latches the REQ descriptor field, and then

Fetches the following REQ: RQRCLS is sent to BMAC, but RQRDY is negative

It remains fixed.

2. REQ with size = 0. Middle: The BSI 10 fetches the next REQ.

3. REQ with size = 0. Only: The BSI 10 requires the capture of an appropriate token,

In the case of RQFINAL, the request is terminated.

4. REQ with size = 0. Final: BSI 10 captures tokens, sets RQFINAL

Next, the request is marked complete (the request object returns zero frames).

Can have).

The ODUD may also have a zero byte count. This is useful for fixed protocol stacks. A layer can be fetched, and if there is no data to add to the frame, the layer can add the ODUD to the list with a byte count of zero. Unlike requests, ODUD objects must have at least 4 bytes (for short addresses).

Request exception

The exception terminates the request. Exceptions can be thrown as a result of external errors (BMAC, ring, ABus), i.e. from host errors (consistency failures) in the request object, lack of state space, or bad ring states (operational / inoperative). do.

One type of host error is inconsistency in the request object. Request machine 14C checks for inconsistencies in the REQ and ODUD streams. The following event is detected as a consistency failure.

1. REQ.F with invalid Cnf＿cls (as shown in the confirmation class table).

2. REQ.F with Rq＿cls = 0

3. REQ.F when the previous REQ was not (REQL; ｜ REQ.O)

4. When the previous REQ was (REQ.L | REQ.O), the REQ rather than the REQ.F

5. ODUD.F when previous ODUD was not (ODUD.L | ODUD.O)

6. When the previous ODUD was (ODUD.L | ODUD.O), ODUD instead of ODUD.F

7. With zero byte count, the last flag is set ODUD.

If a consistency failure occurs, the request terminates in the proper state. Following a consistency failure, request machine 14C finds the end of the current object (REQ or ODUD). If the current descriptor is not the end (the last bit is not set), the request machine 14C fetches subsequent descriptors until it detects the end. The next descriptor must then be the beginning of the object (ie, follow the consistency rule as described above).

Confirm

The host can request confirmation on the request object. Request machine 14C reports the confirmation status in two ways. That is, via the attention and the CNF descriptor. Attention is always used by the request machine 14C, so the host must use the notification register when needed.

The CNF descriptor will be written when an exception is thrown (regardless of Cnf_cls), when the request completes (for end or int Cnf_cls), or when a breakpoint occurs (in int Cnf_cls only). CNF write is controlled via bits [1: 0] of REQ.Cnf_cls. Bit 0 (end) enables CNF write on exception / completion, and bit 1 enables CNF write at breakpoint Int.

The type of verification performed is selected via bit 2 of REQ.Cnf_cls. When set to 0, transmitter acknowledgment is performed; when the bit is set to 1, full acknowledgment is performed. Transmitter acknowledgment simply counts the number of frames successfully transmitted. A complete check counts the number of correctly transmitted frames and the number of correctly verified frames. A correctly identified frame is a frame that satisfies the following matching criteria.

Match = ~ Void and END and FC＿Match and Our＿SA and EFS＿of and VDL and parity＿ok

here:

Void = Invalid frame (ignored by BSI).

ED = Frame has an end delimiter.

FC_Match = The selected bits of the transmitted and received frame FC are the same.

OurSA = MFLAG ｜ SAT and EM

EFS＿ok = FCS＿ok and EE＿ok and EC＿ok and EA＿ok

FCS＿ok = Req＿EFS.FCS ｜ (∼Req＿EFS.FCS and frames are valid

Have FCS.

VDL = frame has a valid data length.

parity ok = all bytes from FC to ED have good parity

(If mode. Flow)

The confirmed frame counter starts when a frame with Our＿SA is received after the first request burst frame is committed by the BMAC. It may be that all frames have been transmitted and the frame counts sent and acknowledged are the same, MACRESET, ring has been disabled from enabled, bad frames are received (see below), or mismatched frames are received. Is not satisfied (the above criteria are not met), or terminates when a token is received. Note that invalid and My＿Void frames are ignored.

When Rea? Cfg.SAT is selected and a full acknowledgment is required, the acknowledgment is started when an MFLAG | EM is detected, assuming the end of the frame. EM is SA_match input from the external address matching circuit.

A bad frame is a frame with a stripped frame or a format error, or a frame with a parity error (when a mode. Flow is set). The parity check on the information from the BMAC includes frames from the FC to the ED.

The MS bit of REQ.Cnf_cls enables refetching of the first frame of REQ. This must be cleared for normal operation. If refetching is enabled, the BSI continuously fetches and transmits the first frame until the request is abandoned.

Request status code

The rs [] field returned into CNF is a 4-bit status code. This is the priority value encoded state value. These values mean the following:

You are not in a state. The BSI 10 does not write this state. Yen

The encoding uses software to identify NULL or invalid CNFs.

It may also be used by a fish.

Preemption RSAP'1 was in service, but a higher priority request

Is activated on RSAP＿0. RSAP＿1 is serviced after R5A0

Will be replaced. Occurs only when a write intermediate CNF is commanded.

(REQ.Cnf＿cls [1] is set).

Part＿done BSI (10) services the request, but the BSI cannot keep the token.

(See the HLD option) and the final frame of the request part

When sent, the BSI 10 has the PartDone state and writes the CNF.

Will be used (if CNF generation is possible).

THT is terminated during the request with Serviceloss THT enabled. group

Generated only when an intermediate intermediate CNF is commanded (REQ.cmd [1] is set).

do). Breakpoints will occur.

When delivered from the Completed bbc beacon state, this state is defined by BMAC as My.

Return when receiving a Beacon. To be delivered in the claims state

This state is returned when the BMAC wins the claim process.

Completed＿ok Checks for frames that were sent normally normal. Bad＿conf.

There was an error. This makes the request

Status or one of the higher priorities (status below).

Let's do it. Types of verification errors include MACRST, Ring-Operation Change,

Receipt of Other＿Void / My＿Void / Token to receive bad frame,

Or frames that do not match the expected program frame state

It is to worship.

Requests when underrun request data is required to be provided to BMAC

There was no data in the data.

Host＿about The host has ABR? In the Service＿attn register. By clearing the beat

By having insufficient entries either directly or in the CNF queue.

As a result, the request was abandoned on this RSAP.

The Bad＿Ringop request is an Rq＿cls that was inappropriate for the current ring activation state.

Was loaded.

MAC＿abort BMAC abandoned the request and assumed TXABORT. this is

FC check from interface parity error or transmitted frame

When not received, or when sent from the beacon state

Can occur when a MAC frame is received. Exact cause

See the BMAC Functional Specification for a description. This state

While the BSI is transmitting in the Beacon State,

When the BMAC receives, or when the BSI transmits in the claim state

Is returned when the claim process is lost.

TRT was terminated during the request with timeout THT disabled.

The request is abandoned.

MAC_reset BMAC assumes MACRST.

Con＿fail consistency failure. There was a consistency failure in the REQ or ODUD stream.

All.

There was an internal logic error or fatal ABus error.

While filling in).

RSAP interaction

There is an interaction between RSAP, which is determined by prestaging and preemption configuration options.

Request machine 14C is in start state looking for REQ on both RSAPs. As soon as a valid REQ is loaded, the request machine issues a token capture request to the BMAC. Once prestaging is enabled, the machine will move to the staging state immediately. This brings the first ODU to the request burst FIFO. If prestaging is not enabled, request machine 14C waits for the appropriate token to be captured before staging the first frame into the burst FIFO. Once the token is captured, request machine 14C starts sending a frame on the RSAP.

In another scenario, request machine 14C may prestage the RSAP'1 frame and identify the RSAP'0 REQ before the token is captured. In this case request machine 14C ignores the staged data in the FIFO. When the RSAP'0 REQ is completed, the request machine 14C resumes the RSAP'1 request processing, and in the RSAP'1 request, RSAR'1 leaves the request machine 14C, i.e., no data is lost.

In another scenario, request machine 14C services an RSAP'1 REQ when RSAP'0 REQ is activated. If preemption is not possible, the request machine 14C continues uninterrupted. However, when preemption is enabled on RSAP'0, request machine 14C ends the transmission of the current frame on RSAP'1, releases the token and returns to the start state. This has the effect of reprioritizing RSAP, thus ensuring that RSAP_0 is the first to go on the next service opportunity. When RSAP'0 is serviced, RSAP'1 is picked up from the place where RSAP'1 left, and no data is lost.

Prestage only applies to requests without an immediate request / release level. Prestage is always available for RSAP'0 and is a programmable option on RSAP'1. Preemption is not applicable to RSAP'1 and is a programmable option on RSAP'0. The BSI always stages the next available frame on the current RSAP in the FIFO once the current frame is performed.

Errors and exceptions

The use of request event logic is complicated by the Req \ cfg option. The expressions and content below attempt to describe each function independently (but obviously there is interaction).

There are five outputs from the request machine 14c: State? Attn.ERR, Req? Attn.RCM, Req? Attn.BRK, Req? Attn.EXC, and CNF.

error

Stat_attn.ERR is set when the BSI has an ABus error while attempting to write a CNF. The error also generates a request-complete state, with the action described below. The RQRSTOP bit is also set and the request machine is stopped.

exception

The exception always raises Req? Attn.EXC and writes the confirmation status. The exception also causes the E bit to be set in CNF.cs []. The exception raises a request-complete state, and the action described below occurs.

complete

Completion occurs when the request object completes normally, an error occurs, or a completion exception occurs. Completion generates Req'attn.RCM. Completion also indicates a REQ object that is fully completed within the BSI.

Breakpoint

Breakpoints are generated whenever a CNF is written.

CNF

The CNF is multi-part and, for example, the CNF Middle can be written when the Service-loss CNF is written. Due to the pipelining, the BSI can write up to two CNFs after detecting the writing to the CNF entry just before the last one. For this reason, a host must always define CNF queue limits to be less descriptors than available space.

All of the above is summarized by the following equation.

ERR = internal＿error ｜ ABus＿error

EXC = exception

RCM = normal＿complete ｜ EXE ｜ ERR

BRK = CNF write

CNF = CNF＿enabled & normal＿complete ｜ EXC

Detailed state diagrams for request machine 14C are provided in FIG.

Indicator Service

There are three indicator ISAPs: ISAP'0, ISAP'1, and ISAP'2, all of which have equal priority. Unlike RSAP, each ISAP has a slightly different function. ISAP shares configuration registers for copy criteria, and also shares all registers that determine breakpoints for all ISAPs.

You program two shared ISAP mode / configuration registers to configure ISAP. Ind＿mode sets the common operating mode for ISAP. The Ind \ cfg register sets the copy criteria for each ISAP. Ind_threshold sets the maximum number of frames that can be received on ISAP # 1 or ISAP # 2 before an attention occurs. Ind＿attn and Ind＿notify define the operation of the indicator event logic. If the Header / Info Sort mode is selected, the Ind_hdrlen register is the length of the header.

Limit this to words (counting FC as one word).

The meaning of the ISAP operation is as follows.

Indicator {

7: Ind＿mode / * indicator configuration option * /

6: Ind＿cfg; / * ISAP copy control * /

8: Ind＿threshold; / * Endpoint Threshold * /

8: Ind＿hdrlen; / * Length of the header part * /

6: Ind＿attn; / * Attention * /

6: Ind＿notify; / * Attention to Notify * /

The BSI 10 generates an IDUD (with state) as follows.

IDUDI

4: is; / * Indication status * /

4: fra; / * Frame properties * /

8: frs; / * Frame state * /

1: vcopy; / * VCOPY is sent to BMAC * /

2: Rsvd; / * Set to reservation-0 * /

13: size; / * count of IDU bytes pointed to by loc * /

32: loc; / * Location of F-L flag and IDU * /

Ind＿mode

SM1 SM0 SKIP Rsvd BOT1 BOT2 BOB BOS

Ind＿cfg

CC7 CC6 Rsvd CC4 CC3 Rsvd CC1 CC0

Ind＿threshold

THR [7: 0]

Ind＿hdrlen

Length [7: 0]

Ind＿attn and Ind＿notify

Rsvd Rsvd EXC 0 BRK 0 EXC 1 BRK 1 EXC 2 BRK 2

IDUD

is fra frs VC Rsvd cnt loc

ia [3: 0] indicator state, [1: burst boundary 3: code]

Non-End Frame State

[0000]-page-the final IDUD of the queue with cross

[0001]-page cross

[0010] -header-end

[0011]-page with header-end-cross

Normal-End Frame State

[0100]-Medium (no breakpoint)

[0101]-burst boundary

[0110]-critical

[0111]-service opportunities

Give up copy because there is no space

[1000]-no data space (no header / info mode).

[1001]-no header space

[1010]-good header, info not copied

error

[1100]-IFF Overrun

[1101]-bad frame (not VDL or VFCS)

[1110]-parity error

[1111]-internal error

fra [3: 0] frame attribute = [MFLAG AFLAG TC] MFLAG = My address (0 = other station

Frame sent by, 1 = frame sent by this station). AFLAG-DA

Match (0 = internal, 1 = internal). TC = Ended state (11 = Frame stripped, 10

= Format error, 01 = ED, 00 = Other (ie Resct / Token). MFLAG and AFAG

Sampled by BSI in INFORCVD.

frs [7: 0] frame state = [VDL VFC5 E A C]. VDI = Valid Data Length, VFCS = Valid

FCS, E, A, C = control indicators (00 = non, 01 = R, 10 = S, 11 = T). This Phil

The lift is valid only when the frame ends with ED.

vc VCOPY. The state of the VCOPY bit sent to the BMAC for this frame.

Reflect. 0 = VCOPY is negated. 1 = VCOPY is assumed.

cnt [12: 0] Count of number of bytes in the ODU (within pagesize).

loc bits [31:30] = F-L tag. Bits [27: 0] = 28-bit ODU start memory

Adheres. For the first ODU of a frame, the address is burst-positive

Fourth FC byte (ie bits [1: 0] = 11) of the serialized frame. In subsequent ODUs

For an address, the address is the first byte of the ODU (ie bits [1: 0] = 00).

Indicator operation

Configuration

The indicator SAP is constructed by loading the registers Ind＿mode, Ind＿cfg, Ind＿threshold, and Ind＿hdrlen.

The steps required to initialize the input are as follows:

1. Set up the ISAP status queue space.

2. Set up the ISAP configuration / mode register via CBus.

3. Reset the INSTOP bit in Stat_attn.

4. Program the IDUD queue limit register.

ISAP Sorting and Copying

It can be seen that the indicator data processing is performed in two steps by the indicator machine 12C, that is, sorting and copying. First, the frame is sorted into one of three ISAPs. Second, it decides whether or not to copy the frame into memory.

Frames are sorted in ISAP according to the FC, AFLAG, and host-defined sorting modes of the frame. The sorting mode is determined by the bit [SMI.SMO] in the Ind_mode register. Table 7 below shows which ISAP the frames will be sorted on.

TABLE 7

Frame to ISAP Mapping

Sort mode SM [1: 0] Frame mode FC etc ISAP # Ind cfg (CC) xx0000010110101111 MAC ｜ SMTSyncAsyncInternalExternalHeaderInfoHi P AsyncLo P Async 012121212 [7: 6] [4: 3] [1: 0] [4: 3] [1: 0] [4: 3] [1: 0] [4: 3] [1: 0]

The BSI 10 identifies its own station addressed as follows.

Addr＿recoginzed = AFLAG ｜ (to ECIP and EA)

Table 8 below shows that each ISAP has a copy control bit. The indicator machine 12C uses the selected copy control bits and various flags to make copy decisions. The basic form programmed by the copy control bits is the same on all ISAPs.

Table 8

ISAP Copy Decision

Copy control Copy decision 00011011 Do not copy. Addr recognized and MFLAG. Addr recognizedM | If FLAG, copy.

Copy control bits are programmed in the Ind_cfg register.

15A Skip 0

ISAP_0 has one additional feature. According to one aspect of the invention, only new / other MAC frames are copied when the copy control is 01 or 10 and the SKIP bit of Ind_mode is assumed. This is accomplished via the MSKIP state bit. MSKIP is set when a frame is copied on ISAP # 0. As long as MSKIP is set, no more MAC frames will be copied. The MSKIP is cleared under the following three conditions, that is, when a MAC frame with an indication of not SAMEINFO is received, a frame with another FC is received, or a CBus write to the Ind_mode register is performed. The last of these can be used to sample a 'same' stream at other points in the MAC frame.

Sync / Async sorting mode

This mode is for end stations or for applications using synchronous transmission. MAC-SMT frames are sorted on ISAP # 0, synchronous frames are sorted on ISAP # 1, and asynchronous frames are sorted on ISAP # 2.

Internal / External Sorting Mode

This mode is for bridging or monitoring applications. MAC-SMT frames that match internal (BMAC) addresses are sorted on ISAP # 0. All other frames that match the BMAC's internal address (either short or long) are sorted on ISAP # 1. All frames (frames requiring bridging) that match the external address are sorted on ISAP # 2 (MAC-SMT frame diagram). Note that the inner match takes precedence over the outer match. This sorting mode uses the EM / EA ECIP pin. Its use is as follows.

1. The external address circuit must assume ECIP at some point from the FCRCVD assumption to the clock before the INFORCVD assumption, otherwise the BSI assumes that no external address comparison occurs.

2. ECIP must be negated before ECRCVD. Otherwise, the frame is not copied.

3. EA and EM are sampled on the clock after ECIP is negated.

4. After the IPIP is denied, it is ignored until FCRCVD is assumed again.

This design allows the ECIP to be a positive or negative pulse.

To identify the transmitted frame in this mode (typically using the SAT), EM is assumed to be in the same time frame as the EA.

Header / Info Sorting Mode

This mode is for high performance protocol processing. MAC-SMT frames are sorted on ISAP # 0. All other frames are sorted on ISAP'1 and ISAP'2. Frame bytes from the FC to the program header length are copied on ISAP # 2. Only one stream of IDUD is generated (on ISAP # 2), but both PSP queues of ISAP are used for space (ie, PSP from ISAP # 1 is for header space and PSP from ISAP # 2 is for info space). The frame may include only headers or may include headers and info. For a frame with info, a multi-part IDUD object is generated (IDUD. Only can be generated if the frame length is less than or equal to the header length). Only the ISAP # 1 copy control bits are used to determine if the frame will be copied. Please note. In this mode, two address spaces (ISAP # 1 and ISAP # 2 data) have IDUDs in one status stream (ISAP # 1). This will generate different space-reclamation software in different sorting modes.

Hi / Lo-Priority Async Sorting Mode

This mode is for end stations using two priority levels of asynchronous transmission. MAC-SMT frames are sorted on ISAP # 0, high priority Async frames are sorted on ISAP # 1, and low priority async frames are sorted on ISAP # 2. The priority is determined by the MS r-bits of the FC, where r = oxx = low-priority and r = 1xx = high-priority.

Channel blocking

The indicator machine 12c is copied onto the ISAP as long as there is data and state space. If a lack of any space is detected on a particular ISAP, the indicator machine 12C stops copying new frames from the ring for that ISAP. This is called channel blocking. There may still be data for the ISAP in indicator data FIFO 12A, but the data will not be able to be written to memory due to lack of space.

When the final PSP for ISAP is prefetched, an internal no dataspace flip-flop is set, and all additional frames on the ISAP are not copied (if what is currently being copied). Low＿data＿space attention is also generated. When the host updates the PSP queue limit, the flip flop is cleared and copying continues.

When the second IDUD is written from the end for the ISAP queue, further copying of the frame is stopped and the final IDUD is written to a special state. When the host updates the IDUD queue, limit copying continues.

Indicator status code

The is [] field returned in IDUD is a 4-bit status code. The value is priority encoded and has the highest priority value with the largest number. Some codes are mutually exclusive (so their relative priorities are not applicable).

When writing the state before the normal end of the frame, the first four values below are written. When the frame normally ends (no errors) the second four values are written. The third four values are written when frame copy is abandoned due to lack of data and / or state space. The last four values are written when there is an exception or error. The values have the following meanings.

[0000] The last IDUD of the queue, beyond the page. End use of the IDP queue in ISAP

Possible locations are listed. Page flips were also needed,

Meant there was more data to fill out. IDUD space more

There is nothing wrong with the rest of the data. This code is IDUD.

Will not be written in the middle, thus zero with a F-L tag

is [] can be used by software as a null descriptor.

[0001] Page Cross. Must be a first or intermediate IDUD. This is currently

Is the part of the frame that fills the rest of the page,

To the new page.

[0010] The end of the header. This refers to the final IDU of the header part of the frame. (minute

Obviously only applicable in header / Info sort mode).

[0011] Page turn and header end. If both of these conditions occur

to be.

[0100] Medium. The frame ended normally and there was no breakpoint.

[0101] Burst boundary. The frame ended normally and the burst boundary

There was a breakpoint because it was detected.

[0110] Threshold. Copies copied when this frame was copied and ended normally.

Reach the lame threshold counter.

[0111] Service Opportunities. This (usually end) frame comes after the token, otherwise

Otherwise a MACRST or MAC frame was received or there was a ring change.

None of these events indicate a burst boundary.

[1000] No data space. This code is not in the header / info sort mode.

Can be written when. Because there is not enough data space

Not all frames can be copied.

[1001] Insufficient header space. Because the header space is exhausted

In (in header / info sort mode), copying of frames is abandoned.

[1010] As a successful header copy, the frame info was not copied. Header

There was enough space to copy. When you want to copy info

Data space, IDUD space (on ISAP # 2) or both

Did not do it. info is not copied.

[1011] info no space. I copied the header, while copying info

The data and / or IDUD space is exhausted.

[1100] FIFO overrun. The indicator FIFO is displayed while copying this frame.

There was Burren.

[1101] Bad frame. This frame does not have a valid data length, or

Is the case with an invalid FCS, or both.

[1110] Parity error. There was a parity error during this frame.

[1111] Internal error. There was an internal logic error during this frame.

Indicator breakpoint

The indicator machine 12C generates an indicator state with every IDUD. Indicator machine 12C also identifies a burst of associated data. Burst boundary generates breakpoint attention. The host programs the Ind＿mode, Ind＿attn, and Ind＿notify registers to set an indication breakpoint common to all ISAPs.

Sometimes it is impossible to detect the end of a burst of data. The host will wait too long for the attention, so a copied frame counter is provided. Each time a frame is copied onto ISAP, this counter is decremented. Breakpoints can be generated whenever zero is reached. Each time the ISAP changes, the counter is reloaded from the Ind_threshold register. Loading Ind_threshold as zero causes a breakpoint after 256 consecutive frames are received on one ISAP. Breakpoint generation is enabled separately for ISAP # 1 and ISAP # 2 via the BOT bit in Ind \ cfg.

The following list describes each state breakpoint condition.

Breakpoint on the BOB burst. If /Ind\cfg.BOB is set, the end of the burst is Ind

Will generate aattn.BRK. End of Burst is ISAP Change or DA

Change or SA change. ISAP change from FC of valid copy frame

Is detected. DA of frame changes from current address to another

DA change is detected when it is changed. The SA of the frame is not the same as before

When not, the SA change is detected.

Breakpoint on the BOT threshold. The BSI 10 checks Ind

Load the frame counter copied from the threshold register. this

The counter is decremented for each valid copy frame on the current ISAP.

All. When the counter reaches zero and Ind＿cfg.BOT in ISAP is set, Ind

AttnBRK occurs. For BOT'1, BOT2's

It is for.

Breakpoints on BOS Service Opportunities. When Ind＿cfg.BOS is set, some copied

After-frame service opportunities (token / MAC frame / ring behavior change)

will generate attn.BRK.

MACInfo MACInfo breakpoints always raise Ind＿attn.BRK (this breakpoint

Is possible). The first four frames with the same MAC frame as the previous frame

MACInfo breakpoints are generated when they do not have info of bytes. Also

SAMEINFO detection is no more MAC frames with SAMEINFO assumed

Used to suppress copying.

Errors and exceptions

There are two attentions related to error / exception operations: State? Attn.ERR / and Ind? Attn.EXC.

An error on the indicator causes a State＿attn.ERR attention. The host must reset the INSTOP attention to resume processing on the ISAP.

If an exception occurs, the current frame is marked complete, the status is recorded in IDUD.L, and Ind_attn.EXC is generated.

Indicator SDU Format

Tables 9 and 10 below show the indicator SDU format. Note that the BSI 10 aligns each SDU on a 16 or 32-byte burst-size boundary. There are no sort restrictions on the request, i.e. each ODU may be several bytes (ODU 0 size). Can start at any byte address in memory.

Table 9

Large-endian indicator SDU (short address)

Byte 0 Byte 3

Bit 31 bit 0

FC FC FC FC DA0 DA1 SA0 SA1

Table 10

Small-endian indicator SDU

Byte 3 Byte 0

Bit 31 bit 0

FC FC FC FC SA1 SA0 DA1 DA0

Queue management

Management of queue entry / free space for all queues is manipulated by state / space machine 16 (FIG. 14). This section describes how the state / space machine 16 is configured and operated.

Configuration

The state queue and the PSP queue must be initialized before resetting the SPSTOP bit in State? Attn. Initialization includes setting up a PRT and limit RAM, setting up a PSP queue, and setting up a status queue.

The host and BSI 10 communicate via a memory base mailbox for RAM access. The mailbox address is normally loaded into Ptr \ mem \ adr once at power-up. Once this is done to set up the PRT RAM, the host does the following:

1. Check that the PTOP bit is set (if not set, wait).

2. Load the starting position of the PTR RAM into Ptr \ int \ adr (zero)

3. Clear the PTOP bit.

4. Repeat this step for all PTR positions to be loaded.

To set up limit RAM, the host does the following:

1. Check that the LMOP bit is set (if not set, wait).

2. Load the limit RAM location to be loaded into Limit # adr (also with MS data bits).

)

3. Load the limit value in Limit＿dat (LS8 bit)

4. Clear the LMOP bit.

5. Repeat this step for every position of the limit.

To initialize the BSI 10 for the PSP queue, the host must do the following.

1. Allocate memory in the PSP queue.

2. Write a valid PSP to the queue.

3. Load the queue's start address into the Ind? Psp? Ptr register.

4. Reset the SPSTOP bit in the State \ attn register.

5. Load the limit of the queue into the limit register.

To initialize the status queue, the host must do the following:

1. Allocate a state space.

2. Load the cue pointer into the Ind? Stsprt register.

3. Load the limit into the limit RAM.

To initialize the REQ queue, the host must do the following:

1. Allocate memory in the REQ queue.

2. Load the cue start address into Req? Req? Ptr.

3. Reset the RQSTOP bit in the State_attn register.

4. Write one or more REQs to the queue.

5. Load the REQ queue limit register.

work

PSP queue

Each ISAP has a DMA subchannel that activates its PSP queue. Each subchannel uses two registers to manage the queue.

1. Ind? Psp? Ptr refers to the next available PSP.

2. The Ind? Next? Psp register holds the next (prefetched) PSP.

State / space machine 16 prefetches the next PSP from the location referenced by Ind? have. When the indicator machine 12C requests space, the state / space machine 16 moves the descriptor from the hold register to the appropriate ISAP PSP pointer register, and then prefetches the PSP from the list and puts it into the hold register. This process is repeated until the PSP is prefetched from the limit of the queue. This causes a Low Data Space Attention on the ISAP and stops further copying when there is no more data space. The host puts more PSPs in the queue reset attention and updates the limit register of the queue. If copying has stopped, copying will resume on the ISAP when the PSP queue limit is updated. (Any write to this limit register is fine, and the host is assumed to move the limit forward.

The host forms a new PSP descriptor (from the reclaimed space) in the tail of the (unfilled) PSP queue. With a 4K byte queue and each descriptor that is 8 bytes, the queue addresses 2M bytes of full space memory per ISAP, including 512 descriptors. If the total associated space area is greater than this amount, the host can easily maintain a larger queue externally by reading Ind? Pap? Ptr as needed. The new PSP is written to the tail of the queue and the limit of the queue used.

Status queue

The BSI 10 writes a two-word descriptor or message to the status queue. Each word is written to an address in the incremented queue pointer register. When a descriptor or message is written, the written address is compared with the limit register of the queue (which is later incremented). If the two addresses are the same, the descriptor or message write is sent to the second queue entry at the end. The consequences of this action are very similar for both the indication and request status queues.

For both queues, this action generates a No＿Status＿Space attention.

For ISPA, the BSI 10 stops copying any more SDUs on the ISAP, and the ISDUs written to the IDUD. Finally, it may have a state indicating that there was no state space. If another IDUD was needed to complete the capture of this frame, is [] would be [0000]. If only this IDUD was needed to complete the SDU copy, is [] will contain some normal end status, so only the No＿Status＿Space attention will warn the host of lack of status space in the queue. No more SDUs will be copied to host memory until No＿Space? Attention is cleared, more status space is queued by the host and the limit register is updated. The BSI will continue copying SDUs to another ISAP (on a spaced ISAP).

For RSAP, the second write at the end will also set Req_atnn.USR. No further requests will be serviced while the USR Attention is set in RSAP. The service may continue by clearing the No＿Status＿Space and USR Attention.

Unlike PSP queues, updating the status queue limit does not resume the service, only clearing the attention will resume the service.

REQ queue

The BSI 10 fetches a two-word descriptor from each REQ queue. To control access, each RSAP maintains an internal Request 내부 Queue＿Empty (RQE) bit. REQ? As long as the bit is cleared, the REQ process continues. If the BSI 10 fetches a REQ from the limit position of the queue, it sets the REQ bit. Each time the host writes to the limit register of the queue, the bit is reset. The host writes each new limit in the limit register, and as long as there is a difference between the BSI's REQ pointer and the limit register, the BSI 10 will fetch and process the REQ.

Indicator throtting

A host can provide flow control on ISPA by limiting data or state space, although data space flow control is more accurate.

Each ISAP has its own PSP queue, so relative ISAP priorities are host-defined.

ABus interface

This section describes the BSI-Memory Bus (ABus) interface.

The ABus interface is operated by a bus interface unit (BIU) 18 (see FIG. 15). The ABus interface connects the BSI with 32-bit external memory.

The ABus interface interfaces to a multi-master bus, supports virtual or real addressing systems, transmits very high bandwidth, supports large-endian or less-endian systems, and synchronizes between ring and bus timing domains. Is designed to provide.

The bus-request / bus-grant mechanism supports multi-master buses. The BSI 10 tri-states all bus outputs when not tri-stateing the bus master. The mechanism also supports preoccupying the bus master.

A typical mode of operation of the BIU 18 is to emit the actual address. To assist the virtual memory system, the BSI 10 may insert the MMU translation state into the bus transaction.

Multiple masters

BIU 18 is a multi-master bus. The simple bus-request / bus-grant protocol uses an arbitration scheme (eg, rotational or fixed priority) to allow the external arbiter to support any number of bus masters. This also supports bus master preemption.

To transmit maximum bandwidth, BIU 18 ABus uses aligned burst mode transmission. This allows the use of DRAM or SRAM external memory. 16-byte or 32-byte bursts are supported.

Programmable options for large / small-endian support any system.

Simple protocols allow easy adaptation to other bus protocols.

summary

BIU 18 (see FIG. 15) is a 32-bit synchronous multiplex address / data multi-master bus with burst capability. All bus signals are synchronized to the master bus clock. The maximum burst rate is one 32-bit word per clock, but even slower rates can be accommodated by inserting a wait-state.

Multiple masters

BIU 18 is a multi-master bus. The simple bus-request / bus-grant protocol uses an arbitration scheme (eg, rotational or fixed priority) to allow the external arbiter to support any number of bus masters. This also supports bus master preemption.

There are two main application environments, where the BSI 10 is directly connected to host memory (see FIG. 8) and host-BSI shared memory (see FIG. 9). The exact configuration is transparent to the BSI 10 and in both cases the bus may be multi-master. Typically, the BSI is one of several bus masters when directly connected to the system bus of the host, and in a shared memory environment, the BSI 10 is the default bus master (for latency / bandwidth reasons).

The bus is effectively shared between the BSI internal DMA channel and the external master. Within the BSI, channels are serviced according to their priority.

Addressing mode

The ABus interface has a programmable bus mode that selects virtual or real addressing. In actual addressing, the BIU 18 releases the memory address and begins to transmit data immediately. In virtual addressing, the BIU 18 inserts two clocks between the release of the virtual address and the start of data transfer. This allows address translation by external mmu.

Bandwidth

In accordance with features of the present invention, BIU 18 supports single read and write and burst read and write. Back-to-back single reads and writes can occur with real addressing every four clock cycles. A burst transaction can send eight 32-bit words every 12 clock cycles. It offers a peak bandwidth of 96Mbytes / sec with a 36 / MHz clock.

To allow the bus to operate at higher frequencies, the protocol defines that all signals are asserted and deasserted by the slaves of the bus master. Actively releasing the signal by the bus device ensures that the inactive transition is fast. If this is not defined, the external pullup register will not be able to release the signal fast enough. The protocol also reduces contention by avoiding the case where two bus devices are driving one line at the same time.

The BSI 10 operates synchronously with the ABus clock. In general, the operation will be asynchronous to the ring because for most applications it will have an asynchronous system bus clock on the ring. The BSI 10 is designed to operate directly on the host main system bus or in local memory. When operating directly on the host bus, two parameters are of interest, latency and bandwidth.

As mentioned above, the BSI 10 uses two FIFOs in each of the transmit and receive paths. One FIFO is 64-byte deep and the other FIFO contains 32 bytes of two banks, each providing bursting capability. The amount of latency covered by the main data FIFO (plus one of the burst banks) must meet the average and maximum bus latency of the external memory. With a new byte every 80ns from the ring, a 64-byte FIFO provides 6 x 80 = 5.12us maximum latency. Of course, the bus must provide less average bus latency than the time it takes for the BSI to assemble a burst from the ring. For a 32-byte burst this is 2560 ns.

To support latency issues, the BSI 10 completely emptys or charges the FIFO within one bus tenure. To accomplish this, the BSI 10 keeps burst-requests assumed for multiple transactions unless the FIFO is charging / emptying. If the bus arbiter grants the BSI 10 for multiple transactions without releasing the bus for anything else, the maximum latency may be allowed. The BSI 10 can be preempted at any time by removing the bus-grant. When the bus-grant is denied, the bus completes the current transaction and releases the bus. There is a maximum of 11 clocks from preemption to bus release (plus memory wait).

Byte ordering

ABus performance optimization is a byte-addressable bus with some degree of optimization.

Descriptors are always aligned on 32-bit address boundaries. The input IDU is always aligned on a burst＿size boundary (the default burst＿size is determined by the mode register setting). The output OUD can be any number of bytes (or 0 bytes if this is not the last ODU of the frame). It can be aligned on any byte address boundary, but works best when aligned on a burst＿size boundary.

Bursts are always aligned on 32-bit words, 16 or 32 byte (burst size) address boundaries. The burst never crosses the burst size boundary. If a large burst is allowed, the BSI will perform the larger burst between 16-byte and 32-byte bursts (the minimum number of clocks to load / store all necessary data).

All descriptor fetches occur when two single words approach a 32-bit aligned boundary and from its boundaries.

The BSI 10 will not perform dynamic bus sizing. The memory accessed must be 32 bits. The bus interface can be operated in zone-endian or small-endian mode. Bit / byte alignment for both modes is shown in Tables 11 and 12, respectively. Byte 0 is the first byte received from or not sent to the ring.

Table 11

D [31] D [0] word Half 0 Half 1 Byte 0 Byte 1 Byte 2 Byte 3

Table 12

D [31] D [0] word Half 0 Half 1 Byte 0 Byte 1 Byte 2 Byte 3

Note that the descriptor is a word quantity, so only the data stream order changes in order to arrange the same in each mode.

Bus status

BIU 18 uses single and burst read and write cycles. When programmed in virtual address mode, the BSI is a 'DMA master' and supplies a virtual address, which is generated by the host CPU / MMU. The BSI 10 inserts two extra cycles after releasing the actual address to allow the MMU to translate the address and send the address on the bus. In the real address mode, the BSI only releases the real address and does not insert any extra cycles.

The BIU master state diagram is shown in FIG.

Master state

The Ti state is present when no bus activity is required. BIU 18 does not operate the bus signal when in this state (everything is released). However, if BIU 18 requires a bus service, BIU 18 may assume its bus-request.

When the transaction is executed, the BIU 18 goes to the Tbr state and assumes a bus-request and then waits for a bus-grant.

The state following Tbr is Tva or Tpa. In the virtual address mode, the BIU 18 becomes Tva and drives the virtual address and size lines on the bus. In the real address mode, Tpa is generated next.

The Tva state is followed by the Tmmu state. During this cycle, the external MMU performs the translation of the BIU virtual address released during Tva.

The Tpa state comes after the Tmmu state (virtual address) or the Tbr state (actual address). The bus master (virtual address host CPU / MMU, real address BSI) drives the real address and the BSI 10 drives the address, read / write strobe and size signals.

Following the Tpa state, the BIU 18 goes to the Td state and transmits the data word. Each data transmission can be infinitely extended by inserting a Tw state. The slave assumes an acknowledgment and acknowledges by transmitting data in Td e (cycle). If the slave can drive data at a rate of one word per clock, the slave will maintain its assumed acknowledgment.

After the last Td / Tw state, the BIU 18 goes to the Tr state to allow time to turn off and return the bus transceiver.

Bus retry requests are recognized in any Td / Tw state. BIU 18 goes to the Tr state and then returns the transaction when a new bus-grant is obtained. The entire transaction is retried, ie all words in the burst are retried. Also, another transaction will be attempted before the interrupted transaction is retried. BIU 18 retries indefinitely until the transaction completes successfully or a bus error is signaled.

Bus errors are recognized in the Td / Tw state.

Bus arbitration

BIU 18 uses a bus-request / bus-grant pair for arbitration. The external logic must provide the intermediary function. The protocol provides a number of transactions and bus master preemptions per retention period.

The BSI 18 assumes a bus-request and performs mastership if a bus-grant is assumed. If the BIU 18 is pending another transaction, the BIU 18 will maintain the state at which the bus-request was assumed and will re-think the bus-request before the current transaction is completed. If the bus-grant is (re) established before the end of the current transaction, the BIU maintains mastership and executes the next transaction. This process can be repeated indefinitely.

If the arbitrator wishes to preempt the BIU, this reverses the bus grant. The BIU will complete the current bus transaction and release the bus. From preemption to bus release is the maximum of the bus clock (11 + 8 × memory_wait_states). For example, in a one-state system, the BSI will release the bus within a maximum of 19 bus clocks.

Signal (fifth 15aaa degree to 15dddd degree)

Address and data

As mentioned above, ABus uses a 32-bit multiplex address / data bus. To support the user with burst transfer capability, three bits of the address that cycle during the burst are demultiplexed and output. The bus carries different information depending on the current state.

AB＿AD [31: 0] 32-bit multiplex address / data bus. 3-state input / output

Force. During Tva, AB＿AD [27: 0] is the address of the memory location to be accessed (28-bit).

Transmit virtual address, AB＿AD [31:28] is the cycle identifier / function

Send the code (4 bits). Host Mask in Virtual Address Mode

Will generate a translated address during Tpa,

Inless mode, the BSI obtains the actual address and function code during Tpa.

Will be. AB＿AD bus data during Td and Tw states

Send it. Sorting of data is big-endian or small-endian

All. The table below shows the function codes that encode for bus access.

Illustrated.

AB＿AD [3: 0] These are the byte parity lines for AB＿AD. AB＿BP [3] is

Byte parity for AB＿AD [32:24], AB＿BP [2] is AB＿AD

[23:16], and AB＿BP [1] is for AB＿AD [15: 8].

AB＿BP [0] is for AB＿AD [7: 0]. BSI output to ABus

Parity is generated on the address. Maximizing speed

Parity is preliminarily computed (calculated when the address is stored)

).

Table 13

Transaction function code

AD [31:28] Transaction type 0123456789ABCDEF RSAP＿1 ODU LoadRSAP＿1 ODUD Load / CNF Save RSAP＿1 REQ Load RSAP＿0 ODU Load RSAP＿0 ODUD Load / CNF Save RSAP＿0 REQ Load ISAP＿2 IDU Save ISAP＿2 IDUD Save ISAP＿2 PSP Load ISAP＿1 IDU Storage ISAP＿1 IDUD Storage ISAP＿0 PSP IDSPAP0 Load / Save PTR RAM

AB＿A [4: 2] Three bits of the demultiplex address that cycle during the burst.

Only 3-state output is present. These are the final Td states from Tpa

, Then negated in the next Tr state, then released

do. The address provided provides an external wave for optimal memory timing.

Note the allowing efraining (Tie for details

See the mining diagram).

Command

The AB＿AS＿ address strobe signal is a 3-signal output, assumed by the BSI from Tpa to the final Td state, where the signal is negated and released at the Tr state. It is intended to be used for two purposes. A cycle whose address is assumed is driven on AB_AD, so AB_AS is an address strobe. When AB＿AS is inactive and AB＿ACK＿ is active, the next cycle is the Tr state and the external arbitrator can sample all bus-reuqests and release the bus-grant in the next cycle.

AB＿RW＿ Read＿Write＿Singnal is a three-state output and the final Td switch from Tpa.

Tate is assumed, negated within the next Tr state, and

Is released. It is driven high for read and write to

Drive low.

The AB＿DEN＿ Data＿Enable signal is a 3-state output and goes to the first Td state.

To the final Td state, in the next Tr state

It is negated and then released.

AB＿SIZ [2: 0] size signal is a 3-state output and the final Td stay from Tpa

Is assumed, and negated within the next Tr state,

Is released. These represent the transfer size of the transaction. Enco

Please refer to the table below for more details.

Note that it is an indicator).

Table 14

Size encoding

AB＿SIZ2 AB＿SIZ1 AB＿SIZ0 Transmission size NNNNAAAA NNAANNAA NANANANA 4 bytes 1 byte 2 bytes Reserved 16 bytes 32 bytes Reserved

The AB＿ACK＿ transmit acknowledgment input indicates the slave's response to the bus master.

It is used to The slave has four select and insert wait states.

Retry for the transaction, terminate on error, or

Normally ends. The BSI performs only 32-bit transmission.

See Table 1 below.

AB＿ERR＿ bus error input causes a transaction retry or transaction abandonment

It is decided. State encoding is shown in the table below.

Table 15

Slave transaction response

AB＿ACK＿ AB＿ERR＿ Justice NNAA NAAA Insert Queue Bus Error Transaction Retry Acknowledgment

The BIU 18 arbitrates between internal DMA channels and issues bus requests when either channel requests service.

The AB＿BR＿ bus request output is set by the BIU to access the ABus.

All.

The AB＿BG＿ bus grant input is connected to the external logic to authorize the bus to the BSI.

Is assumed. If AB＿BG goes to the beginning of the transaction (Tbr)

If so, the BSI will execute the transaction. LE.UH 'Other'.VL150

AB＿CLK＿ All ABus operations are synchronized to the rising edge of AB＿CLK.

Actual Addressed Bus Transaction

This section provides details of all bus transactions in actual addressing mode (FIGS. 24-26). The next section will describe the virtual addressing in detail.

Single reading

Tbr. The BSI sets AB＿BR to indicate that it wants to perform the transmission.

do. Host assumes AB＿BR, BSI drives AB＿A, AB

When ＿BG is assumed, drive AB.AD. From this clock to Tpa

Do it.

Tpa. The BSI drives AB＿A and AB＿AD with an address, and adds AB 가 AS

And run AB＿RW and AB＿SIZ [2: 0], if other transactions

If this is not required, negate AB＿BR.

Td. BSI denies AB＿AS and assumes AB＿DEN＿, AB＿ACK＿ and AB

Sample the "ERR". Slave assumes AB＿ACK and AB＿ERR

Drive and, when ready, drive AB＿AD (with data).

The BSI samples the valid AB＿ACK＿ and captures the read data.

The Tw state may occur after Td.

Tr. The BSI denies AB＿RW, AB＿DEN＿ and AB＿SIZ [2: 0], and with AB＿AS

Release AB＿AS＿. Slave reverses AB＿ACK＿ and AB＿ERR＿

Assume, release AB＿AD.

Single entry

Tbr. BSI assumes AB＿BR＿ to indicate that it wants to transmit.

All. The host assumes AB＿BG＿, BSI drives AB＿A, AB

When AB is assumed, drive AB＿AD. From this clock to Tpa

Do it.

Tpa. The BSI drives AB＿A and AB＿AD with the address and adds AB＿AS.

And run AB＿RW＿ and AB＿SIZ [2: 0], if different transactions

If no option is required, negate AB＿BR＿.

Td. The BSI denies AB＿AD＿, assumes AB＿DEN＿, and

Drive AB＿AD together and start sampling AB＿ACK＿ and AB＿ERR＿.

All. Slave captures AB＿AD data, assuming AB＿ACK＿

Drive AB＿ERR＿. The BSI samples the valid AB＿ACK＿. Tw

The state may occur after Td.

Tr. BSI denies AB＿RW＿, AB＿DEN＿ and AB＿SIZ [2: 0], and AB 와 A and

Release AB＿AD and AB＿AS＿. Slave is AB＿ACK＿ and AB＿ERR

Invert and stop AB＿AD with data.

Burst reading

Tbr. The BSI adds AB＿BR＿ to indicate that it wants to perform the transmission.

Decide The host assumes AB＿BG＿, BSI drives AB＿A,

Drive AB＿AD when AB＿BG＿ is assumed. Tpa at next clock

Move.

Tpa. BSI drives AB＿A and AB＿AD with address, assuming AB＿AS

Drive AB＿RW＿ and AB＿SIZ [2: 0], and other transactions

If not found, negate AB＿BR＿.

Td. The BSI assumes AB＿DEN＿ and samples AB＿ACK＿ and AB＿ERR＿.

Increase the address on AB＿A. The slave sends AB 는 ACK＿.

Assume, drive AB＿ERR＿ and, when ready, AB＿AD (data

With). BSI samples and reads valid AB＿ACK＿

Captured data. The Tw state may be generated after Td. this

The state is repeated four or eight times (depending on the bust size).

On the final Td state, the BSI negates AB＿AS＿.

Tr. BSI denies AB＿RW＿, AB＿DEN＿ and AB＿SIZ [2: 0], and AB＿A

Release AB＿AS＿. Slave titers AB＿ACK＿ and AB＿ERR＿

And release AB＿AD.

Burst entry

Tbr. BSI assumes AB＿BR＿ to indicate that it wants to transmit.

All. The host assumes AB＿BE＿, BSI drives AB＿A, AB

When ＿BG＿ is assumed, drive AB＿AD. Tpa at next clock

Move.

Tpa. BSI drives AB＿A and AB＿AD with address, assuming AB＿AS

Drive AB＿RW＿ and AB＿RW＿ and AB＿SIZ [2: 0];

If no transaction is required, AB＿BR＿ is negated.

Td. The BSI assumes AB＿DEN＿ and drives AB＿AD with the write data.

, AB＿ACK＿ and AB＿ERR, and increment the address on AB＿A

Add. Slave captures AB＿AD data and adds AB＿ACK＿.

Drive the drive AB＿ERR＿. BSI samples valid AB＿ACK＿

do. The Tw state may occur after Td. This state

Repeat as required for transmitted bursts. Final Td State Award

BSI denies AB＿AS.

Tr. BSI denies AB＿RW, AB＿DEN＿ and AB＿SIZ [2: 0], and AB 와 A

Release AB＿AD and AB＿AS. Slave is AB＿ACK＿ and AB＿ERR＿

Inversely, stop the drive of AB＿AD with the data.

Virtual Addressed Bus Transaction

This section provides details of all bus transactions in virtual addressing mode.

Single reading

Tbr. The BSI uses AB＿BR＿ to indicate that it wants to perform the transmission.

Assume The host assumes AB＿BG＿ and BSI drives AB＿A

If AB＿BG＿ is assumed, AB＿AD is driven. At the next clock

Go to Tva.

Tva. The BSI drives AB＿A and AB＿AD with a virtual address for one clock,

Neglect AB＿AS＿, assume AB＿RD＿, and drive AB＿SIZ [2: 0]

If no other transaction is required, it negates AB＿BR ..

Tmmu. The host MMU performs address translation during this clock.

Tpa. The host MMU runs AB＿AD with a translated (real) address,

BSI drives AB＿A and assumes AB＿AS.

Td. BSI denies AB＿AS＿, assumes AB＿DEN＿, and AB＿ACK＿

Sample AB＿ERR＿. Slave assumes AB＿ACK＿, AB＿

＿ERR＿, and when ready, use AB＿AD (with data).

Drive. The BSI samples the valid AB＿ACK＿ and reads the read data.

Include. The Tw state may occur after Td.

Tr. BSI denies AB＿RW＿, AB＿DEN＿ and AB＿SIZ [2: 0], and AB＿A

Release AB＿AS＿. Slave titers AB＿ACK＿ and AB＿ERR＿

And release AB＿AD.

Single entry

Tbr. The BSI adds AB＿BR＿ to indicate that it wants to perform the transmission.

Decide The host assumes AB＿BG＿ and BSI drives AB＿A,

When AB＿BG is assumed, drive AB＿AD. From next clock to Tva

Move.

Tva. The BSI drives AB＿A and AB＿AD for a virtual address for one clock.

Negate AB＿AS＿, negate AB＿RW＿, and drive AB＿SIZ [2: 0]

do.

Tmmu. The host MMU performs address translation during this clock.

Tpa. The host MMU drives AB＿AD with the address, and BSI drives AB＿A.

Assuming AB＿AS, if no other transaction is required

Negative AB＿BR＿

Td. BSI denies AB＿AS＿ and assumes AB＿DEN＿

Drive AB＿AD together and start sampling AB＿ACK＿ and AB＿ERR＿.

do. Slave captures AB＿AD data and assumes AB＿ACK＿

Drive AB＿ERR＿. The BSI samples the valid AB＿ACK＿.

The Tw state may occur after Td.

Tr. BSI denies AB＿RW＿, AB＿DEN＿ and AB＿SIZ [2: 0], and AB＿A

Release AB＿AD and AB＿AS. Slave is AB＿ACK＿ and AB＿ERR＿

Inversely, stop the drive of AB＿AD with the data.

Burst reading

Tbr. The BSI uses AB＿BR＿ to indicate that it wants to perform the transmission.

Assume The host assumes AB＿BG＿ and BSI drives AB＿A.

If AB＿BG＿ is assumed, AB＿AD is driven. At the next clock

Go to Tva.

Tva. The BSI drives AB＿A and AB＿AD as virtual addresses for one clock.

And deny AB＿AS＿, assuming AB＿RD 를, and AB＿SIZ [2: 0]

If no other transaction is required, it negates AB # BR.

Tmmu. The host MMU performs address translation during this clock.

Tpa. The host MMU runs AB＿AD with a translated (real) address and the BSI

Drive AB＿A and assume AB＿AS＿.

Td. BSI assumes AB＿DEN＿ and samples AB＿ACK＿ and AB＿ERR＿.

All. Slave assumes AB＿ACK＿ and drives AB＿ERR＿

When it is raining, drive AB＿AD (with data). BSI is valid

Samples AB＿ACK＿ and captures the read data. Tw state is Td

It can happen later. This state is dependent on the burst size. Choi

In the final Td state, the BSI negates AB＿AS＿.

Burst entry

Tbr. The BSI uses AB＿BR＿ to indicate that it wants to perform the transmission.

Assume The host assumes AB＿BG＿ and BSI drives AB＿A.

If AB＿BG＿ is assumed, AB＿AD is driven. On the next clock

Go to Tva.

Tva. The BSI drives AB＿A and AB＿AD as virtual addresses for one clock.

Deny AB＿AS＿, deny AB＿RW＿, and deny AB＿SIZ [2: 0]

Drive.

Tmmu. The host MMU performs address translation during this clock.

Tpa. The host MMU drives AB＿AD with the address, and BSI drives AB＿A.

Run, assume AB＿AS＿, and no other transaction is required.

In this case, AB＿BR＿ is negated.

Td. The BSI assumes AB＿DEN＿ and returns AB＿AD＿ with the data entered.

Drives and starts sampling AB＿ACK＿ and AB＿ERR＿. Slay

Bb captures AB＿AD data, assuming AB＿ACK＿, and AB＿ERR

Drive ＿. The BSI samples the valid AB＿ACK＿. Tw Stay

Can occur after Td. This state is a complete burst

To be repeated as needed. On the final Td state, the BSI is AB＿

Deny AS.

Tr. BSI denies AB＿RW＿, AB＿DEN＿ and AB＿SIZ [2: 0], and AB＿A

Release AB＿AD and AB＿AS＿. Slave is AB＿ACK＿ and AB＿

Inversely assume ERR \ and drive AB_AD with the data.

BMAC interface

This section describes the interface between BMAC and BSI. As shown in Figs. 30A to 30C, the interface has two parts, a MAC indicator interface and a MAC request interface.

Request interface

data

MRD [7: 0] This is 8-bit output data from the BSI.

MRP This is parity on the MRD.

Requested Service

RQRCLS [3: 0] Select the type of request / release class

Require an RQBCN frame to be sent from the beacon state.

Require an RQCLM frame to be sent from the claim state.

option

STRIP Invalid Strip Option

Select SA from SAT data stream and not select MAC parameter RAM

(This is typically connected to both SAT and SAIGT on BMAC

do).

Disable FCST BMAC-generated FCS and instead stream data

Use

Transmission handshake

If RQRDY is captured, it indicates that the token of the required level will be used.

TXRDY Indicates that an available token has been captured.

Indicates that the RQSEND data is ready for transmission.

Strobe MRDSMRD transmission data. Connect to TXACK on BMAC.

Indicates that the last byte of RQEOF data is on the transport interface.

RQFINAL Represents the last frame of a request.

RQABORT is assumed by the BSI to abandon the current frame.

Indicates that TXED ED is being sent.

Indicates no TXPASS service opportunity.

TXABORT Indicates that the MAC transmit DID has given up this frame.

Transmission status

TXRINGOP Indicates the state of the local MAC transmitter ring operation flag.

TXCLASS This is the class of the current token.

Indiecase interface

data

MID [7: 0] This is 8-bit input data input to the BSI.

MIP This is parity on the MID.

Frame Sequencing and Handshake

Indicates that FCRCVD frame control was received.

INFORCVD Indicates that the first four bytes of the INFO field have been received.

Indicates the end of the EDRCVD frame sequence (EDFS) is being received.

MIDS MAC indicator data strobe, assumed for valid data.

Frame information

Indicates that an internal address match has occurred on the AFLAG DA field.

MFLAG Indicates that a received SA matches the MLA or MSA (BMAC) register.

All.

SAMESA The SA of the current frame is the same as the SA of the previous frame, and the frame is a MAC frame.

It was not a lame, indicating that the two sizes were identical.

SAMEINFO The first four bytes of the info field of the current frame are the beginning of the last frame.

Equal to 4 info bytes, these are MAC frames, their

Indicates that the lengths are the same.

Frame state

VDL indicates the valid data length for a received frame.

VFCS Indicates a valid FCS for a received frame.

TKRCVD Indicates that a complete token has been received.

Indicates that the FRSTRP frame has been stripped.

FOERROR Indicates a standard-defined format error.

MACRST internal error, MAC frame, MAC reset, software reset, or hardware

Indicates a reset.

Status indicator

Used to set the VCOPY COPY indicator.

EA outer A-flag, external DA match is assumed when detected. ECIP

Sampled when changing from hypothesis to negative. Sample window is JK-> ED

Comes from.

External comparisons within ECIP progress. Used to strobe the EA input

All.

EM external M＿Flat. It is assumed when an external SA match is detected. Of the frame

On the last byte (usually when EDRCVD is assumed) or ~ ECIP

Sampled by BSI on

Etc

Various phases of local byte clock from LBC [5, 3, 1] CDD

Scanpath Enable for SSER Ring Clock Scan Chain

Scanpath Enable for SSEB Bus Clock Scan Chain

Scan chain input for SIR [1: 0] clock scan chain

Scan Chain Input for SIB [1: 0] Bus Clock Scan Chain

CBus interface

The BSI 10 provides an 8-bit asynchronous interface to internal registers and logic. Internal registers are accessible. This interface is compatible with similar interfaces on other NSC FDDI chip set members and is called CBus.

Access to the Attention / Notification flag must be via CBus. Operation instructions are loaded into the BSI via the CBus. The protocol for CBus is described in this section. Instruction register usage and internal register maps are described in the Programming Interfaces section above.

CBus Signal

The CB [4: 0] control bus address input selects the BSI location to be accessed.

CBD [7: 0] Bidirectional control bus data signals are decoded from the BSI and 8-bit from the BSI.

Send data.

CBP This is the odd parity for the CBD bus.

CE＿ Chip Enable

The CB＿RW＿ read / write input selects the data transfer direction.

CB＿ACK＿ Acknowledgment Open-Drain Output

INT＿ Interrupts the open-drain output from the BSI.

RST＿ Hard reset input to BSI.

CBus protocol

The protocol is a simple asynchronous handshake. The host sets up addresses and data on the CBA and CBD (for writing), drives CB'RW ', and then assumes CE'. When the transmission is complete, the BSI assumes CB＿ACK＿. Once CB \ ACK \ is assumed, CE \ can be reversed, and once CB \ ACK \ is reversed, a new transaction can be initiated. CB＿ACK＿ is an open-drain output and therefore is not driven to a high output.

It should be understood that various modifications to the embodiments of the invention described herein may be used in the practice of the invention. The following claims are intended to limit the scope of the present invention, and to include within its scope the structures and methods and equivalents thereof.

The data communication system according to the present invention provides an interface between a medium access control (MAC) function of a local area network and a host system attached to a network medium via a MAC. The interface performs the transfer of information between the host memory system and the MAC for both frames received from the MAC receiver and frames provided by the host for transmission to the medium.

The MAC interface (in EFO) according to the present invention adds one final word as the frame state and places the state word behind the data into the receive FIFO. The system interface reads data and writes EOF state descriptors before processing the state. Data / state synchronization is automatic and no other communication between the MAC interface and the system interface is required. This allows any number of frames to be placed within the receive FIFO without complicated data / state synchronization. This allows full use of the FIFO when receiving many small frames, thus reducing the possibility of drop frames due to long-term bus delays. This allows for design flexibility in that the receiving FIFO can be at any depth.

Claims (3)

An interface system for the transfer of information between a local area network and a memory system associated with a station attached to the network, the interface system comprising: (A) bus interface means for implementing information transfer between said interface system and said memory system; (B) indicator means for transmitting information received by the interface system from the network to the memory system via the bus interface means; (C) requesting means for transmitting, by the bus interface means, information received by the interface system from the memory system to the network; (D) monitoring the state of the indicator means and the request means, generating a corresponding status signal, and for storing information transmitted between the network and the memory system via the interface system; A status generation / space management means connected to said indicator means and said request means for managing an assignment, And a plurality of receiving channels for transmitting the information received from the network to the memory system according to a predetermined criterion. The method of claim 1, Wherein each channel has a full space descriptor queue of the channel itself indicating where in the memory system the frame data will be stored, and an independent status queue. An interface system for the transfer of information between a local area network and a memory system associated with a station attached to the network, the interface system comprising: (A) bus interface means for implementing information transfer between said interface system and said memory system; (B) indicator means for transmitting information received by the interface system from the network to the memory system via the bus interface means; (C) requesting means for transmitting, by the bus interface means, information received by the interface system from the memory system to the network; (D) monitoring the status of the indicator means and the request means, generating a corresponding status signal, and for storing information transmitted between the network and the memory system via the interface system; A status generation / space management means connected to said indicator means and said request means for managing an assignment, Priority is given for the transmission of information to the network, a plurality of transmission channels for transmitting information received from the memory system to the network according to a predetermined criterion, and if a preemption of a preemptive transmission channel occurs, Switching the transport channel to service a high priority channel causes the interface system to, upon completion, be associated with the information transmitted on the preemptive transport channel to switch back to the preemptive transport channel and return processing based on the retained identifier information. And means for maintaining the identifier information.