KR100236529B1 - Edge etching mask and manufacturing method of semiconductor device using the same - Google Patents

Abstract

Edge etching mask of the present invention is characterized in that smaller than the multi-chip mask for forming a plurality of chip patterns at the same time, forming a conductor pattern on a semiconductor substrate and then planarizing after forming an insulating layer for insulating the conductor pattern Removing the conductor pattern of the edge of the semiconductor substrate exposed during the planarization by using the edge etching mask can increase the number of net dies implemented on the wafer, thereby reducing the manufacturing cost and improving the price competitiveness.

Description

Edge etching mask and manufacturing method of semiconductor device using same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to an edge mask for removing a conductor pattern acting as a contaminant during a subsequent process among conductor patterns formed on a wafer, and a method of manufacturing a semiconductor device using the same.

In the recent semiconductor manufacturing process, as a planarization method of an interlayer insulating film such as W-PLUG, Inter Layer Dielectric (ILD) or Inter Metal Dielectric (IMD) to enhance the backend process, chemical mechanical polishing with very excellent planarization characteristics (hereinafter referred to as CMP: Chemical Mechanical Polishing) process.

However, in the case of the CMP process, as shown in FIG. 1, since the planarization of the center and the edge of the wafer is different, an arbitrary conductive pattern 10 is formed on the wafer, and then an insulating film 20 is formed and the insulating film 20 is formed. When the planarization is performed by using the CMP process, the conductor pattern of the edge is revealed. At this time, the conductive pattern or abrasive particles, which are pushed out from the center of the wafer to the edge during the CMP process, are not completely cleaned when being cleaned. If left on, it acts as a source of contamination in subsequent processes.

To solve this problem, as shown in FIG. 2, any material (for example, photoresist) 35 applied to the wafer 30 for use in forming a conductor pattern is removed by using a rinse or a figure. An edge mask as shown in 3b was applied to remove the conductor pattern at the wafer edge.

However, the method using the former rinse causes a reduction in the number of available net dies in a multichip structure in which a plurality of chip patterns are arranged in one reticle, and the latter edge mask is applied. Even in this case, the size of the edge mask and the multichip mask 40 forming the plurality of chip patterns 50a, 50b, 50c, and 50d are the same as in FIG. Therefore, there is a problem in that the number of net dies is reduced as in the former.

Accordingly, an object of the present invention is to provide an edge etching mask capable of maximizing the number of net dies that can be obtained from one wafer in order to solve such problems of the prior art.

Another object of the present invention is to provide a method of manufacturing a semiconductor device to which the edge etching mask is applied.

In the edge etching mask of the present invention for achieving the above object, in the edge etching mask for removing the conductive pattern formed on the edge of the wafer, the edge etching mask is a multi-chip mask for forming a plurality of chip patterns at the same time It is characterized by being smaller.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming a conductor pattern on a semiconductor substrate; forming an insulating layer for insulating the conductor pattern; At the same time, by applying a smaller edge etching mask than a multi-chip mask for forming a plurality of chip patterns to remove the conductor pattern of the semiconductor substrate edge exposed during the planarization.

1 illustrates a state of a center and an edge of a wafer in a planarization process using a general CMP.

Figure 2 shows a rinsing method for removing the conductor pattern of the wafer edge as a conventional technique,

Figure 3 shows an edge mask for removing the conductor pattern of the wafer edge as a conventional technique,

4 illustrates a net die distribution implemented on a wafer when the method of FIGS. 2 and 3 is applied.

Fig. 5 shows a new edge mask for removing the conductor pattern of the wafer edge as the present invention,

FIG. 6 illustrates a net die distribution implemented on a wafer when the edge mask of FIG. 5 is applied.

* Explanation of symbols for main parts of the drawings

80: edge etching mask 130: wafer

170: Unusable Die

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

As shown in FIG. 5B, the edge etching mask of the present invention has the same size as each chip size for the multi-chip mask 40 forming the plurality of chip patterns 50a, 50b, 50c, and 50d as shown in FIG. Fabricate or use a portion of the multichip mask.

Alternatively, if the chip is made to have the same size as the conductor pattern mask to form the conductor pattern, and the chip is larger than the edge etching mask, the edge etching mask is repeatedly applied and etched so that a new etching mask does not need to be manufactured even if the size of the chip is different. .

Comparing FIG. 4 showing the case of applying the conventional edge etching mask with FIG. 6 showing the case of applying the edge etching mask according to the present invention, a portion indicated by a dotted line on the edge of the wafer 130 of FIG. 6 is not available. The die 170, which is marked black, indicates the die which has not been used in the prior art but can be used in the present invention, so that a net die which cannot be used in one conventional wafer can be used by 90% or more.

As described above, according to the present invention, the number of net dies implemented on the wafer may be increased, thereby reducing the manufacturing cost, thereby improving price competitiveness.

Claims (6)

An edge etching mask for removing a conductor pattern formed on an edge of a wafer, wherein the edge etching mask is smaller than a multichip mask for simultaneously forming a plurality of chip patterns. The edge etch mask of claim 1, wherein the edge etch mask is smaller than or equal to the chip size. The edge etching mask of claim 1, wherein the edge etching mask is a part of the multichip mask. The edge etching mask of claim 1, wherein the edge etching mask has the same size as a conductor pattern mask for forming the conductor pattern. Forming a conductive pattern on the semiconductor substrate, forming and insulating an insulating layer for insulating the conductor pattern, and simultaneously applying a smaller edge etching mask than a multi-chip mask for forming a plurality of chip patterns. A method of manufacturing a semiconductor device to which an edge etch mask is applied, comprising: removing a conductor pattern of an edge of a semiconductor substrate exposed during planarization. The method of claim 5, wherein when the conductor pattern is larger than the edge etch mask, the edge etch mask is repeatedly applied to the conductor pattern.

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