KR100235985B1 - Fabrication method of mos cell - Google Patents
Fabrication method of mos cell Download PDFInfo
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- KR100235985B1 KR100235985B1 KR1019920000478A KR920000478A KR100235985B1 KR 100235985 B1 KR100235985 B1 KR 100235985B1 KR 1019920000478 A KR1019920000478 A KR 1019920000478A KR 920000478 A KR920000478 A KR 920000478A KR 100235985 B1 KR100235985 B1 KR 100235985B1
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- Prior art keywords
- forming
- layer
- oxide film
- mos cell
- mos
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 title description 5
- 239000003990 capacitor Substances 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000002955 isolation Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 239000012212 insulator Substances 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910021489 α-quartz Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
본발명은 커패시터의 충전용량을 증대시키고 누설전류를 감소시켜서 소자의 특성을 향상시킨 반도체 메모리 셀의 제조방법에 관한 것으로, 종래의 SOI 구조를 갖는 메모리 셀은 트랜지스터로서의 사용은 가능하나 커패시터늘 형성하기가 어려워 대부분 칩의 주변회로나 SRAM용으로 많이 쓰이고 실제 DRAM에는 적당하지 않는 단점이 있었으나 절연체 하부에 평면으로 커패시터를 형성하고 측벽으로 트랜지스터간의 격리를 실시하여 이를 개선하였으며, 한편 커패시터를 한 개 혹은 복수개의 트렌치를 사용하여 형성함으로서 소자의 특성을 향상시킨 것이다.The present invention relates to a method of fabricating a semiconductor memory cell which improves the characteristics of the device by increasing the charge capacity of the capacitor and reducing the leakage current. The memory cell having a conventional SOI structure can be used as a transistor, but it is possible to form a capacitor. It is difficult to be used for peripheral circuits or SRAMs of chips because it is difficult, and it is not suitable for actual DRAM. However, capacitors are formed in a plane under the insulator and transistors are separated from sidewalls. Formation using two trenches improves the characteristics of the device.
Description
제1도는 종래 SOI형 MOS 셀의 구조단면도.1 is a structural cross-sectional view of a conventional SOI type MOS cell.
제2a∼제2d도는 본발명에 따른 MOS 셀의 제조공정도.2A to 2D are manufacturing process diagrams of MOS cells according to the present invention.
제3도는 본발명의 일실시예에 따른 MOS 셀의 구조단면도.3 is a structural cross-sectional view of a MOS cell according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 기판 11, 13, 22 : 폴리실리콘10: substrate 11, 13, 22: polysilicon
12 : 유전체 14, 16, 21 : 산화막12 dielectric 14, 16, 21 oxide film
15 : 에피택셜층 17 : 게이트15: epitaxial layer 17: gate
18, 19 : 소스/드레인영역 20 : 측벽18, 19: source / drain area 20: side wall
23 : BPSG 층 24 : 금속23: BPSG layer 24: metal
본발명은 반도체 메모리 셀의 제조방법에 관한 것을, 특히 충전용량 면적의 증대와 누설전류 감소에 적당하도록 한 SOI(Silicon On Insulator)구조의 MOS 셀 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor memory cell, and more particularly, to a method for manufacturing a MOS cell of a silicon on insulator (SOI) structure, which is suitable for increasing the charge capacity area and reducing the leakage current.
제1도는 종래 SOI형 MOS 셀의 구조단면도로써, 도시한 바와 같이 실리콘기판(1)상에 실리콘 에피택셜층(2)을 성장시키고 선택적으로 이온을 주입한 후 어닐링(anealing)함으로써 n+폴리실리콘 전극(3)과 P+폴리실리콘(4)의 소스/드레인을 형성한다. 그 다음에 식각하여 격리시킨 다음 게이트 산화막(5)을 성장시키고 소스/드레인의 접촉창을 형성하기 위한 식각을 한다. 그 후 얇은 폴리실리콘을 증착하고 이온을 주입하여 채널(6)과 소스/드레인영역(7)(8)을 형성한다. 이렇게 함으로써 벌크(bulk)가 얇은 폴리실리콘으로 형성되므로 누설전류를 줄일 수 있다. 여기서는 누설전류를 줄이기 위하여 박막 채널(thin film channel)을 사용하였다.Article as structural cross-sectional view of a conventional SOI-type MOS cell turns 1, the growth of the silicon epitaxial layer 2 on the silicon substrate 1 as shown and selectively implanting ions and then by annealing (anealing) n + polysilicon Source / drain of the electrode 3 and P + polysilicon 4 is formed. It is then etched and isolated and then the gate oxide film 5 is grown and etched to form the contact window of the source / drain. Thin polysilicon is then deposited and ions implanted to form channels 6 and source / drain regions 7 and 8. This reduces the leakage current since the bulk is formed of thin polysilicon. In this case, a thin film channel was used to reduce leakage current.
그러나 상기와 같이 종래 SOI 구조를 갖는 메로리 셀은 트랜지스터로서의 사용은 가능하나 메모리 용량을 형성하기가 곤란하고 커패시터를 형성하기가 어려워 대부분이 칩의 주변회로나 SRAM(Static RAM)용으로 많이 쓰이고 실제 DRAM(Dynamic RAM)의 메모리셀로는 적당하지 않는 단점이 있었다.However, as described above, the memory cell having the conventional SOI structure can be used as a transistor, but it is difficult to form a memory capacity and hard to form a capacitor, so most of them are used for peripheral circuits or static RAM (SRAM) of a chip, and are actually DRAM. There is a disadvantage that the memory cell of (Dynamic RAM) is not suitable.
본발명은 상기와 같은 단점을 보완하기 위하여 안출한 것으로, 충전용량의 면적을 증대시키고 누설전류를 감소시킨 MOS 셀의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made in order to compensate for the above disadvantages, an object of the present invention is to provide a method for manufacturing a MOS cell to increase the area of the charge capacity and reduce the leakage current.
상기의 목적을 달성하기 위하여 플레이너(planar) 커패시터를 갖거나 복수개의 트렌치(trench)를 갖는 본발명을 첨부한 도면에 따라 상세히 설명하면 다음과 같다.In order to achieve the above object, the present invention having a planar capacitor or a plurality of trenches will be described in detail with reference to the accompanying drawings.
제2도는 본발명에 따른 반도체 MOS 셀의 제조공정도로써, 제2a도에 도시한 바와 같이 기판(10)위에 커패시터를 형성하기 위하여 플레이트 폴리(plate poly)(11)와 유전체(dielectric)(12), 그리고 노드폴리(node poly)(13)를 차례로 형성한 다음 식각하여 인접셀과의 격리를 실시한다. 여기서 격리를 위한 필드산화막은 필요하지가 않다. 그후에 육각구조의 단결정 산화막(예를 들어 α-quartz SiO2)(14)을 형성하고 상기 산화막(14)위에 실리콘 에피택셜층(15)을 성장시킨다.FIG. 2 is a manufacturing process diagram of a semiconductor MOS cell according to the present invention. As shown in FIG. Then, node poly (13) is formed in sequence, and then etched to isolate from adjacent cells. No field oxide is required for isolation here. Thereafter, a hexagonal single crystal oxide film (for example, α-quartz SiO 2 ) 14 is formed and a silicon epitaxial layer 15 is grown on the oxide film 14.
제2b도에 도시한 바와 같이, 상기 실리콘 에피택셜층(15)과 상기 산화막(14)을 식각한 후 게이트 산화막(16)을 성장시키고 게이트 전극(17)을 만든 다음 이온을 주입하여 소스/드레인영역(18)(19)을 형성한다.As shown in FIG. 2B, after the silicon epitaxial layer 15 and the oxide layer 14 are etched, the gate oxide layer 16 is grown, the gate electrode 17 is formed, and ions are implanted to inject the source / drain. Areas 18 and 19 are formed.
제2c도에 도시한 바와 같이, LTO(Low Temperature Oxide ; 저온산화막)를 증착한 후 습식식각하여 측벽(20)을 형성하고, 캡산화막(cap oxide)(21)를 형성한다.As shown in FIG. 2C, the low temperature oxide film (LTO) is deposited and wet-etched to form the sidewall 20, and the cap oxide 21 is formed.
그리고 제2d도에 도시한 바와 같이 상기 소스/드레인 영역(18)(19)의 일부 캡산화막(21)과 상기 노드 폴리(13)상부의 캡산화막(21) 일부를 식각하여 노드 폴리(22)를 형성한다. 그 후에 BPSG(Boron Phosphorus Silicate Glass)(23)를 형성하고 금속 콘택(metal contact)을 뚫고서 금속(24)을 증착함으로써 본발명의 MOS 셀이 형성된다.As shown in FIG. 2D, a portion of the cap oxide layer 21 of the source / drain regions 18 and 19 and a portion of the cap oxide layer 21 on the node poly 13 are etched to form the node poly 22. To form. The MOS cell of the present invention is then formed by forming a Boron Phosphorus Silicate Glass (BPSG) 23 and depositing a metal 24 through a metal contact.
한편 제3도는 본발명의 일실시예에 따른 MOS 셀의 구조단면도로서, 도시한 바와 같이 커패시터영역을 만들 때 트렌치 기법을 적용하여 한 셀에 복수개의 트렌치를 갖는 반도체 메모리 셀을 제조할 수 있다.3 is a structural cross-sectional view of a MOS cell according to an exemplary embodiment of the present invention. As shown in FIG. 3, a trench technique may be used to fabricate a semiconductor memory cell having a plurality of trenches in a cell.
이상에서 설명한 바와 같이 본발명에 따르면 다음과 같은 효과가 기대된다.As described above, according to the present invention, the following effects are expected.
첫째로 매립 커패시터(buried capacitor)를 사용하고 셀의 격리를 위한 필드산화막을 사용하지 않기 때문에 거의 셀의 전체면적을 커패시터 에어리어(capacitor area)로 사용할 수 있으며, 둘째로 트랜지스터의 벌크가 SOI 구조와 동일하여 누설전류등 소자동작의 악영향을 배제할 수 있으므로 소자특성을 개선할 수 있고, 셋째로 종래의 플레이너 기술로도 충분히 MOS 셀을 제조할 수가 있다.Firstly, because the buried capacitor is used and no field oxide film is used to isolate the cell, almost the entire area of the cell can be used as the capacitor area. Second, the bulk of the transistor is the same as the SOI structure. As a result, the adverse effects of device operation such as leakage current can be eliminated, so that device characteristics can be improved. Third, MOS cells can be sufficiently manufactured by conventional planar technology.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920000478A KR100235985B1 (en) | 1992-01-15 | 1992-01-15 | Fabrication method of mos cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920000478A KR100235985B1 (en) | 1992-01-15 | 1992-01-15 | Fabrication method of mos cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930017192A KR930017192A (en) | 1993-08-30 |
| KR100235985B1 true KR100235985B1 (en) | 1999-12-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920000478A KR100235985B1 (en) | 1992-01-15 | 1992-01-15 | Fabrication method of mos cell |
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| KR (1) | KR100235985B1 (en) |
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- 1992-01-15 KR KR1019920000478A patent/KR100235985B1/en not_active IP Right Cessation
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| KR930017192A (en) | 1993-08-30 |
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