KR100233630B1 - High speed data register for laser range finders - Google Patents

Abstract

A high speed data register 11 for storing a series of received data values at a high clock rate RCCK and including a first set of pipelines 17, 19, 21 and a second set of pipelines 23, 25, 27. Is provided. The control circuit 29 is provided with the first latch set 17, 19, 21 and the second latch set from an input or “final” register 13 which stores the final data received by the data register 11. 23, 25, 27) alternately load the received data values. Thus, data values are input into register 11 at high speed clock RCCK, but are loaded into the respective first and second latch sets at half speed.

Description

High speed data register for laser range finder

1 is a circuit block diagram of a high speed data register according to a preferred embodiment.

2 is a circuit diagram of a register control circuit according to a preferred embodiment.

3 is a circuit diagram of a register enable circuit according to the preferred embodiment.

4 is a circuit diagram of a 2-1 multiplex register according to a preferred embodiment.

5 is a schematic block diagram illustrating double buffering according to a preferred embodiment.

6 is a timing diagram showing the operation of the preferred embodiment.

* Explanation of symbols for main parts of the drawings

11: high speed data register 13: final register

15,17,19,21,23,25,27: Latch 12,14,16: Bus

29 enable / control circuit

The present invention relates generally to high speed data storage, and more particularly to the execution of a series of data registers in a manner that allows for multiple laser range finder return storage at high counter speeds.

Current state-of-the-art range counters used in laser radars store only two target returns, i.e. typically only the first and last return. Storing more target returns in an ultrafast design results in the problem that the load of the system clock is reduced by adding more data registers in relation to the high speed range counter according to the conventional design, thereby preventing the desired high speed operation from being reached.

It is an object of the present invention to provide an improved laser range finder.

Another object of the present invention is to provide an improved high speed data storage circuit.

It is a further object of the present invention to provide an improved high speed data register circuit, which is used to store a target return in a laser range finder.

Another object of the present invention is to increase the speed and the storage amount of the target return storage circuit of the laser range finder.

It is a further object of the present invention to provide a circuit which can operate with a high speed laser range counter circuit and which is in accordance with integrated circuit performance.

It is yet another object of the present invention to provide a digital laser range finder storage circuit operable over a wide range of frequencies.

The present invention is to perform a series of data registers in a unique way to store multiple returns at a high counter rate. By carrying out the present invention, the GaAs range counter can obtain the final seven targets as well as the initial target that allows the system to identify smoke, dust, terrain and real targets.

The problem of storing multiple returns in a high speed synchronous design is solved in accordance with the present invention by using a ping pong structure using alternatingly loaded first and second pipelined latch sets. Each latch set needs to be operated at half the system clock speed, thus offloading the high speed system clock. This is done in the GaAs range counter design, which shows that the test can store the first return and the last seven target returns at frequencies above 1 GHz.

This approach is particularly important when used in imaging laser radar applications. The laser radar image signal processor requires a data rate of 100 kHz or more, and the target return latch needs to be double buffered. According to another feature of the invention, this double buffering is provided with a ping-pong structure that allows the system to initiate counting of the next range interval without the system loading the data from the range counter.

Computer simulations using worst-case rise and fall times, worst-case voltages and worst-case temperatures have demonstrated that data registers constructed in accordance with the present invention can operate at frequencies up to 600 nHz and are 1- at room temperature. Indicates that it can operate at frequencies up to 2 gHz.

Circuits designed in accordance with the present invention can be applied in commercial and industrial ranging systems, including vehicle obstacle avoidance, and radar and military applications. Data register design can be applied to a wide range of technologies and is not limited to laser systems.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The following description is provided to enable any person skilled in the art to make or use the present invention, and the following describes the best mode of carrying out the present invention made by the inventor. However, those skilled in the art will appreciate that various modifications are possible because the general principles of the invention are defined herein to clearly provide a high speed data register circuit that is particularly suitable for laser range finder applications.

[Data Register Structure]

A high speed data register 11 according to a preferred embodiment of the present invention is shown in FIG. Register 11 has three odd numbers, including LAST register 13, FIRST register 15 and LAST-1 register 17, LAST-3 latch 19 and LAST-5 latch 21. A latch set. Data register 11 also includes three sets of even latches, including LAST-2 latch 23, LAST-4 latch 25, and LAST-6 latch 27.

The LAST register 13 receives parallel digital inputs from the input bus 12 and stores one binary digital word at a time. In the described embodiment, this word is a 16-bit wide parallel output of the laser range finder range counter, but may be similar to any binary digital input with various selection widths.

A data distribution bus 14 is provided so that the contents of the LAST register 13 can be used in parallel with one of the FIRST latch 15, the LAST-1 latch 117 or the LAST-2 latch 23. Four parallel data transfer buses 16 are provided to transfer the contents of the previous latch, eg, LAST-1 latch 17, to the next consecutive latch, eg, LAST-3 latch 19, in parallel. In the described embodiment, the latches 15, 17, 19, 21, 23, 25, and 27 are 16 bits, 1 word, and enable the data content provided on the respective input and data transfer buses 14 and 16 of the latch. / Latch enable signals FREN, LIEN, L2EN,... Provided by control circuit 29. Is enabled to latch by L6EN. The enable / control circuit 29 also provides the LAST register latch enable signal LSEN and is initially enabled by itself by the initial register enable signal RGEN. The RGEN signal is provided by the associated circuit when the start of operation of the high speed data register 11 is required.

[Register Control Circuit]

A register enable / control circuit 29 of the preferred embodiment is shown in FIGS. 2 and 3. The register control circuit shown in FIG. 2 includes a common reset signal RCRS, a common pull-down signal PLDN, an initial register enable signal RGEN, a latch 1 enable control signal LIENST, and a latch 2 enable control signal L2ENST, as well as a line RCCK. (15) Receive an input control signal including a 600 mHz register clock on the RCCK 14. The RCCK 15 and RCCK 14 clock lines fan-out from the 600 nHz system clock and ideally transmit the same clock signal, ie the signal RCCK shown in the first line of FIG.

The register control circuit of FIG. 2 has 14 register stages RCRRG0, RCRRG1,... Which are D type flip-flops or "D-registers", respectively, except for the RCRRG4 and RCRRG3 stages. , RCRRG13. The register stage RCRRG3 is a conventional JK flip-flop and the RCRRG4 stage is a 2-1 multiplex register stage. As shown in FIG. 4, the 2-1 multiplex register or logic module RCRRG4 includes a multiplex stage 213 and a D flip-flop 215. The multiplex end 213 receives the selection signals S0 as well as inputs " I1 " and " I0 " and has an output 216 connected to the " D " input of the flip-flop 215. Flip-flop 215 also receives a clock input, such as a 600 mHz clock signal at read CP, and a reset signal at line RST, and outputs the current content at the Q output. The multiplex stage 213 functions to have I1 present on line 216 at the next clock pulse if S0 is logic “1” and I0 at line 216 at the next clock pulse if SO is logical zero.

Each register stage on the input side of the control circuit of FIG. 2, that is, RCRRG0, RCRRG1, RCRRG2, RCRRG3 and RCRRG4, receives an input from the 600 mHz register clock RCCK 14 to each clock input CP. Four D-type flip-flop register stages, i.e., RCRRG5, RCRRG6, RCRRG7, and RCRRG8, on the output side of the control circuit of FIG. 2 receive respective clock input CPs from the 600 mHz register clock RCCK 15. The remaining five register stages RCRRG9, RCRRG10, RCRRG11, RCRRG12 and RCRRG13 receive a clock input at each CP input from the clock supplied to line 31. The frequency of the clock of the line 31 is 1/2 of the frequency of the RCCK, as will be described later in detail. Although a RCCK clock frequency of 600 mHz has been discussed herein, the preferred embodiment is designed to operate at RCCK frequencies in the range of 0 to 600 mHz and corresponding half speeds of 0 to 300 mHz.

The common reset signal RCRS is supplied to the first and second buffers RCRBF0 and RCRBF1 which function to amplify the reset signal RCRS to supply a large number of register stages. The common reset signal RCRS is output through the respective buffers RCRBF0 and RCRBF1 to register all the registers RCRRG0,... Except for the registers RCRRG5 and RCRRG6. Is supplied to the reset input RST of RCRRG13. In the case of these two register stages RCRRG5 and RCRRG6, the common reset signal RCRS is supplied to the set input SET. The common pull-down signal PLDN is supplied to the reset input RST of these two flip-flop register stages RCRRG5 and RCRRG6. The pull-down signal PLDN, which is always a logic low or " 0 " value, causes all remaining register stages RCRRG0,... , RCRRG4 and RCRRG7,... Is supplied to the set input SET of RCRRG13. Various register stages RCRRG0,... RCRRG13 is used for generating various control signals as described below.

First, the register stages RCRRG0 and RCRRG1 are used to generate the control signal DLRGEN, which is a signal obtained by delaying the initial register enable signal RGEN by one period of the RCCK clock. For this reason, the initial register enable signal RGEN is supplied to the D0 or toggle input of the register RCRRG0 to which the Q output is applied to the D0 input of the next register stage RCRRG1. Each Q output of the register stages RCRRG0 and RCRRG1 is supplied as each input to an OR gate RCROR1 having an output constituting the DLRGEN signal.

The third register stage RCRRG2 is used to generate a clock RCDVCK which is allocated, i.e., a clock that is half the frequency of the clock RCCK. For this reason, the Q output of the register stage RCRRG2 is fed back to the D0 input through the inverter RCRIR0 to provide a buffer amplifier RCRBF3 and four inverter strings RCRIR1,... Is supplied to RCRIR5. Thus, the distributed clock RCDVCK includes the Q output of the third register stage RCRRG2 delayed by the thirteenth stages RCRBF3, RCRIR1, RCRIR2. The RCDVCK clock is also delayed by two additional inverter stages RCRIR4 and RCRIR5 to generate a distributed clock of 0-300 mHz in line 31.

The fifth register stage RCRRG4 is used to generate the control signal RTSL that is high when the odd number return is stored by the latches 15, 17, 19, 21, 23, 25, and 27, and low when the even number return is stored. do. For this reason, the register RCRRG4 has a Q input fed back to the IO input and to the I1 multiplexer input through the inverter RCRIR3, and an SO select signal connected to the initial register enable signal line RGEN. The output of the inverter RCRIR3 is also supplied to another inverter RCRIR6 having an output constituting the RTSL control signal.

JK flip-flop or fourth stage RCRRG3 is used to generate the control signal LSSL. For this reason, the J input of the register terminal RCRRG3 is supplied by the AND gate RCRAN0, and the K input is supplied by the output of the NOR gate RCRNR0. NOR gate RCRAN0 receives respective first and second inputs from Q output and initial register enable signal RGEN of third register stage RCRRG2. The AND gate RCRAN0 also receives the first and second inputs, respectively, from the output of the third register stage RCRRG2 and the initial register enable signal RGEN. The Q output of the fourth register stage RCRRG3 constitutes a control signal LSSL supplied to the D0 input of the D-register RCRRG9.

D-register columns RCRRG9, RCRRG10,... RCRRG13 functions to generate control signal DLLSSL, which is a delayed signal of control signal LSSL. For this reason, the D0 input of each register RCRRG10, RCRRG11, RCRRG12, RCRRG13 is connected to the Q output of the previous D-registers RCRRG9, RCRRG10, RCRRG11, RCRRG12. The output of the fourteenth register stage RCRRG13 constitutes the control signal DLLSSL provided to the selection input S0 of the first and second multiplexers MXO and MX1.

The sixth register end RCRRG5 is used to generate the latch enable signal L2EN for the LAST-2 latch 23. The register stage RCRRG5 receives the latch 2 enable signal L2ENST from the circuit of FIG. 3 as the D0 input and supplies a Q output as a first input of each of the first and second AND gates AN1 and AN3.

The seventh register stage RCRRG6 is used to generate the latch enable signal L1EN, and receives the latch 1 enable control signal L1ENST generated in the circuit of FIG. 3 at the D0 input. The seventh register stage RCRRG6 provides a Q output to the first inputs of the third and fourth AND gates AN2 and AN4, each second input comprising the latch 1 enable control signal L1ENST. The output of AND gate AN2 constitutes latch 1 enable signal L1EN that controls LAST-1 latch 17 in FIG.

The eighth register end RCRRG7 is used to generate the LAST register enable signal LSEN. For this reason, the eighth register stage RCRRG7 receives the Q output of the ninth register stage RCRRG8 as the D0 input, and the second input I1 is the I0 input of the first melt multiplexer MX0 supplied by the Q output of the ninth register stage RCRRG8. Supply the Q output to The output of multiplexer MX0 constitutes the LAST register enable signal LSEN.

The ninth register stage RCRRG8 receives the output of the OR gate RCROR0 to which the respective first and second inputs are supplied by AND gate AN4 and AND gate AN3 as D0 input. The Q output of the ninth register stage RCRRG8 is supplied as a second input I1 to the multiplexer MX1 whose first input includes the Q output of the eighth register stage RCRRG7. The second multiplexer MX1 generates a buffered latch register enable signal LSENBF which is supplied as one input to the register enable circuit of FIG.

Register Enable Circuit

Referring now to the register enable circuit of FIG. 3, the various registers of the four D-register stages ENRG0, ENRG1, and ENRG3 are assigned to the latch 3 enable signal L3EN, the latch 5 enable signal L5EN, and the latch 1 enable control signal L1ENST. Used to generate The D0 input of the register stage ENRG0 is connected to the output of the AND gate ENANO, where the first and second inputs respectively comprise the RTSL and DLRGEN signals. Each D-register stage ENRG0,... ENRG3 receives a set input from the RCRS signal after being buffered by the buffer ENBF2, and a reset input comprising the PLDN signal. These register stages ENRG0,... , ENRG3 receives the clock signal from the CP input from the signal generated by buffering and inverting the RCDVCK through each of the inverters ENIR0 and ENIR1 and a buffer ENBFO that adds a selected delay to minimize distortion between the output of inverter ENI41 and the output of inverter ENIR3. do.

As shown in FIG. 3, the first and second 2-1 multiplex register stages ENRG8 and ENRG9 are used to generate the enable signal FREN for the first latch 15 of FIG. Each of these register stages ENRG8, ENRG9 receives a signal from the RCCK clock at the CP input and is reset by the RCRS signal provided to the reset input RST. The inputs I0, I1, S0 of the multiplex register stage ENRG8 are connected to the PLDN signal, the LSENBF signal, and the RCCTEN signal, respectively. RCCTEN is a control signal that typically indicates that the associated range counter is counting. The second multiplex register stage ENRG9 has its own Q output, PLUP signal, and I0, I1 and S0 inputs, respectively, connected to the Q output of the previous multiplex register ENRG8, which is always logic high or "1". The Q output of the multiplex register stage ENRG9 is supplied to an inverting ENIR4 having an output constituting the first register enable signal FREN.

The various registers of the four second serial D-registers ENRG4, ENRG5, ENRG6, ENRG7 enable the latch 2 enable control signal L2ENST, and the even register enable for the LAST-4 register 25 and the LAST-6 register 27, respectively. Used to generate signals L4EN and L6EN. Each of these registers ENRG4,... , ENRG7 is set by the RCRS signal supplied through the buffer ENBF1, reset by the PLDN signal, and clocked by the delayed RCDVCK signal of the first and second inverter stages ENIR2 and ENIR3. The first enable register stage ENRG4 of this second group receives the output of the NOR gate ENNR0 including the DLRGEN and RTSL signals, respectively, as the D0 input. Each of the first three second sets of enable register stages ENRG4, ENRG5, ENRG6 supplies a Q output to each of the following register stages ENRG5, ENRG6, ENRG7. The Q output of each register stage, ENRG4, ENRG6, and ENRG7, contains the even-numbered latch register control signals L2ENST, L4EN, and L6EN. Each of the amplifiers ENLD1 and ENLD0 supplies a drive load to compensate for the excessive drive capacity of the particular device selected to perform the register stages ENRG3 and ENRG7 used in the described embodiments.

5 shows an optional double buffering of the contents of the fast data register 11 implemented in the preferred embodiment. This double buffering is enabled to be latched by a second stage latch enable signal comprising a plurality of latches 115, 113, 119, 123, 125, 121, and 127, so that the corresponding latches 15, 13, 17, 23, 19, 25, 21, and 27 Double the content.

[High Speed Data Register Operation]

As can be seen from the above, the high-speed data register 11 of the preferred embodiment is a 16-bit, 8-word double buffer type, and can operate at a maximum frequency of 600 mHz over temperature using a technology using military grade GaAs. have. The high-speed data registers include a 16-bit LAST register 13 for updating at maximum frequency, seven 16-bit latches (15, 17, 19, 21, 23, 25, 27) for updating at half frequency of the maximum frequency, and registers. And latch enable LSEN and L1EN. Control circuit 29 for generating L6EN. When used in a range counter application, the data register 11 stores the first, last seventh return value.

In order to ensure operation at 600 mHz, it is necessary to update the latches 15, 17, 19, 21, 23, 25, 27 at low speed (300 mHz) to reduce the load on the 600 mHz clock and increase the data-latch enable setup time. There is. The ping-pong structure is effectively used to maintain the 600mHz resolution while updating the latch at 300mHz. According to this structure, at the first enable, the "best" latches, LAST-6, LAST-4 and LAST-2, are updated in this order. In the next enable, the “base number” latches, LAST-5, LAST-3, and LAST-1, are again updated in this order. The “lower” latches are enabled first so that there is a storage place to receive additional data and no data is lost. Ping pong continues for all enable. The LAST register 13 supplies the odd and even latches and is updated after the odd or even latch is updated. The FIRST register 15 records the first value received by the LAST register 13, and records the value during the entire time that the odd and even latches 17, 19, 21, 23, 25, 27 are updated. Hold. The control circuit performs the latch loading / ordering structure and ensures that the enable latch is provided directly to the correction latch.

Referring to the control circuit of FIG. 2 and the timing diagram of FIG. 6, the operation of the high speed data register 11 of FIG. 1 will be described in more detail. 6 shows various control signals as well as when any data word (D0, D1, D2, D3, D4, etc.) is in each latch 15, 17, 19, 21, 23, 25 or register 13; Illustrated. It will be noted that the latch enable signal is generated before the control signal LSEN occurs, but there is no data to transmit in the LAST register.

To generate the latch enable clock RCDVCK (300 mHz, maximum), the system clock RCCK (300 mHz, maximum) is divided into two minutes using the D-register RCRRG2 (Figure 2) and the buffer RCRBF3. Thereafter, the register clock RCDVCK is transmitted through the other buffer stages RCRIR1 and RCRIR2 to ensure that a rising edge is generated after the signal synchronized with the system clock RCCK is stabilized.

In performing the range counter chip, a test is performed using simulated returns from two known locations to set the delay between RCDVCK and RCCK to the nearest RCCK period. For example, if the clock period is shorter than the delay of three inverters, the correction indicates that one more counter needs to be added to the calculated range. Such information is used to correct the range counter for the specified frequency. Since this feature is not limited to the RCCK delay by the RCDVCK, it allows the data register 11 to operate at a higher frequency without losing precision. This feature also does not require additional circuitry.

The delayed RGEN signal DLRGEN, one RCCK cycle after the initial register enable signal RGEN goes high, will go high for one cycle of the register clock RCDVCK. If the mantissa values have been stored, the RTSL control signal goes high, and going low means that the even values have been stored. The control signal LSSL goes high when the register clock RCDVCK is high and the initial register enable signal RGEN is high, and goes low when the RCDVCK is low and RGEN is high. The control signal LSSL indicates how much delay is added to the LAST register 13 to maintain system resolution.

The LSSL signal passes through a pipelined delay of five RCDVCK cycles provided by the register stage RCRRG9 so that the DLLSSL signal, which is a delayed LSSL signal, is generated at the same time as the last register enable LSEN and LSENBF. In this way, the control signal DLLSSL can select whether the last register enable signals LSEN and LSENBF are delayed by one cycle or two cycles of the system clock RCCK. Therefore, when the register clock RCDVCK is high and the initial register enable signal RGEN is generated, the final register enable signal LSEN is delayed by only one ECCK period. LSEN, on the other hand, has a delay of two cycles of RCCK. This adjustment is the number of RCCK cycles between the initial register enable signal RGEN and the fixed final register enable signal LSEN, regardless of whether the initial register enable signal RGEN occurs on the rising or falling edge of the register clock RCDVCK. Therefore, the system resolution is maintained.

[Latch loading sequence]

3 and 4, the loading of the odd number latch is generated when the control signal RTSL is low and the control signal DLRGEN is high. When RTSL is high and DLRGEN is high, latch 5 enable L5EN after one cycle of RCDVCK goes high for one cycle of register clock RCDVCK to transfer data from LAST-3 latch 19 to LAST-5 latch 21. . The two RCDVCK cycles after the latch 3 enable L3EN become strobe high for one cycle of RCDVCK to transfer data from the LAST-1 latch 17 to the LAST-3 latch 19. The latch 1 enable control signal L1ENST after one cycle of RCDVCK goes high for one cycle of RCDVCK so that the latch 1 enable signal L1EN goes high for one RCCK cycle after a delay of one cycle RCCK, and thus LAST-1 from the LAST register 13. Transfer data to the latch 17. Thereafter, the last register enable signal LSEN is pulsed high for one RCCK cycle after one cycle or two cycles of RCCK according to the state of DLLSSL to write a new range counter output value to the LAST register 13.

The scenario is consistent with the sequential loading of the latch registers under the control of the enable signals L6EN, L4EN and L2EN, except that the loading sequence is initiated by the control signal DLRGEN going high while the control signal RTSL is low. .

Finally, the first latch enable FREN is activated until the first RCCK 1 cycle occurs after the buffered last register enable signal LSENBF. Because of this timing, the FIRST latch 15 stores the first return value output by the range counter, and its enable FREN remains inactive until a reset occurs. Thus, the FIRST latch 15 always holds the first return value.

In the ranging field, one can see a second stage 110 of data latches (see FIG. 5). However, in the image field the second stage 110 is updated at the beginning of the next firing step.

In any field, when a data register is read, the first and last values will always be at the same address location. However, as a result of the ping-pong structure, the storage locations of the latches 1 and 2, the latches 3 and 4, and the latches 5 and 6 are as shown in Table 1 below. If RTSL = 1 (base number return occurs), it is swapped.

TABLE 1

Those skilled in the art will be able to construct various applications and modifications of the described preferred embodiments without departing from the scope and spirit of the invention. Therefore, the present invention may be practiced other than as described herein within the appended claims.

Claims (9)

In the data register 11 driven by the system clock RCCK to store a series of data values provided to the input bus 12 at the speed of the system clock RCCK, at the frequency of the system clock RCCK. A final register (13) connected to the input bus (12) for receiving a continuous final data value input to the high speed data register (11); First set of pipelined latches (17, 19, 21); Second pipeline latch sets 23, 25, and 27; And to each of the last registers 13 and the respective pipelined latches 17, 19, 21, 23, 25, 27 to provide respective latch loading control signals LSEN, L1EN, L2EN ... L6EN. And a control circuit 29 having a signal line of which the received data values are transferred from the last register 13 to the first latch set 17, 19, 21 and the final register 13; Digital circuitry (see FIGS. 2 and 3) for sequencing the generation of the control signals LSEN ... L6EN to be alternately loaded into the second set of latches 23, 25, 27 from. And the first latch set and the second latch set are each loaded at a half speed of the system clock (RCCK). 2. The set of claim 1, wherein said first pipelined latch set comprises at least three even latches 23, 25, 27 connected in series, and said second pipelined latch set in series. And at least three odd latches (17, 19, 21) connected. 2. The digital circuit of claim 1, wherein the digital circuit is configured to continuously update data values stored in each of the even-numbered latches in the first period, starting from the last even-numbered latch 27 in the series state to the always leading latch 23. Sequencing the control signal and sequencing the control signal to successively update the data value stored in each of the odd number latches from the last latch 21 in the series state to the first latch 17 in a second period. Characterized by a data register. The method according to claim 1, wherein the last register 13 is updated after any one of the series of even-numbered latches 23, 25, 27 or the series of odd-numbered latches 17, 19, 21 is updated. Characterized by a data register. Further comprising a first register (15) connected to the output of said last register (13), said digital circuit comprising said odd and even latches (17, 19, 21, 23, 25). A control signal for causing the first register (15) to store the first data value received by the last register (13) for the entire period of time during which the (27) is updated. The control signal RTSL of claim 1, wherein the digital circuit has a first state when odd data values are stored in the data register 11 and a second state when even data values are stored. Generating a data register. 2. The latch loading control signal of claim 1, wherein the latch loading control signal includes individual latch enable control signals for each of the cardinal surface latches and even-numbered latches 12, 19, 21, 23, 25, and 27. Data register. The digital circuit of claim 1, further comprising a delay circuit (RCRRG9-RCRRG13) for supplying a second control signal (LSSL) and outputting a third control signal (DLLSL). Control the amount of delay used to enable the last register (13). 2. A plurality of second latches (1) according to claim 1, corresponding to the latches (15, 17, 19, 21, 23, 25, 27) of the last register (13) and the first and second latch sets, respectively. And a buffer comprising 113,115,117,119,121,125,127.