KR100233538B1 - Run-level symbol decoder and the method - Google Patents

Abstract

The disclosed content relates to a method and apparatus for decoding [run, level] symbols according to the same scan pattern as used in the encoding process. The apparatus of the present invention receives a [run, level] symbol and separates the data into run and level data, respectively, and outputs them. A data storage unit for resetting the stored contents to “0” and storing the separated level data in the corresponding position to obtain run-level decoded data, and storing the addresses in the blocks for the plurality of scan patterns. Based on the scan pattern data inputted from the run data, the address stored in the position indicated by the current address pointer among the addresses of the same scan pattern as the scan pattern used for variable length encoding is used for storing the level data. It consists of an address output section for outputting. Therefore, the present invention takes one clock to decode the [run, level] symbol, thereby providing an effect of improving the operation speed of the overall system.

Description

Run-level symbol decoding method and apparatus

The present invention relates to a decoding system for decoding a variable length coded run-level symbol by using a selected scan pattern among various scan patterns. More particularly, the present invention provides a method for improving an operation speed of a system. The present invention relates to a level symbol decoding method and apparatus.

Recently, various methods of transmitting video and audio signals or encoding the digital data for storage in a storage medium, and decoding the encoded digital data for reproducing the video and audio signals, transmit video and audio signals. And in a system for receiving. However, in order to improve data transmission efficiency in such an encoding and decoding system, a technique for further reducing the amount of transmission data has been required. Examples of methods for encoding digital data to be transmitted or stored include transform coding, differential pulse code modulation (DPCM), vector quantization, and variable length coding. These coding methods compress the total amount of data by removing redundant data in the transmitted or stored digital data.

The image data of each frame is divided into blocks of a predetermined size and processed in an encoding and decoding system for storing, transmitting, and receiving image signals. Each block data or difference data between the block data is orthogonal-transformed, and the image data is converted into transform coefficients of a frequency domain. Known block data transformation methods include Discrete Cosine Transform (DCT), Walsh-Hadamard Transform (WHT), Discrete Fourier Transform (DFT) and Discrete Sine Transform. ; DST). The conversion coefficients obtained by these conversion methods are appropriately quantized and variable length coded according to the characteristics of the coefficient data, thereby increasing the compression efficiency. Since human visual perception is more sensitive to low frequencies than high frequencies, high frequency data is reduced by data processing. Thus, the encoded data amount can be reduced.

The apparatus for variable length coding compresses data based on frequency of occurrence of symbols, and has a variable length code table for variable length coding the input symbols. This variable long code table is designed according to the Huffman coding technique. Huffman coding, as is well known, assigns shorter codes to symbols with relatively high occurrence frequency and codes with longer codes to symbols with relatively low occurrence frequency. In the conventional coding system, the symbols input to the variable length encoding apparatus are [run, level] symbols that are usually obtained by run-length encoding. In the case of MPEG or the like related to image standardization, image data divided into blocks of 8x8 pixel size is converted into a frequency domain and then quantized. The quantized transform coefficients are represented in 8-by-8 size two-dimensional frequency domain, and are encoded into [run, level] symbols by a well-known zigzag scan that scans from a low frequency in a two-dimensional frequency space to a high frequency. . Here, run means the number of occurrences of "0" between coefficients that are not "0", and level means the absolute value of the coefficient which is not "0". For an 8x8 frequency domain, run means the absolute value of the coefficient other than "0". For an 8x8 frequency domain, a run can have values from "0" to "63". If the quantized transform coefficient is an integer value from "-255" to "255", the level is " It is a value from 1 ”to“ 255 ”and its sign is marked separately.

The use of the zigzag scan pattern results from the phenomenon that the energy of the image signal is concentrated in the low frequency region centered on the DC component. However, the energy of the video signal may be distributed more intensively or broadly toward the frequency component in the horizontal or vertical direction or toward the vertical frequency component according to the pattern of the video signal. Therefore, the existing zigzag scan pattern is not always an optimal scan pattern for variable length encoding of image data. Therefore, scan patterns that can be flexibly concentrated in the horizontal or vertical direction of the two-dimensional frequency domain according to the distribution characteristics of the image data are desired for variable length encoding and decoding. Prior art for this purpose is disclosed in "Variable Coded Encoding and Decoding System" of No. 92-13171 filed by the same applicant.

According to the above prior art, the digital data divided into blocks of a predetermined size is variable length coded according to various scan patterns, and the length of the variable length coded data is accumulated corresponding to each scan pattern, The scan pattern corresponding to the cumulative length is selected. Both the selected scan pattern and the variable length coded data corresponding to the selected scan pattern are transmitted. For decoding, the transmitted variable length coded data is variable length decoded while scanning according to the same scan pattern as the selected scan pattern during variable length encoding. . Therefore, an optimal scan pattern is used for variable length encoding and decoding of block data, thereby further improving data compression efficiency. The variable length decoding apparatus described in FIG. 6 of the previous application is shown in FIG. 1, and the variable length decoding apparatus will be described in more detail.

1 shows an embodiment of a conventional variable length decoding apparatus. Referring to FIG. 1, the variable length coded data D _VLC and the corresponding scan pattern data D _SCAN transmitted from an encoding device (not shown) may be converted into a variable length decoder 11 and a scan pattern selector 12. Enter each). The variable length decoding unit 11 converts the input variable length encoded data D _VLC into [run, level] symbols according to the variable length decoding table. The scan pattern selector 12 stores scan addresses corresponding to various scan patterns 1 to N corresponding to each of the scan patterns, and scan addresses ADDRs corresponding to the input scan pattern data D _SCAN . Select) to print. The run-level decoding unit 13 generates the [run, level] symbols input from the variable length decoding unit 11 according to the corresponding scan addresses ADDRs input from the scan pattern selection unit 12. Convert to quantization coefficients expressed in the spatial domain. The quantization coefficients are then supplied to an inverse quantization unit (not shown).

However, in such a conventional variable length decoding apparatus, it is necessary for the run-level decoding unit 13 to decode one [run, level] symbol as many times as the run length is added to "1". do. Therefore, the existing variable length decoding device can be used only in the system with low operation speed. Therefore, there is a problem that it is difficult to use in high-speed systems such as HD-TV system that need to decode more symbols per unit time.

Accordingly, an object of the present invention is to provide a method for decoding [run, level] symbols at high speed so as to solve the above problems.

Another object of the present invention is to provide an apparatus for implementing the aforementioned run-level symbol decoding method in hardware.

1 is a block diagram showing an embodiment of a conventional variable length decoding apparatus.

2 is a block diagram showing a run-level symbol decoding apparatus according to a preferred embodiment of the present invention.

3 is a detailed view showing the address output portion of the FIG.

4 is a timing diagram for explaining the operation of the device of FIG.

* Explanation of symbols for main parts of the drawings

21: symbol separation unit 22: address output unit

23: data storage unit 221: adder

222 address table

The run-level symbol decoding method of the present invention for achieving the above objects is a method of receiving and decoding [run, level] symbols and scan pattern data, (1) all the contents stored each time the initialization signal is applied; Is reset to “0”, (2) receiving [run, level] symbols, separating them into run and level data and outputting them respectively; and (3) the scan pattern data and the separated run data. And receiving (4) and outputting an address indicating the level data storage location, and (4) storing the separated level data.

The run-level symbol decoding apparatus of the present invention for achieving another object of the present invention is a variable length-decoded [run, level] in the apparatus for decoding block data according to the same scan pattern as used in the data encoding process. A symbol separator that receives the symbols and separates them into run and level data, respectively, and stores the addresses in the blocks for the plurality of scan patterns, changes the current address pointer from the separated run data, and uses the used scan pattern. An address output unit which receives the scan pattern data corresponding to the corresponding scan pattern and outputs the address stored in the current address pointer among the corresponding scan pattern addresses, and resets all the stored contents to “0” in response to the applied initialization signal. The address output from the address output unit indicates the separated level data. Stored in the location to run-level that includes the decoded data obtained parts data storage.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing a run-level symbol decoding apparatus according to the present invention. The symbol separator 21 shown in FIG. 2 receives a symbol composed of a pair of run and level, separates the received symbol, and outputs run data and run level data LEVEL. The symbol separation section 21 outputs the run data RUN and the level data LEVEL obtained from the received [run, level] symbols to the address output section 22 and the data storage section 23 at about the same time. The address output unit 22 receives scan pattern data (Scan_pattern) and an initialization signal (initialize) and generates a scan address ADDR. Referring to FIG. 3 showing its internal configuration, the address output section 22 includes an adder 221 for adding run data RUN, a predetermined value "1", and an address pointer P _ADDR fed back, and And an address table 222 for receiving an address pointer P _{ADDR which} is an addition result calculated by the adder 221 and outputting a scan address ADDR. The address table 222 includes tables P1 to PN in which each table stores scan addresses corresponding to one scan pattern, as many as the number N of scan patterns. The tables P1 to PN store the scan addresses in an order corresponding to the scan order determined by the corresponding scan pattern. The data storage unit 23 resets all stored contents to “0” according to the initialization signal, and from the symbol separation unit 21 according to the scan address ADDR generated by the address output unit 22. Store the received level data (LEVEL).

An initialization signal is applied from the controller (not shown) to the address output section 22 and the data storage section 23 before run-level decoding starts for every block. The address output unit 22 that receives the initialization signal initializes the current address pointer P _ADDR to point to the first scan address of the address table 222. The address output unit 22 also inputs scan pattern data Scan_pattern among the tables P1 to PN of the address table 222 when or before the first run data RUN belonging to a specific block is received. Select the one corresponding to). The data storage unit 23, which has received the same initialization signal supplied to the address output unit 22, resets all the stored contents to an initial value, that is, "0". Initialization of the data storage unit 23 resets all memory cells constituting the data storage unit 23 to “0” at a time or resets the memory cells in a row unit. The technique is common to those skilled in the memory art.

In a state in which both the address pointer P _ADDR and the data storage unit 23 are initialized, the symbol separation unit 21 executes [run, level] symbols applied from the variable length decoding unit (not shown). The data is separated by the level data LEVEL, and the separated run data and the level data LEVEL are output in synchronization with one pulse of the clock clock as shown in FIG. For example, for the case where the [run, level] symbol is [3, 5], the symbol separation unit 21 sets the run data to “3” and the level data LEVEL to “5”, respectively. Output during one pulse period of clock. The run data RUN is input to the address output section 22 and the level data LEVEL is input to the data storage section 23.

The adder 221 in the address output unit 22 that receives the run data RUN adds the received run data RUN, a predetermined value “1” and the fed back address pointer P _ADDR , and the addition result. The new address pointer P _ADDR is supplied to the address table 222. The address table 222 outputs the scan address ADDR stored at the position designated by the address pointer P _ADDR in the selected table to the data storage unit 23. For example, when run data RUN “3” is input in a situation in which the selected table P1 and the address pointer P _ADDR points to the position A1, the adder 221 returns the value “1” of the address pointer P _ADDR fed back. ”And RUN“ 3 ”are added to output a new address pointer (P _ADDR )“ 5 ”. The address table 222 which receives the address pointer P _ADDR stores the level data LEVEL input from the symbol separator 21 in a storage position corresponding to the scan address ADDR stored at position “A5”. . The data storage unit 23 has storage areas corresponding to 8 × 8 blocks, and the inverse quantization unit (not shown) uses data contained in all storage areas including the stored data as run-level decoded data. )

Therefore, the apparatus of FIG. 2 has the run data (RUN) and level data (LEVEL) corresponding to the [run, level] symbol and the address ADDR for storing the level data (LEVEL) as shown in FIG. ) Can occur during one clock pulse period, so that one [run, level] symbol can be decoded during one clock pulse period.

Here, it was explained that the data stored in the data storage unit 23 outputs to the inverse quantization unit at the rear stage. This is because run-level coded data in turn runs a symbol, as is well known to those skilled in the art of orthogonal transformation, quantization, variable length coding and run-level coded data in turn relating to orthogonal transformation, quantization, variable length coding and run-level coding. Run data and level data obtained by level decoding are generally stored in memory in blocks of 8x8 size for inverse orthogonal transformation. Therefore, when the quantization process is not used in the process of obtaining the run-level coded symbol, the data stored in the data storage section 23 may be directly supplied to the inverse orthogonal transform section.

As described above, the present invention relates to a method and apparatus for run-level symbol decoding, which resets all the stored contents to zero in the data storage unit before starting the run-level decoding of every block data and based on the separated run data. Since only the level data is stored in the data storage by determining the storage location of the level data, it is possible to decode the run-level symbols by one clock unit, thereby improving the overall operation speed of the system.

Claims (10)

A method of receiving and decoding a [run, level] symbol and scan pattern data, the method comprising: (1) resetting all stored contents to zero each time an initialization signal is applied; (2) receiving the [run, level] symbol and outputting the run and level data separately; (3) receiving the scan pattern data and the separated run data and outputting an address indicating the level data storage location; And (4) storing the separated level data in a storage location indicated by the address. The method of claim 1, wherein the step (3) comprises: (3a) selecting one of a plurality of scan patterns according to the scan pattern data; (3b) changing the address pointer by adding the run data, a predetermined value "1" and a current address pointer; And (3c) outputting an address stored at a position indicated by a current address pointer among the addresses in the block for the selected scan pattern. 3. The run-level symbol decoding method of claim 2, wherein the step (3) initializes a current address pointer each time the initialization signal is applied. 4. The run-level symbol decoding method of claim 3, wherein the initialization signal is applied before the start of run-level decoding of every block data. 5. The run-level symbol decoding method of claim 4, wherein one run is required for every run-level symbol decoding. An apparatus for decoding block data according to the same scan pattern as used in the data encoding process, the apparatus comprising: a symbol separation unit which receives variable length decoded [run, level] symbols and separates them into run and level data; Stores addresses in blocks for a plurality of scan patterns, changes a current address pointer from the separated run data, receives scan pattern data corresponding to the used scan pattern, and receives a current address among the corresponding scan pattern addresses. An address output unit for outputting an address stored in the pointer; And a data storage for resetting all stored contents to 0 in response to an applied initialization signal, and storing the separated level data at a location indicated by an address output from the address output unit to obtain run-level decoded data. Run-level symbol decoding device comprising a unit. The apparatus of claim 6, wherein the address output unit comprises: an address table comprising tables that store each of the scan addresses corresponding to the scan order of the plurality of scan patterns; And an adder configured to change an address pointer by adding the current address of the table corresponding to the scan pattern used by the scan pattern data in the address table and the separated run data and the value 1 to each other. Decryption device. 8. The run-level symbol decoding apparatus of claim 7, wherein the address output unit outputs an address stored at a position indicated by the changed address pointer in the used scan pattern table as an address for storing the level data. . 9. The run-level symbol decoding apparatus of claim 8, wherein the address output unit initializes a current address pointer each time the initialization signal is applied. The run-level symbol decoding apparatus of claim 9, wherein the initialization signal is applied before each decoding unit starts decoding.

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