KR100233282B1 - Sector non-protect detection/sensing circuit of a flash memory - Google Patents

Abstract

According to the present invention, a sector unprotected test / flash memory of a flash memory capable of generating a high erase erase margin by setting a logic threshold voltage at the time of data reading and a logic threshold voltage at an unprotected erase test in a minicell storing sector protected data differently. The present invention relates to a sensing circuit. To this end, the present invention is controlled by an external input signal and an external reference voltage signal, and provides a plurality of switching means for providing a current path for the data read and erase test to the minicell. In response to a control signal for the read and erase tests provided from the system, a first pass that forms a sense path for the erase test in the minicell when the sensed voltage reaches a predetermined first threshold level, a read provided from the system. And a first pass, in response to a control signal for an erase test, forming a sensing path for reading data in the minicell when the sensed voltage becomes a predetermined second threshold level at least lower than the previously established first threshold level, And logic means configured to provide erasing check state information to the system based on a sensing result signal output from the first pass or the second pass and a sector address signal from the outside.

Description

Sector Unprotected Scan / Detection Circuit in Flash Memory

The present invention relates to a sector protection circuit for use in flash memory, and more particularly to sector unprotected check / detection of flash memory suitable for setting a check margin for erasing when reading sector unprotected detection circuit or performing unprotected check. It is about a circuit.

As is well known, flash memory, particularly in flash EEPROM, which has recently been accelerated in its development, is a sector as a means to prevent in case of losing information by writing false data to the main memory cell or erasing the written data. The protection circuit is adopted.

Such a sector protection circuit is provided with a minicell. For example, when the minicell assumes that data is "1" or "0", each case is defined as a protected state or an unprotected state for the convenience of explanation and for the improvement of understanding. .

Therefore, a sensing circuit is required to read data from the minicells provided in the sector protection circuit, and the minicells must be erased to make the "0" state, and the inspection margin must be set in order to be sufficiently erased in this process. The present invention relates to an improvement in circuitry for setting an erase check margin.

An example of a typical prior art for setting an erase check margin in a sector protection circuit as described above is in the form as shown in FIG.

As shown in the figure, a sector unprotected test / detection circuit of a typical conventional flash memory includes three transistors (M1, M2, M3), two NAND gates (G2, G4) and two inverters (G3, G5). It includes.

Referring to FIG. 3, the P-type MOS transistor M1 has a gate connected to the input signal A, a drain connected to VCC, and a source of the drain and NAND gate G2 of the N-type MOS transistor M3. It is connected to one input. In addition, the P-type MOS transistor M2 has a gate connected to the input signal D, a drain connected to VCC, and a source in common with the source of the P-type MOS transistor M1 described above. Is connected to the drain of and the input of one side of the NAND gate G2. The gate of the N-type MOS transistor M3 is connected to the input signal C and the source is connected to the minicell E. Here, the input signal C is a reference voltage signal, and the input signal D is a signal for determining the data read or erase check, and becomes a pulse of the low level L during the erase test, and high level H during the data read. ) Pulses.

On the other hand, the output of the NAND gate G2, to which the input signal B is connected to the other input, is connected to the inverter G3, and the output of the inverter G3 is connected to one input of the NAND gate G4. In addition, the output of the NAND gate G4, to which the input signal F is connected to the other input, is connected to the input of the output inverter G5. Here, the input signal F is a sector address signal.

In the conventional sector unprotected test / detection circuit having the above-described configuration, in order to read the data of the minicell E, the input signal A is at the low level (L), the input signal (B) is at the high level (H), and the input. The reference voltage is supplied to the signal C, and the input signal D should be at the high level H. When the user gives the protected sector an address, the sector address signal F is at the high level H. ) And the output signal G via the NAND gate G4 and the inverter G5 which make this input signal F the other input becomes the high level H. As shown in FIG. On the contrary, when the user gives an unprotected sector to an address, the sector address signal F becomes the high level H while the output signal G becomes the low level L. FIG.

On the other hand, in the case of erasing data of the minicell E, after the erase pulse is performed, it is checked whether the minicell E is sufficiently erased through an erase test process, wherein the input signal D is at a low level. (L) turns on the P-type MOS transistor M2, and as a result, much current is supplied to the minicell E through the drain-source of the N-type MOS transistor M3, thereby erasing data of the minicell E. do. At this time, when the minicell E is not sufficiently erased, the NAND gate G2 recognizes the minicell E as a programmed cell, and as a result, the output signal G becomes the high level H. Therefore, the system will continue to output the erase pulse to the device (i.e., sector unprotected check / detect circuit) until the data of the minicell E is erased according to the high level output of the output signal G.

Therefore, in the conventional sector unprotected test / detection circuit, the above-described result causes the current of the P-type MOS transistor M2 to become too large, which may cause a test failure, and conversely, there is no test margin. There is a problem that adjustment of the current ratio is very difficult.

That is, in the conventional sector unprotected inspection / sensing circuit, the inspection margin is set by using the current load ratio, that is, the current of one P-type MOS transistor M1 is erased when the data stored in the minicell E is read and erased. In the audit, the currents of the two P-type MOS transistors M1 and M2 are used. In this way, setting the margin for the erase test using the current load ratio not only decreases the precision but also causes the test failure due to the excessive current. there is a problem.

Accordingly, the present invention is to solve the above-described problems of the prior art, and the high precision erase by setting the logic threshold voltage at the time of data reading and the logic threshold voltage at the unprotected erase audit in the minicell storing the sector protected data differently. It is an object of the present invention to provide a sector unprotected check / branch circuit in flash memory that can generate a check margin.

1 is a sector unprotected check / detect circuit diagram of a conventional flash memory.

2 is a sector unprotected check / detect circuit diagram of a flash memory according to a preferred embodiment of the present invention.

3 is a view for explaining the inspection margin secured during the erase test and reading of the minicell in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

M1: P-type MOS transistor M3: N-type MOS transistor

G1, G2, G4: NAND gate G3, G5, G6: Inverter

T1, T1: Transmission gate E: Minicell

In order to achieve the above object, the present invention provides a sector unprotected test / detection circuit of a flash memory that reads data and performs an erase test in a minicell storing the sector protected data, and is controlled by an external input signal and an external reference voltage signal. A plurality of switching means for providing a current path to the minicell for data read and erase tests. A first pass, in response to a control signal for read and erase tests provided from a system, forming a detection path for an erase test in said minicell when the sensed voltage reaches a predetermined first threshold level; In response to a control signal for read and erase tests provided from the system, a sensing path for reading data from the minicell when the sensed voltage becomes a preset second threshold level at least lower than the preset first threshold level; A first pass forming a; And a logic means for providing erasing check status information to the system based on a sensing result signal output from the first pass or the second pass and a sector address signal from the outside. Provides a sector unprotected check / detect circuit of the memory.

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a sector unprotected check / detect circuit diagram of a flash memory according to a preferred embodiment of the present invention.

The sector unprotected test / detection circuit of the present invention sets a detection margin for the test by using a difference between the logic threshold voltage at the time of inspection and the logic threshold voltage at the time of reading the data of the minicell and using the difference between these threshold voltages. Having technical features, it has a means for sensing a different logic threshold between the voltage level for detecting the erase check and the voltage level for reading the data, and always has a constant margin during the erase check and the data read. It can be realized by configuring to have. That is, as shown in FIG. 2, it is possible to implement a constant margin (VMW) at all times during the erase check and the data read, but by adjusting the logic threshold so that the check passes at an appropriate level. Referring to FIG. 1, the output buffer circuit according to the present invention eliminates the P-type MOS transistor M2 which causes a large current to flow in the minicell E during the erase test in the conventional circuit of FIG. It is different from the above-described prior art in that two paths are configured, i.e., a path for an erase test and a path for reading a data.

That is, the present invention constitutes a first pass including a NAND gate G1 and a transmission gate T1 for an erase test, and a second path including a NAND gate G2 and a transmission gate T2 for data reading. Construct a path. At this time, one input of each of the NAND gates G1 and G2 is connected in common between the source of the P-type MOS transistor M1 and the drain of the N-type MOS transistor M3, and the NAND gates of each of the NAND gates G1 and G2 are connected. The other input is simultaneously connected to the input signal B, and each output of the first and second paths is commonly connected to the inverter G3.

On the other hand, the two transmissions T1 and T2 are connected to an input signal D for determining an erase test or a data read through the inverter G6. In the erase test, the input signal D becomes a low level L. The first pass between the NAND gate G1 and the transmission gate T1 is formed, and when the data is read, the second pass between the NAND gate G2 and the transmission gate T2 when the input signal D becomes high level (H). Is formed.

In addition, as shown in FIG. 2, the logic threshold voltage (FIG. 2 (a)) of the NAND gate G1 in the first pass is equal to the logic threshold voltage (FIG. 2) of the NAND gate G2 in the second pass. b) is set lower than that, as the data erase is performed, the NAND gate g1 first recognizes the minicell E as an erased cell and performs the erase, that is, the erase test by a predetermined erase margin width VMW. To do that. At this time, the NAND gate G2 is in an unrecognized state.

Then, after the first pass is formed and erase is performed for the predetermined margin width VMW, the data read will be performed if the data read is recognized by the NAND gate G2. That is, in the circuit of the present invention, a certain logic threshold difference exists between the detected values of the NAND gate G1 and the NAND gate G2, and this logic threshold difference determines the margin of the erase test. Therefore, it is possible to secure a precise erase test margin on the basis of the logic threshold level difference at the time of erase check and data read.

As described above, according to the present invention, by separately providing a pass for the erase check and a pass for reading the data, and setting the logic thresholds in each pass separately, the margin at the erase check is obtained by using the current load ratio. Compared with the prior art to secure, it is possible to secure a high precision erase test margin can effectively prevent the erase test failure due to unstable erase test margin.

Claims (3)

A sector unprotected test / detection circuit of a flash memory that reads data from an minicell storing sector protected data and performs an erase test, wherein the minicell is controlled by an external input signal and an external reference voltage signal to read and erase data from the minicell. Multiple switching means providing a current path. A first pass, in response to a control signal for read and erase tests provided from a system, forming a detection path for an erase test in said minicell when the sensed voltage reaches a predetermined first threshold level; In response to a control signal for read and erase tests provided from the system, a sensing path for reading data from the minicell when the sensed voltage becomes a preset second threshold level at least lower than the preset first threshold level; A second pass forming a; And logic circuit means for providing erasing check status information to the system based on a sensing result signal output from the first pass or the second pass and a sector address signal from the outside. Sector unprotected check / detect circuit of flash memory. The first pass of claim 1, wherein the first pass is controlled by a first NAND gate having an external input and an output on the current path as inputs, and a control signal for the read and erase tests and an inverted signal thereof. And a first transmission gate for switching between a NAND gate and the logic means. The method of claim 1, wherein the second pass; A second NAND gate having each of the external input and the output on the current path in common with the first NAND gate; And a second transmission gate controlled by the control signal for the read and erase tests and the inverted signal thereof in common with the first transmission gate and switching between the second NAND gate and the logic means. Sector unprotected check / detect circuit.