KR100233250B1 - A design of linerization circuit stages for the output gain of the vga amplifiers - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The variable gain amplifier has a linear gain control stage structure.

2. The problem to be solved by the invention

In order to improve the disadvantage of the prior art, which deteriorates the noise figure and lowers the gain by using the feedback method, a structure in which a gain adjustment voltage is applied to the gate of the cascode FET through a predetermined resistance is adopted. The tuning characteristic aims to provide a variable gain amplifier that is adjusted linearly.

3. Summary of Solution to Invention

By adopting the cascaded two-stage FET structure, a wider gain adjustment range can be easily obtained, while a small resistor (R31) is inserted into the gate terminal, and the gain adjustment voltage is applied to the gate of the cascode FET through the resistor. By being applied, the gain adjustment characteristic is made more linear than the characteristic changed by the applied voltage so that the gain adjustment characteristic remains linear even when the supplied voltage is rapidly consumed.

4. Important uses of the invention

Used as intermediate stage of multi-stage driving amplifier for power control of mobile communication terminal.

Description

Variable Gain Amplifier with Linear Gain Control Stage

The present invention provides a mobile communication terminal for a future public land mobile telecommunication system (hereinafter referred to as "FPLMTS") or a third generation mobile communication system (International Mobile Telecommunication-2000 (hereinafter referred to as "IMT-2000"). The present invention relates to a multi-stage driving amplifier for power control, and more particularly, to a variable gain amplifier (hereinafter referred to as " VGA ") whose gain characteristic is linearly changed according to the adjustment voltage.

In general, fading occurs due to attenuation of radio waves according to distance, Doppler fading and propagation shade due to movement of a transceiver, and the terminal transmitter needs to control output power to a desired level in order to overcome this problem.

As a conventional case, a current-parallel feedback method is used as a technique for designing a VGA. The VGA configuration by the conventional current-parallel feedback scheme is illustrated in FIG.

As shown in the figure, in the conventional case, the feedback of the drain of the field effect transistor (hereinafter simply referred to as "FET") (FET12) to the negative terminal is applied to the gate terminal. In the circuit, the gain is adjusted by changing the feedback impedance between the drain and the source by adjusting the voltage Vcntl applied to the gate of the feedback transistor FET11. Frequency gain gain characteristics and gain adjustment characteristics of the VGA according to the prior art of Fig. 1 are shown in Figs. 2A and 2B, respectively.

However, this conventional technique has the advantage of widening bandwidth and stabilizing the amplifier, while impairing the noise figure and lowering the gain, thereby reducing power amplification by the generated noise figure and driving. There is a problem in that the amplification device rather than attenuating the input signal to amplify the output gain lower than the noise figure, and also quickly consumes the power of the battery (battery) provided to the terminal.

The present invention has been made to solve the above-mentioned problems, and provides a variable gain amplifier designed to be used as an intermediate stage such as a multi-stage driving amplifier by varying the gain linearly according to the adjustment voltage. The purpose is to.

1 is a configuration diagram of a variable gain amplifier (VGA) according to a conventional current-parallel feedback method;

FIG. 2A is a frequency band gain variation diagram of FIG. 1; FIG.

2B is a gain adjustment characteristic diagram of FIG. 1;

3 is a configuration diagram of an embodiment of a variable gain amplifier (VGA) having a linear gain adjusting stage structure according to the present invention;

4A is a diagram illustrating a characteristic change in frequency band gain of FIG. 1;

4B is a gain adjustment characteristic diagram of FIG. 1;

Fig. 5 is a block diagram illustrating the overall configuration of a multi-stage drive amplifier employing a variable gain amplifier (VGA) of the present invention for linear gain adjustment.

* Explanation of symbols for main parts of the drawings

FET11, FET12, FET31, FET32: Field Effect Transistor

C11, C12, C13, C31, C32: Capacitor

L11, L12, L31, L32: Inductors

R11, R12, R13, R31: Resistor

ST31: straight microstrip line

ST32: T-shaped microstrip line

51: input stage amplifier 52: intermediate stage amplifier

53: power divider 54, 55: termination amplifier

The present invention provides a voltage transmission means for providing a gain adjustment voltage to achieve the above object; A first transistor having a gate connected to the voltage transfer means to receive the gain adjustment voltage; A second transistor connected to the first transistor by a cascode; First DC voltage component blocking means connected to a signal input terminal and blocking a DC voltage component of an input signal applied from an outside to a gate of the second transistor; First short-circuit preventing means connected to a voltage terminal for providing a predetermined voltage to the gate of the second transistor and preventing a short circuit of a DC voltage component; First feeding means connected in series with said first short circuit prevention means for feeding a DC voltage to a gate of said second transistor; First connection means for coupling the gate of the second transistor, the first DC voltage component blocking means and the first feeding means; Second short circuit prevention means connected to a voltage terminal for providing a predetermined voltage to an output terminal of the first transistor and preventing a DC voltage component from being short-circuited; Second feeding means connected in series with the second short circuit preventing means to feed a DC voltage to the gate of the first transistor; Second DC voltage component blocking means connected to the first transistor output terminal and blocking DC voltage components of a signal output to the outside; Second connection means for coupling the output terminal of the first transistor, the second DC voltage component blocking means and the second feeding means; And it provides a variable gain amplifier including a plurality of third connection means respectively provided between the input and output terminals of the means.

Further, in the variable gain amplifier having the linear gain adjusting stage structure of the present invention, the first and second transistors are field effect transistors, respectively, and the bias voltage Vdd applied to the drain thereof is the first and second of the two-stage structure. It is divided into the field effect transistors FET31 and FET32, and the drain-source of the second field effect transistor FET32 increases as the gain adjusting voltage Vcntl applied to the first field effect transistor FET31 increases from 0V. The inter-voltage Vds is increased, the drain-source voltage Vds of the first field effect transistor FET31 is decreased, and the gate-source voltage Vgs of the first field effect transistor FET31 is It is characterized by being increased.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 3 to 5.

FIG. 3 is a configuration diagram of a variable gain amplifier (VGA) having a cascode field effect transistor (FET) structure according to the present invention, in which FET31 and FET32 are field effect transistors, C13, C31, and C32. Is a capacitor for DC voltage blocking, C33 and C34 are capacitors for short circuit protection of DC voltage, L31 and L32 are inductors for DC voltage feeding, R31 is a resistor, ST31 is a straight microstrip line, and ST32 is a tee The figure (T) microstrip lines are shown respectively.

As shown in the figure, the variable gain amplifier (VGA) according to the present invention is connected to two input field effect transistors (FET31 and FET32) connected to the cascode, and the field effect transistor (FET32) input terminal of the lower stage, respectively, to direct current. (DC) A capacitor (C31) and an inductor (L31), which serve as blocking and DC feeders, and a capacitor which acts as a DC blocking and DC feeder, respectively, connected to the output of the field effect transistor (FET31) at the upper end. C32), an inductor L32, a resistor R31 for applying a gain adjustment voltage to the gate of the upper field effect transistor FET31, and a resistor for providing a predetermined voltage to the gate of the lower field effect transistor FET32. A capacitor C33 connected in series between a voltage terminal Vgg and the inductor L31 to prevent short-circuit of the DC voltage component, and to provide a predetermined voltage to the drain of the upper field effect transistor FET31. A capacitor C34 connected in series between the voltage terminal Vdd and the inductor L32 to prevent short-circuit of the DC voltage component, the lower field effect transistor FET32 input terminal and the field effect transistor FET31 of the upper end; Two T-shaped microstrip lines (ST32) for coupling the capacitor (C31) and the inductor (L31), the capacitor (C32), and the inductor (L32) respectively connected to an output terminal, and input / output of the elements However, a plurality of straight microstrip lines ST31 are disposed between the T-shaped microstrip lines.

In addition, the capacitor C31 and the inductor L31 are respectively connected to the input field effect transistor FET32 at the lower end to serve as DC blocking and a DC feeder.

Similarly, the capacitor C32 and the inductor L32 are respectively connected to the output terminal of the field effect transistor FET31 at the upper end to serve as DC blocking and DC feeder.

The bias voltage Vdd applied to the drain is divided into two field effect transistors FET31 and FET32. When the gain adjustment voltage Vcntl applied to the upper field effect transistor FET31 increases from 0V, the lower field is applied. Vds of the effect transistor FET32 is increased, Vds of the upper field effect transistor FET31 is decreased, and Vgs of the upper field effect transistor FET31 is increased.

Therefore, when the gain adjustment voltage Vcntl is small, the upper field effect transistor FET31 is in a pinch-off state and a drain current does not flow, so that the gain is lowered. As Vcntl) increases, the Vgs of the upper field effect transistor FET31 also increases, so that the drain current increases, so that the gain increases.

In particular, in the variable gain amplifier (VGA), the straight and T-shaped microstrip lines ST31 and 32 are constructed using a GaAs compound semiconductor, and thus the electromagnetic field and characteristic impedance effective dielectric constant and transmission loss. In this embodiment, the widths of the left port, the right port, and the lower port of the T-shaped microstrip line ST32 are 30 μm, 30 μm, and 40 μm, respectively. The length of the plurality of straight microstrip lines ST31 is 50 µm in width and 40 µm in width.

Thus, the circuit of FIG. 3 may be fabricated as MMIC (Monolithic Microwave Intergrated Circuits) that grows and implements all passive and active devices on a single wafer.

The frequency band gain variation and gain adjustment characteristics of a variable gain amplifier (VGA) having a cascode field effect transistor structure according to the present invention of FIG. 3 are shown in FIGS. 4A and 4B, respectively.

As described above, the variable gain amplifier (VGA) according to the present invention has been conceived in view of the fact that the VGA used in the FPLMTS driving amplifier, etc. does not require a very wide band, and instead of using the feedback method in the prior art. In addition, by adopting two-stage field effect transistor structure connected by cascode, wider gain adjustment range can be easily obtained.

On the other hand, in the present invention, when the VGA is formed by the cascode, a small resistor R31 is inserted into the gate terminal so that the gain adjustment voltage is applied to the gate of the cascode field effect transistor through the resistance, whereby the gain adjustment characteristic is adjusted. To be linearized rather than varying characteristics.

FIG. 5 is a block diagram showing the overall configuration of a drive amplifier using the variable gain amplifier (VGA) of the present invention for linear gain adjustment as an embodiment of the present invention.

As shown in the figure, the driving amplifier may be composed of an input stage amplifier 51, an intermediate stage amplifier 52 for gain adjustment, a power divider 53 and termination amplifiers 54 and 55.

The input stage amplifier 51 has a function of pre-amplifying the output of the mixer of the transmitter converted to the carrier frequency of the uplink channel to obtain a sufficient output, and the magnitude of the input signal to enable the uplink power control. It has a function to adjust.

The intermediate stage amplifier 52 for gain adjustment is constructed using the VGA of the present invention of FIG. 2, so that a wider gain adjustment range can be easily obtained, and the gain adjustment characteristic is linearized. For example, in designing a multi-stage driving amplifier, when using a field effect transistor having a gate width of 300 μm, it is desirable to make the gain adjustment level of the middle stage more than 40 dB. As described above, the field effect transistor is connected to the cascode type, and an adjustment voltage is applied to the gate of the upper field effect transistor.

The power divider 53 can be implemented using a Wilkinson divider, which has a device value optimized to have a minimum transfer loss for a given regulated voltage.

The termination amplifiers 54 and 55 are configured in consideration of the size of the field effect transistor so that the maximum power level to be output can be amplified without distortion.

As described above, the variable gain amplifier of the present invention enables to vary linearly the gain of the multistage drive amplifier used in the terminal for FPLMTS according to the adjustment voltage, and thus is useful as an intermediate stage of such a multistage drive amplifier. Can be used.

The variable gain amplifier (VGA) of the present invention constructed and operated as described above connects two field effect transistors in a cascode and applies a regulated voltage to the gate of the upper field effect transistor through a resistor having an appropriate magnitude. In addition, the linear gain change range is very wide, and the structure is easier to manufacture with a small amount of lumped device and loss compared to the variable gain amplifier (VGA) using the conventional feedback method. It has a small and excellent effect of improving noise characteristics.

Claims (11)

Voltage transfer means for providing a gain adjustment voltage; A first transistor having a gate connected to the voltage transfer means to receive the gain adjustment voltage; A second transistor connected to the first transistor by a cascode; First DC voltage component blocking means connected to a signal input terminal and blocking a DC voltage component of an input signal applied from an outside to a gate of the second transistor; First short-circuit preventing means connected to a voltage terminal for providing a predetermined voltage to the gate of the second transistor and preventing a short circuit of a DC voltage component; First feeding means connected in series with said first short circuit prevention means for feeding a DC voltage to a gate of said second transistor; First connection means for coupling the gate of the second transistor, the first DC voltage component blocking means and the first feeding means; Second short circuit prevention means connected to a voltage terminal for providing a predetermined voltage to an output terminal of the first transistor and preventing a DC voltage component from being short-circuited; Second feeding means connected in series with the second short circuit preventing means to feed a DC voltage to the gate of the first transistor; Second DC voltage component blocking means connected to the first transistor output terminal and blocking DC voltage components of a signal output to the outside; Second connection means for coupling the output terminal of the first transistor, the second DC voltage component blocking means and the second feeding means; And A plurality of third connection means respectively provided between input and output terminals of the respective means; Variable gain amplifier having a linear gain control stage structure comprising a. The method of claim 1, And the voltage transfer means is a resistor connected to the gate of the first transistor. The method according to claim 1 or 2, The first and second transistors are each a field effect transistor, A variable gain amplifier having a linear gain control stage structure, characterized in that the bias voltage across the drain (Vdd) is configured to be divided between the first and second field effect transistors (FET31 and FET32) of the two-stage structure. The method of claim 3, wherein And said first and second DC voltage component blocking means have one capacitor, respectively. The method of claim 4, wherein And said first and second short-circuit preventing means each have a capacitor. A variable gain amplifier having a linear gain adjusting stage structure. The method of claim 5, And said first and second feeding means each having one inductor. The method of claim 6, The first and second connecting means are each a T-shaped microstrip line, And the third connecting means each has a straight microstrip line. The method of claim 3, wherein As the gain adjustment voltage Vcntl applied to the first field effect transistor FET31 increases from 0V, The drain-source voltage Vds of the second field effect transistor FET32 is increased, The drain-source voltage Vds of the first field effect transistor FET31 is decreased, And a gate-source voltage Vgs of the first field effect transistor FET31 is increased. The method of claim 7, wherein And the first to third connection means are formed of a GaAs compound semiconductor. The method of claim 9, The t-shaped (T) microstrip line constituting the first and second connecting means has a width ratio of the left port: the right port: the lower port is substantially 30: 30: 40, And a plurality of straight microstrip lines constituting the plurality of third connecting means, each having a length: width ratio of substantially 50:40. The method of claim 7, wherein And all passive and active elements and microstrip lines constituting the above means are fabricated from MMIC (Monolithic Microwave Intergrated Circuits) grown on a single wafer.

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