KR100233139B1 - Circuits testing network interfacing unit - Google Patents

Abstract

end. FIELD OF THE INVENTION The present invention relates to circuitry for independently testing a network interfacing unit.

I. The technical problem to be solved by the present invention is to provide a network interfacing unit test circuit capable of independently testing and maintenance in the ATM set-top box irrespective of the signal received from the remaining functional block circuit unit other than the network interfacing unit unit. .

All. Summary of the Invention Solution of the Invention: A network interfacing unit connected to a physical communication transmission medium such as a telephone line for modulating and transmitting ultra-high speed data, and a circuit unit for converting the data received from the network interfacing unit to be displayed on a display device. In the asynchronous transmission mode set-top box having a signal, the signal blocking / passing circuit for blocking or passing the signal transmitted from the circuit portion to the network interfacing unit according to the open or short state of the jumper, and the jumper of the signal blocking / passing circuit And a gate circuit unit for generating and outputting signals for independently initializing the network interfacing unit while all signals transmitted to the network interfacing unit are blocked by the operation.

la. Significant Uses of the Invention: Can be used for ATM set-top boxes or standalone network interfacing units.

Description

Network Interfacing Unit (NIU) Test Circuit

The present invention relates to an asynchronous transmission mode set-top box, and more particularly, to a circuit capable of independently testing the performance of a network interfacing unit (hereinafter referred to as NIU) for demodulating and demodulating ATM cell data.

In accordance with the trend of establishing a high-speed communication network and becoming a multimedia technology, ATM data processing, complex integration of independent devices, and integration into a single product are being accelerated. For example, an ATM set top box is an example. In general, an ATM set-top box is connected to an NIU of a high speed modem function that modulates and demodulates ATM cell data, and displays the data received from the NIU to a monitor such as a TV under the control of a microprocessor. For this purpose, the ATM set-top box has an ATM data separation-combining device, MPEG data decoder and NTSC encoder on the same PCB board. NIU, on the other hand, is a network interfacing function block that functions as a modem and is different from the circuitry of the rest of the function block of an ATM set-top box. Therefore, it is necessary to have the flexibility to independently research, develop, test, and maintain the current ATM set-top box because the signals between the NIU and the rest of the functional blocks in the ATM set-top box are correlated with each other. Without it, NIU alone is not easy to test.

Hereinafter, the interaction between the NIU 102 and the ATM set-top box 112 will be described with reference to FIG. 1 showing the configuration of the ATM set-top box and FIG. 2 showing the detailed configuration of the NIU 102.

First, referring to FIG. 1, a configuration of an ATM set-top box 112 is provided. An ATM set-top box 112 is connected to a physical communication transmission medium 100 such as a telephone line, and the NIU 102 modulates and transmits and transmits ultra-high speed data. The ATM data separation-combining unit 106 for processing the data received from the NIU 102 under the control of the microprocessor 104 to be displayed on a monitor such as a TV, an MPEG data decoder 108 and an NTSC encoder ( 110 is provided on the same PCB board 112. Hereinafter, the ATM data separation-combining unit 106, the MPEG data decoder 108, and the NTSC encoder 110 will be referred to as an ATM set-top box circuit unit 112.

2, the splitter filter circuit 200 separates a telephone signal and an ATM data signal, and the wideband transformer 204 converts a balanced mode ATM data signal into an unbalanced mode. Match the impedance. The diplexer filter circuit 206 separates the signal modulated by the CAP16 method and the signal modulated by the QPSK method among the ATM data signals that are output signals of the wideband transformer 204. The wideband transformer 208 converts an unbalanced mode into a balanced mode signal CAP16 and simultaneously matches impedance. The operational amplifier circuit 210 amplifies the output signal (compensation) of the CAP16 signal, and the CAP16 RX (receive) Low Pass Filter (LPF) 212 passes only the frequency band used by the CAP16 signal. The operational amplifier circuit 214 then amplifies the CAP16 signal and outputs it to the QPSK transmitter T7661 (a chip model name named by AT & T of the United States) 218. The wideband transformer 230 converts the QPSK balanced mode signal separated by the diplexer filter circuit 206 into an unbalanced mode signal and simultaneously matches impedance. The operational amplifier stage 228 amplifies and outputs the QPSK signal, and the QPSK TX (Band Pass Filter) BPF (226) passes only the frequency band used by the QPSK signal. The operational amplifier stage 224 amplifies and outputs the QPSK signal input from the QPSK TX BPF 226. The QPSK transmitters T7661 and 218 are one-chip ICs that modulate and transmit a QPSK signal to a transmission path in synchronization with an oscillation clock input from the oscillator 216. The CAP16 receiver (T7660) 220 is a one-chip IC that demodulates the CAP16 signal and transmits the demodulated CAP16 signal to the ATM set-top box circuit unit 112. The set-top transmitters T7662 and 222 are transmitted and received to and from the ATM set-top box circuit 112. It is a one-chip IC that interfaces signals.

Hereinafter, the operation of the NIU 102 and the ATM set-top box circuit unit 112 having the above-described configuration will be described. An analog signal in which the NIU 102 is modulated by the CAP16 method from a physical communication transmission medium 100 such as a telephone line is described. Receive and demodulate. The digital signal of the demodulated final output is transmitted to the ATM data separation-combining unit 106 under the control of the microprocessor 102 and output through the MPEG data decoder 108 which restores only the payload data. The output data is converted into an NTSC signal by the NTSC encoder 110 and output to the TV monitor, thereby completing the downstream reception process. In contrast, the reverse signal transmission proceeds in the reverse order as described above. However, the analog signal digitally modulated in the QPSK method in the NIU 102 is transmitted to a physical communication transmission medium such as a telephone line, thereby performing an upstream transmission process. Therefore, the CAP16 receiver 220 of the NIU 102, which is connected between the physical communication transmission medium and the ATM set-top box circuit section 112, receives an "valid data" signal from the ATM set-top box circuit section 112 (hereinafter referred to as VALDATA). And a logic " 1 " level for the " reset " signal, and a logic " 0 "

However, the NIU 102 is a network interfacing function block that functions as a modem and is different from the circuit portion of the data decoding of the ATM set-top box circuit portion 112. Therefore, it is necessary to have the flexibility to independently research, develop, test, and maintain. In the current ATM set-top box device, signals between the NIU 102 and the ATM set-top box circuitry 112 ("VALDATA", "reset" signals, etc.) Because of the involvement, the NIU 102 may become inoperable without the "VALDATA" and "Reset" signals transmitted from the ATM set-top box circuitry 112 to be in a normal state, so that single testing is not easy.

Accordingly, an object of the present invention is to provide an NIU test circuit capable of independently performing tests and maintenance regardless of whether signals are transmitted to the NIU in an ATM set-top box.

It is still another object of the present invention to provide an NIU test circuit that can be used to connect to a product other than the set-top box to separate the NIU into a single type, and the separated NIU can perform testing and maintenance by itself.

The present invention provides a network interfacing unit connected to a physical communication transmission medium such as a telephone line to modulate and demodulate and transmit ultra-high speed data, and convert the data received from the network interfacing unit to be displayed on a display device. In the asynchronous transmission mode set-top box having circuit parts,

A signal blocking / passing circuit for blocking or passing a signal transmitted from the circuit units to the network interfacing unit according to an open or shorted state of a jumper;

And a gate circuit unit generating and outputting signals for independently initializing the network interfacing unit in a state where all signals transmitted to the network interfacing unit are blocked by the jumper operation of the signal blocking / passing circuit. .

1 is a block diagram of an ATM set-top box connected to a network interfacing unit (NIU) 102. FIG.

FIG. 2 is a detailed block diagram of the network interfacing unit 102 of FIG. 1.

3 is a partial circuit diagram of a network interfacing unit 102 according to an embodiment of the present invention.

4 illustrates the use of standalone interfacing unit 102 in accordance with one embodiment of the present invention.

Hereinafter, an operation according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

)과 접속된 풀업저항들(R1∼R4)과, 각각 2개의 풀업저항의 타측을 2입력으로 하는 앤드게이트들(A1,A2)로 구성된다. 그리고 상기 앤드게이트들(A1,A2)의 1입력측은 일측이 접지된 점퍼 J1,J2와 접속되어지며, 앤드게이트들(A1,A2)의 출력측은 각각 CAP16 리시버(220)의 VD(VALDATA)단과 RS(RESET)단에 접속된다.3 is a circuit diagram of a portion of the NIU 102 according to an embodiment of the present invention. The test circuit according to an embodiment of the present invention is provided between the transmitter 222 and the CAP16 receiver 220 shown in FIG. The state in which 310 is connected is shown. 4 shows an example of the use of the standalone NIU 102 in accordance with one embodiment of the present invention. First, in FIG. 3, the NIU test circuit 310 connected between the transmitter 222 and the CAP16 receiver 220 includes a signal blocking / passing circuit 300 and a gate circuit. The signal blocking / passing circuit 300 blocks and passes various signals 301 received from the ATM set-top box circuit unit 112 by opening and shorting jumper 3 (JUMPER 3: J3 hereinafter). For example, if the signal blocking / passing circuit 300 uses a 74AC244 IC buffer, the IC pins on the A and B sides are internally disconnected and shorted by the opening and shorting of the jumper J3. That is, the signal blocking / passing circuit 300 can independently test only the NIU 102 independently of the presence or absence of signals flowing from the ATM set-top box circuit unit 112 and whether it is a noise chip and requires an integrated normal operation. At this time, the signals flowing into the ATM set-top box circuit 112 are passed through the CAP16 receiver 220 so that the ATM set-top box operation can be normally performed. And the gate circuit is the operating power input side (

) And pull-up resistors R1 to R4 connected to each other, and end gates A1 and A2 having two inputs of two pull-up resistors as two inputs, respectively. One input side of the AND gates A1 and A2 is connected to a jumper J1 and J2 having one side grounded, and an output side of the AND gates A1 and A2 is respectively connected to the VD (VALDATA) end of the CAP16 receiver 220. It is connected to RS (RESET) terminal.

Hereinafter, the operation of the NIU test circuit 310 illustrated in FIG. 3 will be described. First, the signals 301 flowing from the ATM set-top box circuit 112 to the NIU 102 are blocked / transmitted through the transmitter 222. It is transmitted to the passing circuit 300. In this case, the signal blocking / passing circuit 300 may block all signals 301 transmitted from the ATM set-top box circuit 112 by opening the jumper J3. Accordingly, the NIU test circuit 310 makes the mode capable of independently testing the NIU 102 independently of the presence or absence of a signal transmitted from the ATM set-top box circuit unit 112 and noise intrusion. This abnormally prevents the NIU 102 from becoming inoperable by sending "VALDATA" and "RESET" signals to the CAP16 receiver 220. On the other hand, when the NIU 102 is independently testing, the jumpers J1 and J2 of the AND gates A1 and A2 are shorted and opened so that the "VALDATA" and "RESET" signals can be normally activated. Generate a signal. When an integrated normal operation is required, normal ATM set-top box operation may be performed by shorting the jumper J3 of the signal blocking / passing circuit 300 to normally pass the signals 301.

4 shows a case in which the NIU 102 is an independent device, and the stand-alone NIU 102 also includes the NIU test circuit 310 as shown in FIG. have. In addition, the cable 600 between the stand-alone NIU 400 and the terminal device 500 is in the ATM set-top box, cable the signals to the stand-alone NIU 102 and the signal 301 received from the ATM set-top box circuitry 112 Interfacing to (or connectors) allows standalone NIU 400 to be tested independently.

As described above, in the present invention, when the network interfacing unit is embedded in an ATM set-top box or implemented as a stand-alone device, the present invention can be independently tested and maintained without depending on functional block circuits other than the network interfacing unit. There is an advantage to improve development efficiency.

Claims (4)

Asynchronous transmission mode set-top box having a network interfacing unit connected to a physical communication transmission medium such as a telephone line to modulate and demodulate and transmit ultra-high speed data, and circuit sections for converting the data received from the network interfacing unit to be displayed on a display device. In A signal blocking / passing circuit for blocking or passing a signal transmitted from the circuit units to the network interfacing unit according to an open or shorted state of a jumper; And a gate circuit unit generating and outputting signals for independently initializing the network interfacing unit in a state where all signals transmitted to the network interfacing unit are blocked by the jumper operation of the signal blocking / passing circuit. Network interfacing unit test circuit. The gate driving circuit of claim 1, wherein the gate circuit unit comprises: a gate circuit; Pull-up resistors, Logical multipliers having one side of the pull-up resistors as an input terminal, The network interfacing unit is connected between the pull-up resistor of one of the pull-up resistors respectively connected to the input terminal of the logical multiplication devices and the ground so that different logic level values are input to the logical multiplication device according to the open and short-circuit states. A network interfacing unit test circuit comprising jumpers for generating a signal to initialize. A network interfacing unit connected to a physical communication transmission medium such as a telephone line for modulating and transmitting ultra-high speed data, A signal blocking / passing circuit for blocking or passing the signal transmitted from the terminal device through the cable according to the open or short state of the jumper; And a gate circuit unit generating and outputting signals for independently initializing the network interfacing unit in a state where all signals transmitted to the network interfacing unit are blocked by the jumper operation of the signal blocking / passing circuit. Standalone network interfacing unit test circuit. 4. The single network interfacing unit test circuit of claim 3, wherein the cable is replaced with a connector.

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