KR100232970B1 - High frequency signal module of double band digital mobile telephone - Google Patents

Abstract

The present invention relates to a high-frequency signal module of a digital portable terminal and includes a lower-band interface unit for CDMA mobile communication, a higher-band interface unit for a PCS service, and a common interface unit commonly used for CDMA mobile communication and PCS service Frequency signal module for converting a clock signal used for a PCS service into a main clock signal and using the clock signal used for a conventional CDMA mobile communication terminal as a main clock signal, Thus, it is possible to accommodate both CDMA mobile communication and PCS service in one portable terminal.

Description

Dual band digital mobile terminal high frequency signal module

FIG. 1 is a block diagram showing a schematic configuration of the present invention. FIG.

FIG. 2 is a block diagram showing a detailed configuration of a higher-band interface unit in FIG. 1; FIG.

FIG. 3 is a block diagram showing a detailed configuration of a lower-band interface unit in FIG. 1; FIG.

FIG. 4 is a block diagram showing the detailed configuration of the common interface unit in FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

1: Interface block 10: Upper band interface part

20: altitude band interface unit 30: common interface unit

11, 21, 31: Transmitter 12, 22, 32: PLL oscillator

32-1: Transmit PLL unit 32-2: Receive PLL unit

13, 23, 33: Receiving section 34: Baseband analog section

34-1: transmitting end 34-2: receiving end

34-3: oscillation part 2: control block

P1, P2, P3, P4: PLL L1, L2, L3, L4: Loop filter

FA1, FA2, FA3, FA4, FA5, FA6, FB1, FB2:

FC1, FC2: low-pass filters A1, A2, A3, A4, A5: amplifiers

D1, D2: Driver D3, D4, TC1, TC2: Divider

M1, M2, M3, M4, M5, M6, M7, M8: mixer U1, U2:

T1, T2, T3: Tanks B1, B2, B3: Buffers

TR1, TR2, TR3, TR4: Trap PS1, PS2: Power distributor

IS1, IS2: Isolator DP1, DP2: Transmitter / Receiver

SW, SW1: Switches VGA1, VGA2: Voltage gain regulator

DA1, DA2: digital / analog converter

AD1, AD2, AD3: Analog / digital converter

VC1, VC2, VC3, VC4: voltage-controlled oscillator C: combiner

PC: Power controller AG: Automatic gain controller

DE: Alarm detection unit M: Adder

MU: Multiplier AT: Attenuator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency signal module of a digital portable terminal, and more particularly to a high-frequency signal module of a digital mobile terminal for use in a code division multiple access (CDMA) Frequency signal module in which a CDMA mobile communication service and a PCS service can be both performed in one terminal.

A high frequency signal module of a digital portable terminal currently in use is for a low frequency band CDMA mobile communication terminal and a high frequency signal module for a high frequency band portable terminal for a PCS service to be implemented is currently under development.

The present invention can perform the functions of the CDMA mobile communication portable terminal of the lower band and the PCS service portable terminal of the upper band in one terminal, Frequency signal module of a high-band digital portable terminal used in a PCS to be used in the future, and a high-frequency signal module of a dual-band digital mobile terminal in which a high-frequency signal module is mixed.

That is, an antenna switch for selecting a high-frequency signal module of a digital portable terminal as an internal antenna signal and an external antenna signal, a trap for selecting a higher-band signal from a signal inputted through the antenna switch, a trap for selecting a lower- An interface block for transmitting / receiving data, and a control block for controlling the system. The interface block includes a lower band CDMA mobile communication interface (hereinafter referred to as a lower band interface) and a higher band PCS service interface (Hereinafter referred to as a higher-band interface), and a common interface unit commonly used for CDMA mobile communication and PCS service.

The lower band interface unit for the CDMA mobile communication uses a known technique, and the higher band interface unit for the PCS service changes the signal processing band of the lower band interface unit and applies it to the corresponding band. Therefore, the main part of the present invention is the common interface unit.

The common interface unit includes a PLL oscillation unit for generating a frequency to be applied to the transmission unit and the reception unit using a main clock applied to the transmission unit and the reception unit for transmission and reception with the upper band interface unit and the lower band interface unit, A voltage-controlled oscillator for generating a main clock of the interface block according to a received signal, and a baseband analog unit for converting signals transmitted and received.

In the present invention, a clock signal used in a high-frequency signal module of a conventional portable terminal for CDMA mobile communication is used as a main clock signal of the system, and a multiplier is provided in an upper interface unit and a divider is provided in a common interface unit .

In the initialization state, when the user turns on the power, the common interface unit is turned on in the control block, and the bandwidth of the band to be served And the interface unit is turned on to prepare for receiving a service. The idle state is a state in which, when a call channel is monitored during a slot allocated to a state after the initial state, message confirmation, terminal registration, idle handoff, The system access state transmits a message to the base station through the access channel, receives the message from the base station via the paging channel, and communicates with the base station using the communication channel in the call channel state.

The present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of the present invention; an antenna switch SW for selecting an internal antenna signal and an external antenna signal; A trap TR1 for selecting an upper band signal from an input signal; A trap TR2 for selecting a lower band signal; A lower band interface unit 20 for a lower band CDMA mobile communication, a higher band interface unit 10 for a higher band PCS service, a common interface unit 30 commonly used for a CDMA mobile communication and a PCS service, An interface block 1 comprising: And a control block 2 for controlling the system.

FIG. 2 is a block diagram showing the detailed configuration of the high-band interface unit 10 in FIG. 1, and includes a transmitting unit 11 for transmitting a signal transmitted from the common interface unit 30 to the outside through an antenna, A receiving unit 13 receiving a signal transmitted from the common interface unit 30 and transmitting the received clock signal to the common interface unit 30 and generating a clock signal used in the upper band interface unit 10 by oscillating a clock signal applied from the common interface unit 30 And a PLL oscillating unit 12 for generating a PLL.

The transmitter 11 includes a bandpass filter FB1 for filtering a signal transmitted from the common interface unit 30 into a signal for use in the higher band interface unit 10, A mixer M 1 for mixing a signal input from the distributor PS 1 and a signal input through the bandpass filter FB 1 and outputting the mixed signal, a mixer M 1 for extracting a surface acoustic wave from the signal output from the mixer M 1, A driver D1 for transmitting a signal output from the band-pass filter FA1 to the amplifier A1; a band-pass filter FA1 for filtering a signal output from the driver D1; An amplifier A1 for amplifying a signal, an isolator IS2 for protecting a signal output from the amplifier A1 and a transmission and reception filter DP1 for transmitting and receiving signals.

The PLL oscillating unit 12 includes a multiplier MU for outputting a frequency of a clock signal applied from the common interface unit 5 and outputting the frequency of the clock signal, A PLL P1 for detecting a clock signal used in the band interface unit 10 and a loop filter L1 for filtering a signal output from the PLL P1 to extract a signal of a signal output from the PLL P1 A voltage controlled oscillator VC3 for receiving the output signal of the loop filter L1 and generating a frequency; a voltage controlled oscillator VC3 for receiving a signal output from the voltage controlled oscillator VC3 and supplying the signal to the PLL P1; And a power distributor PS1 that distributes the signal transmitted from the buffer B1 and transmits the distributed signal to the mixers M1 and M2 of the transmitter 11 and the receiver 13 .

Then, the multiplier MU converts the main clock signal generated by the common interface unit 30 into a clock signal to be used in the high-band interface unit 10 for the PCS service by the signal transmitted from the control block 2 Respectively.

The receiving unit 13 includes a transmitting and receiving filter DP1 for transmitting and receiving signals, an amplifier A5 for amplifying a signal input from the transmitting and receiving filter DP1, A band-pass filter (FA4) for receiving and filtering a signal output from the amplifier (A5) in order to extract an acoustic wave; a band-pass filter (FA4) for filtering a signal outputted from the band-pass filter (FA4) And a mixer M2 for mixing signals output from the mixer 30 and transmitting the mixed signals to the common interface unit 30. [

FIG. 3 is a block diagram showing the detailed configuration of the lower-band interface unit 20 in FIG. 1, a transmission unit 21 for transmitting a signal transmitted from the common interface unit 30 to the outside through an antenna, A receiver 23 for receiving the clock signal and transmitting the clock signal to the common interface unit 30 and a clock signal used in the lower band interface unit 20 using the clock signal applied from the common interface unit 30 And a PLL oscillating unit 22.

The transmitter 21 includes a bandpass filter FB2 for filtering a signal transmitted from the common interface unit 30 into a signal for use in the lower band interface unit 20, A mixer M3 for mixing and outputting a signal output from the power distributor PS2 and a signal input through the bandpass filter FB2 and a mixer M3 for extracting a surface acoustic wave from the signal output from the mixer M3 A bandpass filter FA3 for receiving and filtering a signal output from the mixer M3; a driver D2 for transmitting a signal output from the bandpass filter FA3 to the amplifier A2; A power controller PC for receiving a signal output from the amplifier A2 and for controlling power and re-inputting the signal to the amplifier A2; A2) to protect the output signal And an input / output filter DP2 for transmitting and receiving signals. In the above, the power controller (PC) is an option.

The PLL oscillator 22 includes a PLL P2 generating a clock signal to be used by the lower-band interface unit 20 using a main clock signal applied from the common interface unit 30, A loop filter L2 for filtering a signal output from the PLL P2 in order to extract a parity of the output signal, a voltage controlled oscillator VC4 for generating a frequency by receiving an output signal of the loop filter L2, A buffer B2 for receiving a signal output from the voltage controlled oscillator VC4 and supplying the signal to the PLL P2 and transmitting the signal to the power divider PS2, And a power distributor PS2 for transmitting the signals to the mixers M3 and M4 of the receiving unit 23.

The receiving unit 23 includes a transmitting and receiving filter DP2 for transmitting and receiving a signal, an amplifier A4 for amplifying a signal input from the transmitting and receiving filter DP2, A band pass filter FA2 for filtering a signal outputted from the amplifier A4 to extract an acoustic wave and an alarm detection unit for receiving and detecting the output signal of the band pass filter FA2 for detecting an output signal An automatic gain controller AG for controlling the gain of the amplifier A4 by an output signal of the alarm detection unit DE and a signal output from the band pass filter FA2 and a PLL oscillation unit 22, And a mixer M4 for mixing the signals output from the power distributor PS2 of the power distributor PS2 and transmitting the mixed signals to the common interface unit 30. [

4 is a block diagram showing a detailed configuration of the common interface unit 30 in FIG. 1, and FIG. 4 is a block diagram showing a detailed configuration of the common interface unit 30, A receiving unit 33 for receiving signals input from the upper band interface unit 10 and the lower band interface unit 20 and a receiving unit 33 for receiving signals inputted from the transmitting unit 31 and the receiving unit 33 using the main clock, A voltage controlled oscillator TC1 for generating a main clock of the interface block 1 according to a signal input from the control block 2, a PLL oscillator 32 for generating a frequency to be supplied to the control block 2, And a baseband analog unit 34 for converting the baseband signal. The voltage-controlled oscillator TC1 is for adjusting the fine frequency.

The transmission unit 31 includes an attenuator (AT) for attenuating and outputting a signal transmitted from the baseband analog unit 34, a transmission unit 30 for filtering the signal transmitted from the control block 2 to adjust the sensitivity of the output signal, A low pass filter FC1 for input to a voltage gain controller VGA1 and a transmission voltage gain controller VGA1 for adjusting a voltage gain of a signal output from the attenuator AT by a signal output from the low pass filter FC1, And a divider D3 for transmitting a signal output from the transmission voltage gain controller VGA1 to the higher band interface unit 10 and the lower band interface unit 20. [ The divider D3 includes a trap TR3 for receiving only a signal to be transmitted from the signal input from the transmission voltage gain controller VGA1 to the upper band interface unit 10 and transmitting the signal to the upper band interface unit 10, And a trap TR4 for receiving only a signal to be transmitted to the interface unit 20 and transmitting the signal to the lower band interface unit 20. [

The receiving unit 33 includes a combiner C for combining signals input from the upper band interface unit 10 and the lower band interface unit 20 and a combiner C for combining signals input from the combiner C, Two bandpass filters FA5 and FA6 for receiving and filtering signals output from the amplifier A3 in order to extract surface acoustic waves from the signal output from the amplifier A3, A low pass filter FC2 for filtering a signal transmitted from the control block 2 to adjust the sensitivity of an input signal and inputting the filtered signal to a receive voltage gain controller VGA2 and a low pass filter FC2 for filtering the signal output from the low pass filter FC2 And a receiving voltage gain controller VGA2 for adjusting the voltage gain of the signal output from the band-pass filters FA5 and FA6. One band-pass filter (FA5 or FA6) is selectively used in the two band-pass filters (FA5 and FA6) (FA5 is a digital CDMA system and FA6 is an analog system).

The PLL oscillating unit 32 includes a transmission PLL unit 32-1 for receiving a main clock signal of the system output from the voltage controlled oscillator TC1 and generating a clock signal for controlling the transmission unit 31, And a reception PLL unit 32-2 for generating a control clock signal.

The transmission PLL unit 32-1 includes a PLL (P3) for receiving a main clock signal of the system output from the voltage control oscillator TC1 and locking the corresponding clock signal (transmitter control clock signal) A loop filter L3 for filtering a signal output from the PLL P3 to extract a signal of a signal output from the PLL P3; A tank T2 for generating a low band frequency signal by receiving and resonating an output signal of the loop filter L3; a tank T2 for generating an output signal of the two tanks T1 and T2; And a buffer B3 that receives a signal output from the switch SW1 and outputs the signal to the PLL P3.

Meanwhile, the reception PLL unit 32-2 includes a PLL (P4) for receiving a main clock signal of the system output from the voltage control oscillator TC1 and locking the corresponding clock signal (receiver control clock signal) A loop filter L4 for filtering a signal output from the PLL P4 to extract a signal of a signal output from the PLL P4; And a tank T3 for generating a frequency signal.

The baseband analog unit 34 includes a transmitter 34-1 for transmitting the signal transmitted from the control block 2 to the transmitter 31 and a receiver 34-1 for transmitting the signal transmitted from the receiver 33 to the control block 2. [ And an oscillation unit 34-3 that generates a clock signal to be applied to the system by the main clock signal applied from the voltage control oscillator TC1.

The transmitting terminal 34-1 includes a voltage controlled oscillator VC1 that generates a transmission frequency twice as high as the signal input through the switch SW1 of the transmitting PLL unit 32-1 in the PLL oscillating unit 32, A phase converter U1 for receiving a signal output from the voltage-controlled oscillator VC1 and for converting the phase of the signal; and two digital-to-analog converters (ADCs) Two mixers M5 and M6 for mixing signals output from the phase converter U1 and signals output from the digital-to-analog converters DA1 and DA2; M5, and M6, and outputs the signals to an attenuator (AT) of the transmitter 31. The adder

The receiver 34-2 includes a voltage controlled oscillator VC2 that generates a reception frequency twice as high as a signal input through the tank T3 of the reception PLL unit 32-2 in the PLL oscillation unit 32, A phase converter U2 that receives a signal output from the voltage controlled oscillator VC2 and converts the phase of the received signal to mixers M7 and M8 and a signal output from the phase converter U2 to a receiver 33 Two mixers M7 and M8 for mixing the signals outputted from the voltage gain controller VGA2 of the mixers M7 and M8 and two analogue signals M7 and M8 for converting the analog signals outputted from the two mixers M7 and M8 into digital signals, And an analog / digital converter AD1 for converting the analog signal into a digital signal in order to sense the temperature of the digital converters AD2 and AD3, the battery, and the amplifiers A1 and A2 and take appropriate measures .

The oscillation unit 34-3 generates a clock signal to be input to each of the digital / analog and analog / digital converters DA1 to DA2 and AD1 to AD3 using the main clock signal output from the voltage controlled oscillator TC1. And an oscillator TC2 for generating a clock signal to be input to the multiplier MU of the upper band interface unit 10. The driver The oscillator TC2 supplies the main clock signal generated by the common interface unit 30 to the multiplexer MU of the upper band interface unit 10 and uses the main clock signal generated by the common interface unit 30 in the upper band interface unit 10 for the PCS service And used as a reference clock signal.

The operation of the above configuration will be described in detail as follows.

First, when a signal for making the main frequency of the interface block 1 is input to the voltage control oscillator TC1 of the common interface unit 30 in the control block 2, in the voltage control oscillator TC1, The main clock output from the voltage control oscillator TC1 is supplied to the PLL P2 of the lower band interface unit 20 and the PLL P2 of the common interface unit 30, Is applied to the two PLLs (P3 and P4) of the internal PLL oscillating section 32 and the oscillating section 34-3 in the baseband analog section 34 of the common interface section 30. [

For reference, the voltage-controlled oscillator TC1 uses a VC-TCXO that is finer and finer-tunable than the other voltage-controlled oscillators VC1 to VC4.

The main clock applied to the PLL P2 of the lower band interface unit 20 is subjected to phase comparison in the PLL P2 and output to the loop filter L2. In the loop filter L2, The voltage controlled oscillator VC4 generates the frequency by the voltage output from the loop filter L2 and outputs the generated frequency to the buffer B2 and outputs the frequency to the PLL P2, In the buffer B2, the signal output from the voltage-controlled oscillator VC4 is input to the power distributor PS2. In the power splitter PS2, the signal output from the buffer B2 is distributed The frequency is applied to the transmitting unit 21 and the receiving unit 23 by being applied to the transmitting unit 21 and the receiving unit 23. [ The main clock applied to the two PLLs P3 and P4 of the PLL oscillating unit 32 in the common interface unit 30 is oscillated in the PLL P3 in the transmitting PLL unit 32-1 and input to the loop filter L3 And the loop filter L3 extracts the corruption of the signal output from the PLL P3 and inputs it to the two tanks T1 and T2. In each of the tanks T1 and T2, And outputs the double frequency of the high frequency band and the low frequency corresponding to the transmission frequency to generate a signal from the voltage controlled oscillator VC1. The selection of each of the tanks T1 and T2 is selected by the switch SW1 And the output of the tanks T1 and T2 is input to the buffer B3 and the voltage controlled oscillator VC1 in the transmitter 34-1 of the baseband analogue unit 34. The signal input to the buffer B3 is And output to the PLL P3.

On the other hand, in the reception PLL unit 32-2, the PLL P4 performs phase comparison and is input to the loop filter L4. The loop filter L4 extracts the corruption of the signal output from the PLL P4, , The signal output from the tank T3 is input to the voltage-controlled oscillator VC2 in the receiving end 34-2 of the baseband analog unit 34. Then,

The main clock applied to the oscillation unit 34-3 in the baseband analog unit 34 of the common interface unit 30 is input to each divider / analog / analog / digital converter Is used to generate a new clock signal to be input to the high-band interface unit 10 (DA1 to DA2, AD1 to AD3) and is used to generate a reference clock signal to be input to the high-band interface unit 10 in the divider TC2 of the oscillation unit 34-3 A signal output from the divider TC2 and applied to the higher band interface unit 10 is input to the multiplier MU of the upper band interface unit 10 and multiplied by 5 times in the multiplier MU, When a signal output from the multiplier MU is input to the PLL P1, the PLL P1 oscillates the signal input from the multiplier MU and inputs the signal to the loop filter L1, Extracts the corruption of the signal output from the PLL (P1) The voltage controlled oscillator VC3 generates a frequency by the signal output from the loop filter L1 and inputs the frequency to the buffer B1 and outputs the frequency to the PLL P1 The buffer B1 supplies the signal output from the voltage controlled oscillator VC3 to the power distributor PS1 and the power distributor PS1 distributes the signal output from the buffer B1 to the transmitter 11, And the reception unit 13, as shown in FIG.

That is, when power is applied to the system through the above process, data is transmitted and received. When power is applied to the system, power is not applied to all blocks but power is applied to only a block to be driven, The same operation is performed by the control of the control block 2. [

Since the operation of transmitting and receiving data is the same in operation of the upper band interface unit 10 and the lower band interface unit 20, the process of transmitting and receiving data is described through the upper band interface unit 10, The process in the high band interface unit 20 is the same as the process in the high band interface unit 10 described below.

Also, when data is received (received) through the antenna, the signal input through the internal antenna and the signal input through the external antenna are selected and input from the antenna switch SW, Receiving filter DP1 of the upper band interface unit 10 receives the signal selected in the upper band trap SW and receives the signal inputted in the upper band trap TR1 to the receiving unit 13 The amplifier A5 amplifies the signal output from the transmission / reception filter DP1 and transmits the amplified signal to a band-pass filter FA4 for extracting a top acoustic wave. The band-pass filter FA4 The mixer M2 extracts a surface acoustic wave from the signal transmitted from the amplifier A5 and transmits the extracted acoustic wave to the mixer M2. The mixer M2 mixes the signal transmitted from the band-pass filter FA4 and the power of the PLL oscillator 12, In the distributor (PS1) Mixing the transmitted signal will be sent to the receiving unit 33 within the combiner (C) of the common interface (30). The signal passed through the combiner C in the common interface unit 30 is input to the bandpass filters FA5 and FA6 for amplifying the surface acoustic waves by the amplifier A3 and the bandpass filters FA5, FA6 extracts a surface acoustic wave by filtering the signal inputted from the echo amplifier A3 and outputs the signal. The signal output from the band-pass filters FA5 and FA6 is adjusted by the voltage gain adjuster VGA2, Are input to the two mixers (M7, M8) of the receiving end (34-2) of the band analog unit (34).

When the voltage gain of the voltage gain adjuster VGA2 is controlled, the control block 2 outputs a control signal to adjust the sensitivity of the received signal. The signal output from the control block 2 is applied to a low pass filter FC2 and input to the voltage gain regulator VGA2. The signals input from the voltage gain controller VGA2 to the mixers M7 and M8 are mixed with the signals input to the mixers M7 and M8 in the phase converter U2 and transmitted to the analog / digital converters AD2 and AD3 And converted into a digital signal by the analog / digital converters AD2 and AD3 and transmitted to the control block 2. In the phase converter U2, a signal output from a voltage-controlled oscillator VC2, which generates a frequency by a signal input from a tank T3 in the reception PLL unit 32-2 of the PLL oscillation unit 32, (M7, M8).

When data is transmitted from the control block 2 to the control block 2, the signal output from the control block 2 is transmitted to the common interface 30 of the baseband analogue unit 34 The digital signals input to the digital-to-analog converters DA1 and DA2 are converted into analog signals and input to the two mixers M5 and M6 The two mixers M5 and M6 mix the signals input from the phase converter U1 and the signals input from the digital-to-analog converters DA1 and DA2 and output the mixed signals output from the mixers M5 and M6 The signal is transmitted to the attenuator (AT) of the transmitter 31 via the adder M. [ In the phase shifter U1, the signal output from the voltage controlled oscillator VC1, which generates the frequency by the signal input from the switch SW1 in the transmission PLL unit 32-1 of the PLL oscillating unit 32, And outputs it to two mixers M5 and M6. A signal transmitted from the adder M to the attenuator AT is attenuated by the attenuator AT and transmitted to the voltage gain adjuster VGA1 and the voltage gain adjuster VGA1 adjusts the voltage of the signal output from the attenuator AT And controls the gain to be transmitted to the divider D3 and the signal transmitted from the voltage gain controller VGA1 is transmitted to the bandpass filter FB1 of the upper band interface unit 10 in the upper band trap TR3 of the divider D3 The control block 2 outputs a control signal to the control block 2 in order to adjust the sensitivity of the received signal when the voltage gain of the voltage gain controller VGA1 is adjusted. The signal transmitted from the common interface unit 30 to the higher band interface unit 10 is filtered by the band pass filter (VCO) 1 in the higher band interface unit 10 transmitter 11, (FB1) The signal output from the power distributor PS1 of the PLL oscillator 12 and the bandpass filter FA1 are transmitted to the mixer M1 in the mixer M1. In the bandpass filter FA1, The driver D1 filters the signal output from the mixer M1 to extract an acoustic wave and the driver D1 transmits the signal output from the bandpass filter FA1 to the amplifier A1, In the amplifier A1, the signal transmitted from the driver D1 is amplified and transmitted to the isolator IS2. In the isolator IS2, the signal transmitted from the amplifier A1 is transmitted to the transmitter / receiver filter DP1 , And the transmission / reception filter (DP1) becomes the transmission mode and outputs the signal transmitted from the isolator (IS2) to the antenna.

The relationship between the input / output frequencies of the PLL oscillation unit and the oscillation unit block will be described below with reference to an embodiment.

First, it is designated as a frequency band used by the higher-band signal _Z 1.8GH interface unit 10 for the PCS services (this is a known technique in a wireless terminal configured for a CDMA mobile communication). That is, in the present invention and using the 19.68MH _Z signal for a CDMA mobile communication to the main click signal, a clock signal for PCS service was used to generate a new frequency from the main clock signal (a common interface unit 30, a baseband analog And a multiplexer in the PLL oscillation section of the upper band interface section 10).

On the other hand, two of the PLL (P2) and a common interface (30) within the PLL oscillation unit 32 of the common interface is 19.68MH _Z signal from the voltage-controlled oscillator (TC1) of the 30 lower-band interface 20 in 19.68MH _Z signal PLL (P3, P4), and, PLL (P2) of said common interface unit 30, a baseband is applied to the oscillation unit 34-3 in the analog part 34, the lower-band interface 20 receiving input to accept the divider a ratio of 1/656 and used as a reference frequency, the two PLL (P3, P4) of the common interface (30) within the PLL oscillation unit 32, the input signal of 1/1968 19.68MH _Z And the signal output from the PLL (P3) of the transmitting PLL unit 32-1 is used as a reference frequency of the lower band frequency through the loop filter (L3) in the tanks (T1, T2) is input to the higher-band tank (T1) to 350.80MH _Z, the lower-band tank (T2) is oscillating at a _Z output 260.76MH It said, the output from the PLL (P4) of the reception PLL unit 32-2 signal is input to a tank (T3) via a loop filter (L4), and outputs the generated signal to the reception band of 170.76MH _Z.

Further, the common interface (30) to the divider (D4) from the oscillation unit 34-3 in the analog baseband unit 34 receives the signal _Z 19.68MH divide in the ratio of 512/1025 9.830MH generate a signal _Z the top to the applied to the respective analog / digital, digital / analog converter (AD1~AD3, DA1~DA2) and the divider (TC2) receiving the signal generates a 4.92MH 19.68MH _{Z Z} signal to divide the quarter-rate by applying a multiplier (MU) of the band-interface unit 10, the multiplier (MU) of the higher-band interface unit 10 to generate a signal _Z to the 24.6MH 5x 4.92MH receiving the _Z signal PLL ( P1), and the PLL (P1) receives the 24.6 signal and divides it at a ratio of 1/492 to use it as a reference frequency. In the higher-band interface unit 10 by the process such as the internal reference frequency, and the 50MH _Z, the lower-band interface 20 internal reference frequency is the 30MH _Z.

The present invention constitutes an interface block composed of a lower band interface unit for CDMA mobile communication, a higher band interface unit for PCS service, and a common interface unit commonly used in CDMA mobile communication and PCS service, Frequency signal module using a clock signal used in a conventional portable terminal for CDMA mobile communication and a clock signal for a PCS service using a main clock signal, By allowing CDMAd mobile communication and PCS service to be accommodated, it is possible to control the call quality of communication service (mutual currency conversion between CDMA and PCS when the call volume is overloaded and the call status is bad) So that it can be selected and used.

Claims (14)

An antenna switch SW for selecting an internal antenna signal and an external antenna signal, a trap TR1 for selecting an upper band signal from a signal inputted through the antenna switch, a trap TR2 for selecting a lower band signal, An interface block 1 composed of a lower band interface unit 20 for CDMA mobile communication and a higher band interface unit 30 for a higher band PCS service and a control block 2 for controlling the system In a dual-band digital portable terminal in which a CDMA mobile communication service and a PCS service can be both performed in a single terminal, the common interface unit 30 transmits a signal transmitted from the control block 2 to the high-band interface unit 10 ) And a lower band interface unit (20), and a transmission unit (31) for transmitting the lower band interface unit (10) and the lower band interface unit A PLL oscillating unit 32 for generating a frequency to be applied to the transmitting unit 31 and the receiving unit 33 using an applied main clock, A voltage control generator (TC1) for generating a main clock of the interface block (1) by a received signal, and a baseband analog unit (34) for converting signals to be transmitted and received. . The method as claimed in claim 1, wherein the high-band interface unit (10) receives the main clock signal generated by the common interface unit (30) by a signal received from the control block (2) And a multiplier (MU) is used to make a clock signal to be used. The transmitter according to claim 1, wherein the transmitter (31) comprises: an attenuator (AT) for attenuating and outputting a signal transmitted from the baseband analogue unit (34) Pass filter FC1 for filtering the input signal and inputting it to the transmission voltage gain regulator VGA1 and a transmission voltage gain regulator VCO1 for regulating the voltage gain of the signal output from the attenuator AT by the signal output from the low- And a divider D3 for transmitting a signal output from the transmission voltage gain adjuster VGA1 to the higher band interface unit 10 and the lower band interface unit 20, High frequency signal module. The apparatus according to claim 3, wherein the divider (D3) comprises: a trap (TR3) for receiving only a signal to be transmitted to the higher band interface unit (10) from the signal output from the transmission voltage gain controller (VGA1) And a trap (TR4) for transmitting the signal to the lower band interface unit (20). The receiver as claimed in claim 1, wherein the receiver (33) comprises a combiner (C) for combining signals input from the higher band interface unit (10) and the lower band interface unit (20) Two band-pass filters FA5 and FA6 for receiving and filtering a signal output from the amplifier A3 in order to extract a surface acoustic wave from a signal output from the amplifier A3, an amplifier A3 for amplifying a signal, A low pass filter FC2 for filtering a signal transmitted from the control block 2 to adjust the gain of the input signal and inputting the filtered signal to the receive voltage gain controller VGA2 and a low pass filter FC2 for filtering the signal output from the low pass filter FC2 And a receiving voltage gain controller (VGA2) for adjusting a voltage gain of a signal output from the band pass filters (FA5, FA6). 6. The method of claim 5, wherein one band-pass filter (FA5 or FA6) in the two band-pass filters (FA5 and FA6) uses FA5 in the digital CDMA system and an analog AMPS (Advanced Mobile Phone System: Frequency signal module of the dual-band digital portable terminal, which uses FA6 in the case of a telephone system, a portable telephone type next-generation car telephone system). The PLL circuit according to claim 1, wherein the PLL oscillator (32) comprises a transmission PLLQN (32-1) for receiving a main clock signal of the system output from the voltage controlled oscillator (TC1) and generating a clock signal for controlling the transmitter (31) And a reception PLLQN (32-2) for generating a control clock signal for controlling the high frequency signal module (33). The transmission PLLQN according to claim 7, wherein the transmission PLLQN (32-1) receives the main clock signal of the system output from the voltage controlled oscillator (TC1) and generates a corresponding clock signal (transmitter control clock signal) A loop filter L3 for filtering a signal output from the PLL P3 to extract a signal of a signal output from the PLL P3 and a PLL P3 for receiving an output signal of the LF filter L3 A tank T2 for generating a lower band frequency signal by resonating an output signal of the LF filter L3 and generating a lower band frequency signal by resonating the output signal of the LF filter L3; A switch SW1 for selecting one of output signals of the switch SW1 and a buffer B3 for receiving a signal output from the switch SW1 and supplying the signal to the PLL P3 at a comparison frequency. Digital mobile terminal high frequency signal module. The receiver PLLQN 32-2 receives the main clock signal of the system output from the voltage controlled oscillator TC1 and generates a corresponding clock signal (receiving clock signal) to the loop filter L4 A lef filter L4 for filtering the signal output from the PLL P4 in order to extract the corruption of the signal output from the PLL P4 and a PLL P4 for receiving the output signal of the loop filter L4 And a tank (T3) that resonates and generates a reception band frequency signal. The receiver according to claim 1, wherein the baseband analog unit (34) comprises a transmitter (34-1) for transmitting the signal transmitted from the control block (2) to the transmitter (31) (34-3) for generating a clock signal to be applied to the system by a main clock signal applied from a voltage-controlled oscillator (TC1), and an oscillation unit (34-3) for generating a clock signal to be applied to the system. Band digital mobile terminal high frequency signal module. The PLL circuit according to claim 10, wherein the transmitting terminal (34-1) comprises: a voltage controlled oscillator (VC1) for generating a frequency by a signal inputted through the switch (SW1) of the transmitting PLLQN (32-1) in the PLL oscillating section (32) A phase converter U1 that receives a signal output from the voltage controlled oscillator VC1 and converts the phase of the received signal to mixers M5 and M6 and a phase shifter U2 that converts the digital signal transmitted from the control block 2 into an analog signal Analog converter DA1 and DA2 and a signal outputted from the phase converter U1 and digital-to-analog converters DA1 and DA2 and a signal output from the phase converter U1 and digital-to-analog converters DA1 and DA2, And an adder M for receiving a signal output from the two mixers M5 and M6 and outputting the received signal to an attenuator AT of the transmitter 31. The mixer M5, Frequency signal module of the dual band digital mobile terminal. The receiver of claim 10, wherein the receiving stage includes a voltage controlled oscillator (VC2) for generating a frequency by a signal output through a tank (T3) of a receiving PLL unit (32-2) in the PLL oscillating unit A phase converter U2 that receives a signal output from the voltage controlled oscillator VC2 and converts the phase of the received signal to mixers M7 and M8; Two mixers M7 and M8 for mixing the signals output from the gain controller VGA2 and two analog / digital converters for converting the analog signals output from the two mixers M7 and M8 into digital signals And an analog / digital converter (AD1) for converting the analog signal into a digital signal in order to sense the temperature of the battery (A1, A2) and the battery voltage and to take appropriate measures. Terminal high frequency signal module. The oscillation unit (34-3) of claim 10, wherein the oscillation unit (34-3) comprises a clock signal to be input to each of the digital / analog and analog / digital converters (DA1 to DA2, AD1 to AD3) using the clock signal outputted from the voltage- A divider D4 for generating a signal and a divider TC2 for generating a clock signal to be input to the multiplier MU of the upper band interface unit 10. The dual band digital mobile terminal of claim 1, The system of claim 13, wherein the divider (TC2) supplies the main clock signal generated by the common interface unit (30) to the multiplier (MU) of the upper band interface unit (10) And the reference clock signal is used as a reference clock signal to be used in the high-frequency signal module.