KR100232320B1 - Enhanced mobility p-channel structure in silicon on insulator - Google Patents

Abstract

The field effect transistor of the present invention is formed by alloying, oxidizing, precipitation or synthesizing in a semiconductor material layer to have a volume larger than the initial volume and to have a channel region subjected to biaxial compressive stress. . The present invention solves the problems of CMOS logic circuits having n-channel and p-channel transistors with low carrier mobility and p-type channel transistors with low carrier mobility.

Description

Device for improving carrier mobility and semiconductor island forming method

FIELD OF THE INVENTION The present invention relates to p-channel and n-channel field effect transistors of silicon on insulators, in particular the effective band edge mass of heavy hole bands due to compressive stress in the silicon plane. (silicon island) of a silicon on insulator that allows for reduced band edge mass and reduced effective mass of the conduction band.

Stresses in silicon thin films can be used to improve the properties of field effect transistors (FETs). In one embodiment, when a semiconductor, such as silicon, is subjected to biaxial stress in the plane of the layer, the hole mobility of the channel FETs used in complementary metal oxide semiconductor (CMOS) logic, memory, and analog circuits. (hole mobility) can be improved. The performance degradation of the p-FET is due to the scattering properties of the holes at low electric fields, as well as the high effective mass of the holes, thereby reducing the carrier speed. This reduces the mobility relative to the velocity and becomes a common measure of the carrier's transmission. As the speed of holes or hole mobility increases, the performance of p-channel FETs, CMOS circuits and memories will be improved correspondingly. In addition, under sufficiently high stresses, if the velocity of the electrons increases, the improvement is made in the n-channel device, although the ratio is smaller.

The field effect transistor disclosed in US Patent No. 3,566,215, issued February 23, 1971 to W. Heywang, improves carrier mobility by mechanically stressing the semiconductor substrate. During deposition of the silicon layer, the temperature of the substrate having a material different from that of silicon was raised, and upon cooling the silicon layer was stressed due to the difference in thermal contraction of the substrate relative to the layer.

The SOI substrate disclosed in US Pat. No. 5,461,243, issued October 24, 1995 to BA Ek et al., Initially has a silicon layer thereon, a SiGe layer is grown thereon and relaxed to the thickness of this layer ( and a layer of silicon is grown on the SiGe layer. The silicon layer is subject to tensile strain due to mismatch of lattice spacing.

According to the present invention, there is provided an apparatus and method for improving the mobility of holes and electrons in a carrier of a semiconductor layer, including an insulating substrate and a semiconductor layer located on the insulating substrate, the semiconductor layer comprising a second region. A first region substantially enclosing the periphery), wherein the first region is a process selected from the group comprising alloying, oxidizing, precipitating, and reacting processes. Thereby forming an alloy, oxide, precipitate or compound, alone or in combination with materials of the semiconductor layer, whereby the first region has a volume larger than the initial volume of the material, thereby allowing the second region. Under this compressive stress (high enough stress for the second region), degeneracy of the valence band is eliminated and in the band of the carrier such as a hole An apparatus and method are provided that reduce band edge mass of carriers and improve the transport of holes and electrons.

In addition, the present invention forms a channel region of the semiconductor layer subjected to compressive stress in the biaxial direction due to the peripheral oxidation of the semiconductor layer around the channel region, such that the stress reduces the mass of planar carriers, holes and electrons and changes the ratio. Provided are p-channel and n-channel field effect transistors with improved carrier mobility such that is reduced and subjected to large stresses.

The present invention also includes a layer of semiconductor material on an insulator, a first region subjected to compressive stress in the biaxial direction by oxidizing a partial layer around the second region, and a p-channel field effect transistor formed in the first region. Provides a CMOS logic circuit. The semiconductor layer described above for forming a CMOS also includes a similar n-channel field effect transistor in design and a conductor interconnecting the p and n-channel field effect transistors.

The foregoing and other features, objects, and advantages of the present invention will become more apparent with reference to the detailed description of the invention in conjunction with the accompanying drawings.

1 is a graph illustrating the operation of a directional bandgap semiconductor according to compressive, zero and tensile stresses in the biaxial direction;

FIG. 2 is a graph illustrating the operation of a directional bandgap semiconductor such as silicon according to biaxial compressive stress (strain), zero stress and tensile stress in the plane 100.

FIG. 3 is a graph depicting calculations for silicon valence bands in the <110> and <100> directions parallel to the top surface according to tensile strain, zero strain and compressive strain

FIG. 4 is a graph depicting calculations for silicon valence bands in the <111> and <1> directions parallel to the top surface according to tensile strain, zero strain and compressive strain

5 is a graph showing the calculation of hole mobility of silicon according to strain

6 is a graph showing the calculation of electron mobility of silicon according to strain

7-9 illustrate one embodiment of the manufacturing progress steps for implementing the embodiment of the present invention shown in FIG.

10 illustrates one embodiment of the present invention.

11 is a plan view of a second embodiment of the present invention;

12 is a cross-sectional view taken along line 12-12 of FIG.

13 is a plan view of a third embodiment of the present invention;

14 is a plan view of a fourth embodiment of the present invention.

Explanation of symbols for the main parts of the drawings

112: carrier layer 113: insulating layer

114, 150: semiconductor layer 116: mask

118: oxide layer 119: silicon region

122: p-channel field effect transistor 126: gate oxide layer

128: gate electrode 129, 131, 133: lead

141: semiconductor island 142: trench

143: silicon dioxide 153: polysilicon

156: quantum wiring device 157: quantum wiring

158, 167: oxidation region 170: quantum box

Referring to FIG. 1, there is shown a graph of a direct bandgap semiconductor layer affected by biaxial compressive stress, zero stress, and biaxial tensile stress in the plane of the layer. In Figure 1, the ordinate represents energy and the abscissa represents stress. Curve 12 is the conduction band edge of the compressive stressed semiconductor layer. Curves 13 and 14 are the valence band edges of the corresponding layer subjected to compressive stress. Curves 13 and 14 are separated from each other, and curve 14 has lower energy. Curve 15 is the conduction band edge of the zero stressed semiconductor layer. Curves 16 and 17 are valence band edges of the corresponding layer subjected to zero stress. Curve 20 is the conduction band edge of the semiconductor layer under tensile stress. Curves 21 and 22 are valence band edges of the corresponding layer under tensile stress. The maximum energy of curve 21 at point 23 is lower than the maximum energy of curve 22 at point 24. As shown by curves 13 and 14 and curves 21 and 22, the valence band edges of the layer are divided according to compressive or tensile stress, respectively. Reference line 26 shows that the conduction band edge has gradually lower energy as it progresses from the compressive stress layer through the zero stress layer to the tensile stress layer. Reference line 27 shows that the valence band edge has a higher energy as it progresses from the compressive stress layer through the zero stress layer to the tensile stress layer.

FIG. 2 is a graph showing indirect bandgaps of a semiconductor layer, such as silicon, affected by biaxial strain in the plane 100. In Figure 2, the ordinate represents energy and the abscissa represents stress. Curve 29 is the conduction band edge of the compressive stressed semiconductor layer. Curves 30 and 31 are valence band edges of the corresponding layer subjected to compressive stress. Curves 30 and 31 are separated from each other, and curve 31 has lower energy. Curve 33 is the conduction band edge of the semiconductor layer with zero stress. Curves 34 and 35 are valence band edges of the corresponding layer subjected to zero stress. Curve 37 is the conduction band edge of the semiconductor layer under tensile stress. Curves 38 and 39 are valence band edges of the corresponding layer under tensile stress. Reference line 41 indicates that the conduction band edge has lower energy under compressive stress (point 44) than under zero stress (point 42). Reference line 43 shows that the conduction band edge has lower energy under tensile stress (point 45) than under zero stress (point 42). It should be noted that in FIG. 1 the reference line 26 from compressive stress to zero stress proceeds in a low direction, whereas in FIG. 2 the reference line 41 from compressive stress to zero stress proceeds in a high direction. Thus, point 44 on curve 41 in FIG. 2 is lower than points 42 and 45 on curve 43. Reference line 47 indicates that the valence band edge has higher energy as it progresses from the compressive stress layer through the zero stress layer to the tensile stress layer.

Referring to Figure 3, curves 51-68 are shown. In FIG. 3, the ordinate represents energy (eV) and the abscissa represents a k-vector (2π / a). Curves 51-53 show the EP written for the k-vector, where EP represents three valence bands separated from each other. EP is experimental (not local) pseudopotentials. Kp (pronounced k dot p) represents an approximate solution of the valence band, where k is the electron or hole quasi-momentum and p is the momentum operator ).

Curves 54-56 show kp plotted for the k-vector, where kp represents three valence bands separated from each other. Curves 51-56 are calculated for tensile stresses with lattice parameter a in the plane of the silicon layer of 1.034 Angstroms, and c / a0 is 0.975. Where c is the lattice parameter in the <100> direction, ie the direction perpendicular to the top surface. Curves 51-56 on the left side of reference line 70 are for the <110> direction, and curves 51-56 on the right side of reference line 70 are for the <100> direction.

For k-vectors curves 57-59 represent EP and curves 60-62 represent kp, and k-vectors represent two valence band curves 57, 58, 60, 61 of the three valence bands. As shown by, the scattering of carriers is increased by overlapping each other. The silicon layer was not strained. The curves 57-62 on the left side of the reference line 71 are for the <110> direction, and the curves 57-62 on the right side of the reference line 70 are for the <100> direction.

For k-vectors curves 63-65 represent EP and curves 66-68 represent kp and these curves represent three valence bands for the silicon layer subjected to compressive strain. In the silicon layer, a / a ₀ corresponding to a unit cell is compressed from 1 to 0.970, and c / a ₀ is 1.025. Curves 63-68 on the left side of reference line 72 are for the <110> direction, and curves 63-68 on the right side of reference line 72 are for the <100> direction. Curves 63-68 show that the three valence bands are separated.

4, curves 81-98 and reference lines 100-102 are shown. In FIG. 4, the ordinate represents energy (eV) and the abscissa represents a k-vector (2π / a). In FIG. 4, curves 81-86 are calculated for the silicon layer under tensile strain and correspond to curves 51-56 of FIG. 3, but indicate different directions for the k-vector. The curves 81-86 on the left side of the reference line 100 are for the <111> direction of the silicon layer, and the curves 81-86 on the right side of the reference line 100 are for the <1> direction.

Curves 87-92 are calculated for the zero strained silicon layer and correspond to curves 57-62 of FIG. 3, but indicate different directions for the k-vector. The curves 87-92 on the left side of the reference line 101 are for the <111> direction of the silicon layer, and the curves 87-92 on the right side of the reference line 101 are for the <1> direction.

Curves 93-98 are calculated for the silicon layer subjected to the compressive strain and correspond to curves 63-68 of FIG. 3, but indicate different directions for the k-vector. Curves 93-98 on the left side of reference line 102 are for the <111> direction of the silicon layer, and curves 93-98 on the right side of the reference line 102 are for the <1> direction.

3 and 4, the silicon layer is oriented so that the parallel plane directions point to <110> and <100>. 3 and 4 show that the valence band is split by providing either the compressive stress or the tensile stress in the biaxial direction with respect to the silicon layer having the aforementioned directing direction. When the valence bands are separated from each other, carrier scattering is reduced to increase the mobility of the carriers.

5 is a graph showing the hole mobility calculated for strain in 300K silicon (001). In FIG. 5, the ordinate represents hole mobility, and the abscissa represents strain c / a ₀ . Curve 105 represents the hole mobility of the silicon layer in the <100> direction parallel to the layer (in in plane), and curve 106 is perpendicular to the layer (in off plane). The hole mobility in the <1> direction is shown. In FIG. 5, when c / a ₀ is 1.00, there is no strain in the silicon layer. In FIG. 5, the acoustic phonon deformation potential Δac is 6.1 eV and the optical phonon deformation potential (DK) op is 7.98 × 10 ¹⁰ eV / cm. If there is even a very small tensile strain with respect to the silicon layer, the mobility of the parallel planes is rapidly increased at c / a ₀ , for example with a value of 0.99 (point 103), so that the mobility μ is about 5 Increase from x10 ² to about 3 × 10 ³ cm ² / Vs. In addition, if there is even a very small compressive strain with respect to the silicon layer, the mobility of the parallel plane is rapidly increased, for example, at c / a ₀ with a value of 1.01 on the abscissa of the point 104, so that the parallel plane shifts The figure increases from about 5 × 10 ² to about 1.3 × 10 ³ cm ² / Vs. 5 and 6, the lattice space c is a direction perpendicular to the silicon layer, and the lattice space a ₀ is a direction parallel to the silicon layer.

6 is a graph of calculated electron mobility for strain of silicon at 300K. In FIG. 6, the ordinate represents electron mobility and the abscissa represents strain c / a ₀ . Curve 108 represents the electron mobility of the silicon layer in a direction parallel to the layer, and curve 109 represents the electron mobility of the silicon layer perpendicular to the layer. If c / a ₀ of FIG. 6 is 1.00, there is no strain in the silicon layer. In FIG. 6, the dilation deformation potential Ed is +1.1 eV and the uniaxial deformation potential Eu is 10.5 eV. As shown by curve 108, if there is a value for a small amount of tensile strain of about 0.99 for the silicon layer in abscissa, the electron mobility is from about 1.5 × 10 ³ to about 2.25 × 10 ³ cm ² / Vs To increase. If there is a small amount of compressive strain of about 1.01 for the silicon layer in abscissa, the electron mobility slowly decreases from about 1.5 × 10 ³ to about 1.3 × 10 ³ cm ² / Vs, but slightly more than 1.025 in abscissa. With values for large compressive strains the electron mobility increases from about 1.5 × 10 ³ to about 1.7 × 10 ³ cm ² / Vs. As shown for curve 109, the presence of a small amount of tensile strain reduces the electron mobility in the vertical direction with the silicon layer, and the presence of a small amount of compressive strain increases the electron mobility in the vertical direction with the silicon layer. . Thus, if there is a small amount of strain of about 1 percent on c / a ₀ relative to the mobility in the direction parallel to the top surface, hole and electron transfer for either compressive strain in the biaxial direction or tensile strain in the biaxial direction The degree is increased.

Referring to FIG. 7, a substrate 111 of a silicon on insulator is shown. For example, the carrier layer 112, which may be silicon, has an insulating layer 113 formed on the top surface, which may be, for example, silicon dioxide. In addition, the insulating layer 113 may be formed by an oxidation step after ion implantation of oxygen. A process called separation by implantation of oxygen (SIMOX) can be used in such a process. The semiconductor layer 114 may be, for example, monocrystalline silicon and may be formed by a SIMOX process or a bond and etch back process, which process is carried out by RH Dennard et al. 1995. U.S. Patent No. 5,462,883, issued October 31, 1986. Layer 114 may have a thickness in the range of 250-5000 angstroms and typically has a thickness of 2000 angstroms or less.

Referring to FIG. 8, a mask 116 is shown that may be an insulating metal that includes silicon oxide and / or silicon nitride. The mask 116 functions to protect the semiconductor layer 114 under the mask 116 while oxidizing the layer 114 surrounding the protective region. Mask 116 is a layer that is first deposited on layer 114 and then patterned.

Thereafter, the semiconductor layer 114 having the mask 116 thereon is oxidized. Oxidation is performed by conventional thermal dry or wet oxidation means, such that the mask 116 may comprise silicon oxide and silicon nitride. Oxidation can also be achieved by injecting oxygen at high doses similar to those used to implement SOI wafers through the SIMOX process. If oxygen injection is used, the material used for the mask 116 may be obtained from a broader set of materials that includes substantially photoresists.

As shown in FIG. 9, oxidizing the peripheral region protected by the mask 116 causes the silicon dioxide to expand around the silicon under the mask 116. The unprotected layer 114 is fully oxidized to form an oxide layer 118 with the layer 114 remaining in the silicon region 119. Mask 116 remains on silicon region 119. The expansion of the silicon dioxide volume is slightly larger than the coefficient 2, and the molecular weight of the silicon molecule has 12.056 cm ⁻³ . When expansion is performed in this manner, compressive stress is generated between the silicon regions 119. As shown in FIG. 10, a device such as p-channel field effect transistor 122 may be partially fabricated prior to stripping mask 116 on silicon region 119 or fully fabricated thereafter. Can be. This compressive stress increases the hole mobility of the silicon region 119. The stresses are all generated on the four sides of the region 119 and thus are biaxially generated in two transverse directions in the plane of the region 119 or with a stress of the region 119 parallel to the top surface. Has a direction. This stress may be in two perpendicular directions to the plane of region 119.

The magnitude of the stress in the silicon region 119 is a function of the aspect ratio (length to width), the area, and the volume and size of the surrounding silicon to be subsequently oxidized. Thus, in the geometry of the transistor where the aspect ratio of each silicon region may have 3: 1, it has a different stress than the FET whose characteristic ratio of each silicon region is 1: 1. The latter has a uniform biaxial stress when the surrounding oxide regions are symmetrical. In either case, the stress can be controlled through control of the silicon and silicon dioxide regions.

Typically, a stress that results in a small change of less than 2% at c / a ₀ is desirable, and is accomplished by oxidizing a very small area around silicon region 119. Oxidation of a very small region around region 119 may cause the isolation oxide to have an area similar to that of a p-channel device with shallow trench isolation. Thus, there is little loss of packing density compared to shallow trench isolation. More importantly, it becomes possible to design stresses and may be asymmetric.

Referring to FIG. 10, a p-channel field effect transistor 122 formed in the silicon region 119 is shown. Source 123 and drain 124 are formed on the upper surface of silicon region 119. Gate oxide layer 126 is formed on silicon region 119. The gate electrode 128 is formed on the gate oxide layer 126 and may be made of aluminum or polysilicon. Gate 128 may be connected to lead 129. The source 123 may be connected to the lead 131 and the drain 124 may be connected to the lead 133. The n channel field effect transistor can be shown in a similar manner as the transistor 122. N-channel and p-channel transistors can be used to form CMOS logic circuits, which are well known in the art.

FIG. 11 is a plan view illustrating a semiconductor island 141 surrounded by a trench 142, having a dielectric layer such as silicon dioxide 143 on the inside of the trench 142, and the dielectric layer shown in FIG. 12. As shown, the side walls and the lower part are applied. FIG. 11 is a cross-sectional view taken along line 12-12 of FIG. 12. In Fig. 12, the aspect ratio of the semiconductor island 141, i.e., length to width, is 1, and thus the length is equal to the width.

As shown in FIG. 12, the substrate 146 has an upper surface 147 and includes silicon, silicon germanium alloy, silicon carbide, gallium arsenide, gallium indium acetone. Gallium indium arsenide, gallium aluminum arsenide and indium phosphide. An insulating layer 149, such as silicon dioxide, is formed on the top surface 147. Semiconductor layer 150 is formed on layer 149, and layer 149 may be a single crystal semiconductor of the same or different material as substrate 146 and has a thickness of about 2000 angstroms. The trench 142 may be formed through the layers 150 and 149 to the substrate 146.

The trench 142 may be filled with amorphous silicon, which may then be converted to polysilicon 153 by heat treatment in the range of 600-750 ° C. Polycrystalline silicon is expanded until a compressive stress and strain are applied to the semiconductor islands 141. Alternatively, the polysilicon 153 may be oxidized to form silicon dioxide, which may expand to apply a compressive force to the semiconductor island 141. Instead of successive trenches in the periphery of the semiconductor islands 141, a plurality of separated spaces are formed along the trench paths, or a plurality of short trenches are formed along the periphery of the semiconductor islands 141 to provide compressive stress in the biaxial direction. 141 may be provided.

FIG. 13 is a plan view of a quantum wiring device 156 with a quantum wire 157, which is formed of a semiconductor material such as a material suitable for the substrate 146. An oxide region 158 is formed in the semiconductor layer 150. In FIG. 13, similar reference numerals are used for functional parts corresponding to the apparatus of FIGS. 11 and 12. Electrodes 161 and 162 create ohimic contacts to each end of quantum interconnect 157. The electrode 163 creates an electrical contact in the middle of the quantum wiring 157 or provides a gate electrode on the insulating region 164 that insulates the quantum wiring 157 from the electrode 162.

The quantum wiring 157 can be formed by using a thin line having a large aspect ratio value. For example, using a 0.45 micron line on 0.2 micrometer thick silicon can produce a narrow sub 500 angstrom line, which then controls oxidation to surround the line. The quantum interconnects can then be designed to have the desired properties depending on the stresses they are formed or programmed.

14 shows a quantum box 170. Similar reference numerals are used in FIG. 14 for functions corresponding to the apparatus of FIGS. 11 and 12. The semiconductor islands 141 may be formed by oxidizing the controlled semiconductor layer 150 around the periphery to form the structure or the semiconductor islands 141 in a 1: 1 characteristic ratio. The peripheral oxide region 167 surrounds the semiconductor island 141.

It will be appreciated that silicon region 119 and silicon layer 114 may be replaced with other semiconductor compounds suitably designated for substrate 146.

While the present invention is shown and described with a semiconductor layer stressed to provide improved carrier mobility for the field effect transistors formed in the layer, those of ordinary skill in the art, as defined in the appended claims, It will be understood that various modifications and changes can be made without departing from the scope of the present invention.

Thus, the field effect transistor of the present invention is formed by alloying, oxidizing, precipitation or synthesizing in a semiconductor material layer to provide a channel region which has a volume larger than the initial volume and is subjected to biaxial compressive stress, and the mobility of the carrier It provides the advantages of solving the problems of CMOS logic circuits having low n-channel and p-channel transistors and p-type channel transistors with low carrier mobility.

Claims (9)

An apparatus for improving the mobility of carriers in a semiconductor layer, ① an insulating substrate, ② comprises a semiconductor layer located on the insulating substrate, The semiconductor layer has first regions that substantially surround a second region, the first region alloying, oxidizing, precipitating, and reacting. formed by a process selected from the group comprising a reacting process, whereby an alloy, oxide, precipitate or compound having a material of the semiconductor layer is formed such that the first region is larger than the initial volume of the material. Resulting in a compressive stress in the second region, thereby eliminating the degeneracy of the valence band and reducing the band edge mass of carriers. felled Device for improving carrier mobility. The method of claim 1, And said second region further comprises a p-channel field effect transistor. The method of claim 1, And said second region further comprises an n-channel field effect transistor. The method of claim 2, Further comprising a plurality of first and second regions, wherein an n-channel field effect transistor is formed in at least one of the plurality of second regions. The method of claim 4 And interconnect interconnection between at least one of said p-channel and n-channel transistors to construct a CMOS logic circuit. In a quantum wire, ① insulation layer, A line of semiconductor material having a thickness, a length and a width and having a width of less than 500 angstroms on the insulating layer; A surrounding region of material that compresses the width of the line to improve the mobility of the carrier of the line as the band is separated Quantum wiring. In a quantum box, ① insulation layer, (2) an island of semiconductor material having a thickness, a length and a width, wherein said length and width are less than 500 angstroms on said insulating layer; (3) a quantum box comprising a perimeter region of material that compresses the length and width of the island to improve the mobility of the carrier of the island as the band of carriers is separated. A method of forming a semiconductor island such that band separation of a carrier is increased, ① selecting an insulating layer, (2) forming a semiconductor island on the insulating layer; (3) forming a trench around the semiconductor island; ④ filling the trench with an amorphous material, Converting the amorphous material into a crystalline material such that the semiconductor island is subjected to a biaxial compressive stress as the amorphous material expands into a polycrystalline material; Semiconductor island formation method. The method of claim 3, wherein And oxidizing the polycrystalline material.

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