KR100232096B1 - Vlsi of systolic array for discrete wavelet transform - Google Patents

Abstract

In the systolic array structure for the discrete wavelet transform calculation, the present invention stores coefficients of a low frequency wavelet filter and a high frequency wavelet filter, and analyzes one level of analysis wave by a processing element that multiplies and outputs an input value and a stored value. Systolic array for discrete wavelet transform calculation, characterized in that the high frequency filter output and the low frequency output are alternately calculated during the calculation of the letlet and the calculation of the composite wavelet of one level so as not to calculate an unused output sequence at the next level. Present the structure.

Description

Structure of VLSI for Discrete Wavelet Transform

1 is a diagram showing a three-level analysis process of DWT.

2 is a diagram showing a three-level synthesis process of DWT.

3 shows a Type I systolic array structure for one level analysis wavelet calculation.

4 shows a type II systolic array structure for one level analysis wavelet calculation.

FIG. 5 shows the functionality of the processing elements used in Type I shown in FIG. 3 and Type II shown in FIG.

6 shows a systolic array structure for three-level DWT calculation.

7 shows a systolic array structure for one level composite wavelet calculation.

The present invention relates to a systolic array structure for Discrete Wavelet Transform (DWT).

Among the image compression methods, the transform coding method has a good compression ratio, but since the used basis is discontinuous between blocks, a block effect occurs in a reproduction operation.

DWT has recently been proposed to reduce this block effect.

DWT can express signals with locality with respect to time and frequency, which is advantageous for interpreting non-stationary image signals, and the images represented by these images are similar to human visual characteristics. I started to receive.

However, although DWT is a useful change, it is difficult to process in real time due to a large amount of calculation. In order to solve this problem, a method of improving the processing speed of an algorithm using a parallel computer has been studied.

Recently, the development of a dedicated computer for a specific algorithm has been promoted in consideration of the cost, complexity, and system load of a general purpose computer. A typical example is a systolic / wavefront array using VLSI technology.

Systolic arrays are dedicated hardware architectures that achieve maximum concurrent execution to improve the performance of specific algorithms using VLSI technology. The characteristics of a systolic array are modularity, regularity, local connectivity, highly dependent connectivity, and well-synchronized. Multiprocessing and so on. This structure is popular for DSP applications because of its simple control and high throughput per unit time.

The conventional structure for DWT calculation is Knowles's structure, published in 1990, which requires a large multiplexer to store intermediate results.

Parhi and Nishitani proposed a `` folded architecure '' with a short computation time, but the disadvantage is that it requires hardware for complex routing and control.

In addition, this structure has a disadvantage that the structure is not easily determined when the filter size is changed. Vishwanath et al. Implemented using RPA (Recursive Pyramid Algorithm), but has a disadvantage in that a routing network is required.

It is an object of the present invention to provide a systolic array structure for DWT calculation that compensates for the shortcomings of the conventional structure as described above.

In order to achieve the above object, the present invention is a systolic array structure for discrete wavelet transform calculation, and stores the coefficients of the low frequency wavelet filter and the high frequency wavelet filter and outputs by multiplying the input value and the stored value In the calculation of the analysis wavelet of one level and the calculation of the composite wavelet of one level by the processing element to calculate the high frequency filter output and the low frequency output alternately so as not to calculate the output sequence not used in the next level A systolic array structure for the discrete wavelet transform calculation is presented.

In addition, the present invention proposes a systolic array structure in which the input and output of the systolic array structure for one level calculation as described above are connected in series to enable multilevel discrete wavelet transform calculation.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

In the present specification, for convenience, a systolic array structure for DWT calculation having a level number of three and a filter tap number of four is described as an example.

Before describing the systolic array structure for DWT calculation according to the present invention, DWT will be described.

DWT is an example of a subband coating consisting of analytical and synthetic processes.

1 is a diagram illustrating a three-level analysis process of DWT.

In FIG. 1, G is a high frequency wavelet filter and H is a low frequency wavelet filter. When the input signal a is input, the signal passing through the G filter is downsampled 2: 1 and output to u. On the other hand, the signal v passed through the H filter and downsampled passes through the G filter and the H filter again.

2 is a diagram illustrating a three-level synthesis process of DWT.

2 is a reverse of the three-level analysis process of FIG. The input signals y and z are up-sampled 1: 2 and pass through the G and H filters, respectively, and are summed into x signals.

1 and 2 are the overall block diagram of the one-dimensional DWT, the main features are as follows.

First, each level is configured identically. That is, a block for G and H filtering and a block for downsampling constitute one block. However, there is a problem in hardware implementation because the blocks are the same but the timing of the input values at each level is different due to downsampling. In more detail, the first level is input every clock, but the second clock is input only at an even clock by downsampling at the first level, and the third level is input every four clocks.

Second, the large amount of computation passes through the low-frequency wavelet filter H, and how to implement this block becomes an important problem.

Third, since each level is downsampled after passing through the G and H filters, all the results of the filtering calculations are not required. Therefore, this feature should be used in hardware implementation.

Hereinafter, a method of implementing the above-described DWT using a systolic array structure will be described.

It is assumed that the transfer function of the high frequency wavelet filter G and the low frequency wavelet filter H is expressed by the following equation (1).

If one level of DWT calculation process is displayed, the following equation (2) is shown.

In Equation (2), a _n represents an input sequence and v _n represents a low frequency output sequence.

In Equation (2), v _{2n + 1} , n≥0, are not used at the next level, and do not need to be calculated, and only calculation of a _2n h _2m and a _{2n + 1} h _{2m + 1} is necessary. Using this feature, the present invention proposes a structure for calculating a level of analysis DWT as shown in FIGS. 3 and 4.

3 shows a Type I systolic array structure for one level analysis wavelet calculation, and FIG. 4 shows a Type II systolic array structure for one level analysis wavelet calculation.

In the structures shown in FIGS. 3 and 4, H (z) and G (z) are stored in a processing element (PE) and input a _n is input from the left to alternate outputs v _2n and u _2n . I was going to calculate. In this way, u _2n is calculated without calculating v _{2n + 1,} which is not necessary. A1 to A3 shown in FIG. 3 are processing elements for calculating the sum of two inputs, and D is a processing element for delaying the input by one clock.

In FIG. 3, x, y, and z denote the number of delayed clocks, which can be obtained by the following equation (4).

In Equation (3), C represents a clock difference. For example, the first, second, and third levels of x are 1, 2, and 4, y is 0, 2, and 6, and z is 1, 4, and 10. In Figures 3 and 4, one clock is the time to multiply one sum and product.

In the type II systolic array structure shown in FIG. 4, the D processing element and the A processing element are not necessary.

FIG. 5 is a diagram illustrating the functionality of the processing elements used in Type I shown in FIG. 3 and Type II shown in FIG.

5 (a) is a processing element for multiplying g (h) stored in the processing element by an input a, and 5 (b) is a processing element for delaying an input by one clock, and FIG. 5c is a processing element for adding two inputs. The processing elements shown in Figures 5 (a) through 5 (c) are used for the Type I systolic array structure shown in Figure 3. Figure 5 (d) is used in the Type II systolic array structure shown in Figure 4 as a processing element that passes a and d and calculates ah + d + e for inputs a, d and e.

To facilitate the understanding of the systolic array structures shown in FIGS. 3 and 4, the flow of data is shown in Table 1 below.

TABLE 1

In order to configure the three-level wavelet analysis filter by the one-level wavelet analysis filter as described above, three processing element arrays must be connected as shown in FIG.

6 shows a systolic array structure for 3-level DWT calculation.

In FIG. 6 the input is a _n and the high frequency output u _n of the first level is output and the low frequency output v _n is input to the second array of processing elements. In this manner, the low frequency and high frequency outputs y _n and z _n are output from the third processing element.

7 shows a systolic array structure for one-level composite wavelet calculation.

The first level synthesis wavelet filter calculation is calculated as shown in Equation (4) below.

In the systolic array structure shown in FIG. 7, g _m u _{2n + 1} and h _m v _{2n + 1} , n≥0, do not need to be calculated as in the one-level synthesis wavelet filter calculation process, as in the analysis process. Calculate only _m u _2n and h _m v _2n .

Low and high frequency filter coefficients were stored in the processing element and the inputs were left.

That is, only the Type I systolic array structure for the level analysis wavelet calculation shown in FIG. 3 differs from the input coefficients and the filter coefficient values stored in the processing elements.

As in the three-level wavelet analysis process, the three-level wavelet synthesis process must connect three processing elements as shown in FIG.

The performance of DWT calculation by the systolic array structure presented by the present invention and the conventional systolic array structure was compared and analyzed in Table 2.

TABLE 2

In Table 2, N represents the sequence size, L represents the number of levels, and M represents the number of filter taps.

In the results of the performance analysis shown in Table 2, while the systolic array structure according to the present invention requires Nm multiplication processing elements, the structure of Lee et al. And the structure of Vishwanath et al. Of the conventional structure are Nm or m. Multiplication processing elements are required.

Parhi and Nishitani have the best performance in terms of computation time and the number of processing elements required, but the disadvantage is that memory blocks are required. That is, the systolic array structure according to the present invention has the advantage that no additional hardware such as a control unit, a memory unit, or a routing network required in the conventional structure is required.

Claims (1)

Given the transfer function of the high frequency wavelet filter G and the low frequency wavelet filter H for the discrete wavelet transform, Input sequence low-frequency output sequence with respect to a _n v _n, the high-frequency output sequence u _n discrete waves in the systolic array structure for the wavelet transform, the low-frequency wavelet filter coefficients (h _n) and the high frequency wavelet filter coefficients (g for outputting _n ) is stored and constitutes an array of processing elements PE for outputting a, ah _n + d + e, ah _n for inputs a, b, and e, with even components (a _2n ) of the input sequence a _n H ₀ , g ₀ is the input (a) of the processing element stored, the odd component (a _{2n + 1} ) of the input sequence a _n is h ₁ , input (a) of the processing element stored g ₁ , h _2n, g _2n of the output of the stored processing element a is of the following steps: h _2n, g _2n is the input (a) of the stored processing _{elements, h 2n + 1, g 2n} + 1 of which the output of the processing element is stored a Is the input of the processing element where h _{2n + 1} and g _{2n + 1} are stored (a) is, h _2n, g _2n is stored during the output of the processing element ah _n + d + e is the input (d) of processing elements of h _2n, g _2n previous step are stored, h _{2n + 1,} In the output of the processing element with g _{2n + 1} stored, ah _n + d + e becomes the input (d) of the processing element with h _{2n + 1} and g _{2n + 1} stored in the previous step, and h _{2n + 1} , g _{2n + one} of the outputs (c) a low-frequency output sequence of the processing elements is h _0, g ₀ is stored by as the of the a-h _n outputs of the processing element is stored is such that the input (e) of processing elements is h _2n, g _2n stored Systolic array structure for discrete wavelet transform, characterized in that the even component (v _2n ), and the odd component (u _2n ) of the high frequency output sequence alternately output.