KR100230381B1 - Pt layer etching method in semiconductor processing - Google Patents
Pt layer etching method in semiconductor processing Download PDFInfo
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- KR100230381B1 KR100230381B1 KR1019960055051A KR19960055051A KR100230381B1 KR 100230381 B1 KR100230381 B1 KR 100230381B1 KR 1019960055051 A KR1019960055051 A KR 1019960055051A KR 19960055051 A KR19960055051 A KR 19960055051A KR 100230381 B1 KR100230381 B1 KR 100230381B1
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- 238000005530 etching Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims abstract description 22
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims abstract description 154
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000001678 irradiating effect Effects 0.000 claims abstract description 6
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052801 chlorine Inorganic materials 0.000 claims abstract description 5
- 239000000460 chlorine Substances 0.000 claims abstract description 5
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 230000008018 melting Effects 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims description 3
- 229910052736 halogen Inorganic materials 0.000 abstract description 5
- 150000002367 halogens Chemical class 0.000 abstract description 5
- 238000004544 sputter deposition Methods 0.000 abstract description 5
- 230000003213 activating effect Effects 0.000 abstract description 3
- 210000002381 plasma Anatomy 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000006227 byproduct Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
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Abstract
레이저광을 이용하여 백금층을 식각할 수 있는 반도체 장치의 백금막 식각방법에 관하여 개시되어 있다. 이를 위하여 본 발명은, 하부구조가 형성되어 있는 반도체기판상에 순차적으로 적층된 백금막 및 식각마스크로서의 유전막이 있는 반도체 장치를 염소나 불소를 포함하는 플라즈마를 이용하여 백금막을 식각하는 반도체장치의 백금막 식각방법에 있어서, 레이저 입사광을 상기 백금막과 유전막위에 조사하여 백금막의 온도를 조절함으로써 백금막의 식각을 활성화하는 것을 특징으로 하는 반도체장치의 백금막 식각방법을 제공한다. 따라서, 스퍼터링 방법에 의한 백금막의 식각공정에서 레이저 입사광에 의해 할로겐계의 플라즈마를 활성화하고 백금막의 온도를 적절히 조절함으로써, 백금막 하부층과 백금막의 경계면에서 소자의 기능이 퇴화되는 것을 방지할 수 있는 반도체장치의 백금막 식각방법을 구현할 수 있다.A platinum film etching method of a semiconductor device capable of etching a platinum layer using laser light is disclosed. In order to achieve the above object, the present invention provides a semiconductor device having a platinum film sequentially stacked on a semiconductor substrate on which a lower structure is formed and a semiconductor device having a dielectric film as an etch mask, wherein the platinum film is etched using chlorine or fluorine- A method for etching a platinum film of a semiconductor device characterized by activating a platinum film by irradiating a laser beam onto the platinum film and a dielectric film to adjust the temperature of the platinum film in the film etching method. Therefore, in the etching process of the platinum film by the sputtering method, the halogen-based plasma is activated by the laser incident light and the temperature of the platinum film is appropriately controlled so that the function of the device at the interface between the platinum film lower layer and the platinum film can be prevented A platinum film etching method of the device can be implemented.
Description
본 발명은 반도체장치의 제조방법에 관한 것으로서, 특히 레이저광을 이용하여 백금층을 식각할 수 있는 반도체 장치의 백금막 식각방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of etching a platinum film of a semiconductor device capable of etching a platinum layer using laser light.
최근에는, 백금(Pt)-폴리실리콘을 이용한 도전막의 구조가 연구되고 있는데 백금(Pt)-폴리실리콘 구조의 도전막을 형성하면, 저항측면에서 유리하다. 또한, 이러한 도전막을 게이트패턴으로 사용할 경우, 측벽에서의 침해현상을 방지할 수 있으며, 구조를 단순화할 수 있다. 참고로, 텅스텐 폴리사이드 게이트의 저항은 ∼80μΩ·㎝정도이고, 티타늄 폴리사이드 게이트의 저항은 ∼20μΩ·㎝정도이며, 백금- 폴리실리콘 게이트의 저항은 ∼10μΩ·㎝정도이다.Recently, the structure of a conductive film using platinum (Pt) -Polysilicon has been studied, and it is advantageous in terms of resistance when a conductive film of a platinum (Pt) -polysilicon structure is formed. In addition, when such a conductive film is used as a gate pattern, it is possible to prevent the phenomenon of invasion at the side wall, and the structure can be simplified. For reference, the resistance of the tungsten polycide gate is about -80 mu OMEGA. Cm, the resistance of the titanium polycide gate is about -20 mu OMEGA. Cm, and the resistance of the platinum-polysilicon gate is about -10 mu OMEGA.
그러나, 백금을 이용하여 도전막을 형성하고자 하는 경우, 건식식각을 이용한 패턴닝이 매우 어려운 단점이 있다. 이는, 백금이 비반응성 금속이어서 다른 화학물질과 반응하기가 어렵기 때문에 반응성 이온 식각(Reactive Ion Etching) 방법과 같은 건식식각에 의해 쉽게 식각되지 않기 때문이다. 다시 말하면, 반응성 이온 식각공정에서 통상 사용되는 할로겐 원소와 백금 이온과의 반응성이 매우 낮기 때문에 통상의 건식식각 방법으로는 패턴닝이 어렵다.However, when a conductive film is to be formed using platinum, patterning using dry etching is very difficult. This is because platinum is a non-reactive metal and thus difficult to react with other chemicals, so that it is not easily etched by dry etching such as a reactive ion etching method. In other words, since the reactivity between a halogen element and a platinum ion which are usually used in a reactive ion etching process is very low, patterning is difficult with a conventional dry etching method.
따라서, 백금으로 형성된 도전막은 주로, 높은 이온 에너지를 이용한 스퍼터링 방법을 이용하여 식각하고 있다. 그러나, 이와 같이 이온 스퍼터링을 이용하여 백금의 도전막을 식각하는 경우에는, 에칭 잔류물(residue)이 형성되는 문제점과 이로 인해 백금전극 측벽이 경사지는 문제점이 발생한다. 또한 낮은 식각율 개선하기 위하여 불소계와 염소계의 플라즈마를 사용하는 경우, 그에 따른 반응부산물인, 백금(Pt) 혹은 약각의 PtFx 나 PtClx가 식각될 표면에 퇴적된다. 여기서, PtFx 나 PtClx 계통의 반응부산물은 기판의 온도가 500∼700℃의 고온에 이르면 휘발성물질로 변한다. 따라서, 상기한 PtFx 나 PtClx의 표면 퇴적을 방지하려면 기판을 500∼700℃로 가열하여야 한다. 그러나, 이러한 기판의 온도상승은 소자가 형성된 활성영역과 백금막의 경계면에서 소자의 기능이 퇴화(degradation)되는 문제가 발생하고 있는 실정이다.Therefore, the conductive film formed of platinum is mainly etched using a sputtering method using high ion energy. However, when the conductive film of platinum is etched using the ion sputtering as described above, etching residues are formed and the side walls of the platinum electrode are inclined. When fluorine and chlorine plasma are used to improve the etching rate, platinum (Pt) or weak PtFx or PtClx, which is a by-product of the reaction, is deposited on the surface to be etched. Here, the reaction by-products of the PtFx and PtClx systems change into volatile substances when the temperature of the substrate reaches a high temperature of 500 to 700 占 폚. Therefore, in order to prevent deposition of the PtFx or PtClx on the surface, the substrate should be heated to 500 to 700 占 폚. However, the temperature rise of such a substrate has a problem that the function of the device is degraded at the interface between the active region where the device is formed and the platinum film.
본 발명이 이루고자 하는 기술적 과제는 스퍼터링 방법에 의한 백금막의 식각공정에서 식각율을 높이기 위하여 할로겐계의 플라즈마를 활성화하여야 하고 이를 위하여 기판을 고온으로 올려야 하는데 이에 수반하여 발생되는 소자의 기능퇴화를 방지할 수 있는 반도체장치의 백금막 식각방법을 제공하는데 있다.In order to increase the etching rate in the etching process of the platinum film by the sputtering method, the halogen-based plasma must be activated and the substrate must be raised to a high temperature, thereby preventing functional deterioration of the device And a method for etching a platinum film of a semiconductor device.
도 1은 본 발명의 바람직한 실시예를 설명하기 위한 도면으로 백금막이 형성된 반도체기판상에 레이저 입사광을 적용하는 것을 설명하기 위한 단면도이다.FIG. 1 is a cross-sectional view for explaining application of laser incident light onto a semiconductor substrate on which a platinum film is formed, for explaining a preferred embodiment of the present invention.
도 2는 본 발명의 바람직한 실시예를 설명하기 위한 도면으로 레이저 입사광의 펄스 형태를 설명하기 위한 그래프이다.FIG. 2 is a graph for explaining pulse shapes of laser incident light according to a preferred embodiment of the present invention. Referring to FIG.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
100: 반도체 기판 102: 백금막100: semiconductor substrate 102: platinum film
104: 산화막 106: 레이저 입사광104: oxide film 106: laser incident light
108: 반사광108: Reflected light
상기의 기술적 과제를 달성하기 위하여 본 발명은, 하부구조가 형성되어 있는 반도체기판상에 순차적으로 적층된 백금막 및 식각마스크로서의 유전막이 있는 반도체 장치를 염소나 불소를 포함하는 플라즈마를 이용하여 백금막을 식각하는 반도체장치의 백금막 식각방법에 있어서, 레이저 입사광을 상기 백금막과 유전막위에 조사하여 백금막의 온도를 조절함으로써 백금막의 식각을 활성화하는 것을 특징으로 하는 반도체장치의 백금막 식각방법을 제공한다.According to an aspect of the present invention, there is provided a semiconductor device including a platinum film sequentially stacked on a semiconductor substrate having a lower structure and a dielectric film serving as an etch mask, the platinum film using chlorine or fluorine- There is provided a method of etching a platinum film of a semiconductor device characterized by activating a platinum film by irradiating a laser beam onto the platinum film and a dielectric film to control the temperature of the platinum film.
바람직하게는, 상기 유전막은 레이저 입사광을 투과할 수 있는 산화막인 것이 적합하다.Preferably, the dielectric film is an oxide film capable of transmitting laser incident light.
상기 레이저 입사광은 인가하는 시간과 펄스폭과, 강도의 세기(Intensity)에 의하여 백금막 표면의 온도를 조절하는 것이 바람직하다.It is preferable that the temperature of the platinum film surface is controlled by the time, the pulse width, and the intensity of the laser incident light.
바람직하게는, 상기 레이저 입사광을 조사하여 백금막의 온도를 조절하는 범위는 상온에서부터 백금막의 융해점까지인 것이 적합하다.Preferably, the range of controlling the temperature of the platinum film by irradiating the laser incident light is suitably from the room temperature to the melting point of the platinum film.
따라서, 레이저 입사광을 통하여 할로겐계의 플라즈마를 활성화시키고, 백금막의 표면의 온도를 조절하여 소자가 열화되는 것을 방지할 수 있는 반도체장치의 백금막 식각방법을 실현할 수 있다.Therefore, it is possible to realize a method of etching a platinum film of a semiconductor device capable of activating a halogen-based plasma through laser incident light and preventing the device from deteriorating by controlling the temperature of the surface of the platinum film.
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 2는 본 발명의 바람직한 실시예를 설명하기 위한 도면이다.1 and 2 are views for explaining a preferred embodiment of the present invention.
도 1을 참조하면, 소자를 포함하는 하부구조가 형성된 반도체기판(100)상에 백금막(102)이 적층되어 있고, 그 상부에 식각마스크의 역할을 하는 유전막, 즉 산화막(104)이 형성되어 있다. 종래기술에 있어서는 상기 백금막(102)과 산화막(104)의 표면에 불소계와 염소계의 플라즈마, 예컨대 PtFx 나 PtClx를 퇴적하고 기판의 온도를 500∼700℃의 고온으로 상승하여야만 백금막을 원하는 정도로 식각할 수 있었다. 또한, 그로 인한 소자를 포함하는 하부구조가 형성된 반도체기판(100)과 백금막(102)의 경계면에서 소자의 퇴화문제가 지적되었다. 하지만 본 발명에서는, 상기 기판의 온도를 500∼700℃의 고온으로 상승하는 것 대신에 레이저 입사광을 조사함으로써 백금막의 온도를 선택적으로 상승시켜 백금막의 식각을 가능하게 한다.Referring to FIG. 1, a platinum film 102 is stacked on a semiconductor substrate 100 on which a lower structure including a device is formed, and a dielectric film serving as an etch mask, that is, an oxide film 104 is formed on the platinum film 102 have. In the prior art, fluorine-based and chlorine-based plasmas such as PtFx and PtClx are deposited on the surfaces of the platinum film 102 and the oxide film 104 and the platinum film is etched to a desired extent only by raising the substrate temperature to a high temperature of 500 to 700 ° C I could. In addition, there has been pointed out a problem of device degradation at the interface between the semiconductor substrate 100 and the platinum film 102 on which the underlying structure including the resulting device is formed. However, in the present invention, instead of raising the temperature of the substrate to a high temperature of 500 to 700 DEG C, the temperature of the platinum film is selectively raised by irradiating the laser with incident light, thereby enabling the platinum film to be etched.
상세히 설명하면, 상기의 결과물상에 연속모드 혹은 펄스모드의 레이저 입사광(106)을 조사한다. 이때, 레이저 입사광(106)의 일부는 백금막(102)에 흡수되어 반도체기판(100)의 온도를 상승시키며, 일부는 산화막(104)이 레이저 입사광(106)을 투과시키는 투명한 막의 성질을 갖기 때문에 산화막(104)을 통과하여 벡금막(102)의 표면에서 반사광(108)의 형태로 반사된다.In more detail, laser incident light 106 of a continuous mode or a pulse mode is irradiated onto the resultant product. At this time, a part of the laser incident light 106 is absorbed by the platinum film 102 to raise the temperature of the semiconductor substrate 100, and a part thereof has a property of a transparent film through which the laser incident light 106 is transmitted through the oxide film 104 Passes through the oxide film 104, and is reflected from the surface of the backing film 102 in the form of reflected light 108.
도 2를 참조하면, 상기 도 1의 백금막과 산화막의 표면에 인가하는 레이저 입사광이 펄스 형태인 경우, 그 펄스파형을 도시한 그래프이다. 여기서, 이러한 펄스파형을 조작함으로써 백금막의 표면의 온도를 조절하는 것이 가능해진다.Referring to FIG. 2, there is shown a graph of the pulse waveform when the laser incident light applied to the surface of the platinum film and the oxide film of FIG. 1 is in the form of a pulse. Here, by manipulating such a pulse waveform, it becomes possible to control the temperature of the surface of the platinum film.
상세히 설명하면, 백금막의 온도가 상승하게 되는 원인은 여기된 레이저 입사광으로부터의 에너지형태의 열이 그 근원(source)인데, 이는 펄스주기(110), 펄스폭(112), 강도의 세기(114)를 조작하면 백금막의 온도의 범위를 광범위하게 조절하는 것이 가능하다. 즉, 펄스폭(112)을 길게 하는 경우에는 백금막의 표면의 온도상승을 가속화할 수 있다. 또한, 펄스폭(112)을 일정하게 유지한 상태에서 펄스의 주기(110)를 상대적으로 길게 하면 백금막 표면에 조사되는 레이저 입사광의 양을 감소시켜서 온도를 낮출 수 있는 수단이 된다. 마지막으로, 펄스폭(112)과 주기(110)를 일정하게 한 상태에서 레이저 입사광의 강도를 세기(114)를 낮추거나 높이면 백금막 표면에 조사되는 레이저 입사광의 양을 감소 또는 증가시켜서 백금막 표면의 온도 조절이 가능해진다.In detail, the cause of the temperature rise of the platinum film is the source of the energy type heat from the excited laser incident light, which is the pulse period 110, the pulse width 112, the intensity 114, It is possible to widely control the temperature range of the platinum film. That is, when the pulse width 112 is made long, the temperature rise of the surface of the platinum film can be accelerated. In addition, if the pulse period (110) is relatively long in a state where the pulse width 112 is kept constant, the amount of laser incident light irradiated on the surface of the platinum film is reduced to lower the temperature. Finally, when the strength 114 of the laser incident light is lowered or increased in a state where the pulse width 112 and the period 110 are kept constant, the amount of laser incident light irradiated on the platinum film surface is decreased or increased, It is possible to adjust the temperature of the liquid.
이러한 온도조절 수단을 적절히 활용함으로써, 백금막의 온도를 상온에서 백금막의 융해점까지 조절이 가능한 상태에서 식각을 진행할 수 있기 때문에 종래에 있어서, 소자를 포함한 하부구조가 형성된 반도체기판과 백금막의 경계면에서 열에 의하여 소자가 퇴화되는 문제를 효과적으로 해결할 수 있다.By appropriately utilizing such a temperature control means, etching can be carried out in a state where the temperature of the platinum film can be adjusted from the room temperature to the melting point of the platinum film. Therefore, conventionally, at the interface between the semiconductor substrate and the platinum film, It is possible to effectively solve the problem of degeneration of the device.
본 발명은 상기한 실시예에 한정되지 않으며, 본 발명이 속한 기술적 사상 내에서 당 분야의 통상의 지식을 가진 자에 의해 많은 변형이 가능함은 명백하다.It will be apparent to those skilled in the art that the present invention is not limited to the above-described embodiment, and many modifications may be made by those skilled in the art without departing from the spirit and scope of the present invention.
따라서, 상술한 본 발명에 따르면, 스퍼터링 방법에 의한 백금막의 식각공정에서 레이저 입사광에 의해 할로겐계의 플라즈마를 활성화하고 백금막의 온도를 적절히 조절함으로써, 백금막 하부층과 백금막의 경계면에서 소자의 기능이 퇴화되는 것을 방지할 수 있는 반도체장치의 백금막 식각방법을 구현할 수 있다.Therefore, according to the present invention described above, in the etching process of the platinum film by the sputtering method, the halogen-based plasma is activated by the laser incident light and the temperature of the platinum film is appropriately controlled, whereby the function of the device at the interface between the platinum film lower layer and the platinum film is degraded A platinum film etching method of a semiconductor device can be realized.
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