KR100228303B1 - Apparatus and method for atm switching - Google Patents

Abstract

The N * N large-capacity ATM switch device is composed of log ₂ (N / n) MUX switch stages, each stage is composed of N / n MUX switches, and the final switch stage is composed of n * n output switches. N input ports are connected to the MUX switch groups t (1,1) and t (1,2) of the first stage, 1≤A≤log ₂ (N / n) -1, and 1≤C≤2 C second MUX switch of stage a with a value of ^a group t (a, C) of the output ports are respectively t (a + 1,2C-1) and t (a + 1,2C) input port of the copying machine via the The output ports of the final MUX switch group t (log ₂ (N / n), C) are connected to the input ports of the n * n output switches.

Description

ATM switch device and method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch apparatus and method for a broadband integrated information communication network, and more particularly to an ATM switch apparatus and method.

Asynchronous Transfer Mode (ATM) is a popular technology for realizing a Broadband Integrated Service Digital Network (BISDN). A small LAN (Local Area Network) switch using the ATM technology is being developed, and various tests for use as a communication infrastructure are also being conducted in each country. One of the key technologies required for such an ATM network is switching technology. Therefore, many researches are currently being conducted to develop the ATM switch, and many countries and companies have developed various types of ATM switches and applied them to commercial or systems.

The ATM switch is basically composed of VLSI chips, and the capacity of the switch is limited due to the limitations of VLSI technology and packages. The main physical constraints here are the number of transistors that can fit into a VLSI chip, thermal issues, and the number of pins that can be connected to the chip. Therefore, the size of an ATM switch that can be implemented with a current chip is about 8 * 8 or 16 * 16. However, as the use of ATM switch networks increases, the demand for large-capacity ATM switches is increasing. However, since it is impossible to implement a large-capacity switch on one chip, a large-scale ATM switch requires a modular expansion using a small-capacity ATM switch element.

In general, the expansion of the ATM switch device is basically making a structure for expansion using a 2 * 2 switch. The expansion methods of the conventional switch device must continue to develop new boards for continuous expansion, and the number of inputs that can be received from one board is limited due to the limitation of the connector, and thus continuous expansion is impossible. Since a conventional switch device takes the form of an input buffer, a method for resolving collision at the output is additionally required, and a basic maximum transmission rate due to HOL (Head of Line) blocking is small.

In order to solve such flexibility problem of expansion, it is necessary to have a structure that can be expanded to a large capacity by using only one board, and this board adopts an output buffer type switch to block and output HOL (Head of Line). It should have a structure that can resolve the collision on the side, and the maximum transmission rate should be close to 1 so that the performance improvement should be possible.

Accordingly, an object of the present invention is to provide a large capacity switch device and method that can be easily expanded by connecting switches in a board unit.

Another object of the present invention is to provide an apparatus and method that can be extended to a large-capacity switch by connecting the switches that can solve the collision of the head of the line blocking and the output side by adopting the output buffer type structure.

It is still another object of the present invention to provide an apparatus and method which can be expanded to a N * N sized large capacity switch by using a 2n * n MUX switch and an n * n output switch.

In order to achieve the above object, the present invention provides a N * N high-capacity ATM switch device comprising log ₂ (N / n) MUX switch stages, and each stage includes N / n MUX switches. The stage consists of n * n output switches, the N input ports are connected to the MUX switch groups t (1,1) and t (1,2) of the first stage, and 1≤A≤log ₂ (N / n ) The output ports of the C-th MUX switch groups t (A, C) of the A stage with a value of 1≤C≤2 ^A pass through the copier, respectively t (A + 1,2C-1) and t (A It is connected to the input ports of +1, 2C, characterized in that the output ports of the final MUX switch group t (log ₂ (N / n), C) is connected to the input ports of the n * n output switches .

1 is a diagram showing the structure of a 2n * n MUX switch

Fig. 2 is a diagram showing the structure of a 2n * 2n switch.

3 is a view for explaining a method for expanding to a large capacity switch according to an embodiment of the present invention;

4A and 4B are views showing the configuration of an N * N switch device implemented using a 2n * n MUX switch and an n * n output switch.

5A and 5B are diagrams showing the configuration of a device implementing an N * N switch using a 2n * n MUX switch and an n * n output switch.

Fig. 6 is a diagram showing the configuration of a 128 * 128 switch device implemented using a 32 * 16 MUX switch and a 16 * 16 output switch.

FIG. 7 is a diagram schematically showing the configuration of a 128 * 128 switch device implemented using a 32 * 16 MUX switch and a 16 * 16 output switch.

8 is a flowchart illustrating a process of self-routing by analyzing a routing tag of a cell in a high-capacity switch device according to an embodiment of the present invention.

In an embodiment of the present invention, a 2n * n MUX switch and an n * n output switch are used to implement a large capacity switch. At this time, a multi-stage distribution network is created using the 2n * n MUX switch, and the inputted cell is output to the n * n output switch of the final stage, and the n * n output switch is a cell input from the distribution network. It is responsible for transmitting to the final destination. In this case, the n * n output switch may use any type of switch.

By implementing the large-capacity switch as described above, we can obtain various advantages such as equal use of intermediate nodes, no need for setting a cell routing path, and improved performance.

First, the structure of the 2n * n MUX switch will be described with reference to FIG. 1. The 2n * n MUX switch includes a port selector part 110, a first in first out part 120, and an output part 130.

The header of the ATM cell processed by the switch according to the embodiment of the present invention has a structure as shown in Table 1 below.

TABLE 1

Routing Tag (N / n) + k Bits VPI VPI VCI VCI VCI PTI CLP HEC Pay load

In Table 1, the remaining configuration except for the routing tag region is a configuration of a general ATM cell. Here, VPI (Virtual Path Identifier) is an area for storing virtual path identification information, VCI (Virtual Channel Identifier) is an area for storing virtual channel identification information, and PTI (Payload Type Identifier) is for storing payload type identification information. Cell Loss Priority (CLP) is an area for storing loss priority information of a cell, and HEC (Header Error Control) is an area for storing header error control information. The above information becomes header information of an ATM cell, and payload information is carried in the remaining areas of the cell.

The ATM cell used in the embodiment of the present invention further includes an area for storing a routing tag, which is information for self-routing a cell, in the structure of a general ATM cell. The routing tag is additionally added to the front of the cell header for cell transmission in the N * N large capacity switch device, and the switch selects and transmits an output port to which the cell is to be transmitted using the routing tag.

The operation of a MUX switch for switching a cell to which a switch as shown in FIG. 1 is input using the structure of an ATM cell as shown in Table 1 will be described.

The 2n * n MUX switch inputs 2n cells, and each input port is inputted by a cell in the form of a valid cell or dummy cell at every cell time. As described above, 2n cells received through the input port are selected by the port selector 110 and transferred to the bag 120. The port selector 110 looks at a routing tag in the header of each cell and checks whether each cell is a cell to be delivered to the packer 120. If it is determined that the cell is to be delivered in the inspection process as described above, the port selection unit 110 transfers the corresponding cell to the bag unit 120, otherwise the input cell is discarded. In this case, since all cells output from the 2n * n MUX switch are transferred to the same n * n output buffer, it may be output to any of the n outputs. Therefore, the routing tag required by the port selector 110 is 1 bit is sufficient.

The bag unit 120 storing the cells output from the port selector 110 is composed of all 2n packets, and can store 2n cells at the same time. This is to store all cells without cell loss even when all 2n cells inputted are outputted from the port selector 110. And since the 2n blisters operate as a shared blister, all the blisters are seen as one blister.

The output unit 130 reads n cells at the cell unit 120 every cell time and outputs the outputted cells to the output switch. The output unit 130 sequentially reads n cells in a round robin manner from 2n packets and outputs them to the output port side. When the number of cells existing in the bag 120 is smaller than n, the output unit 130 reads out and outputs as many cells as there exist, and outputs dummy cells to the remaining output ports. In this case, since the order in which the cells are written from the port selector 110 to the wrapper 120 and the order of reading the cells from the output unit 130 are the same, the order of the cells is not scattered.

2 shows a 2n * 2n switch structure. The 2n * 2n switch having the structure as shown in FIG. 2 is a switch having a minimum size that can be implemented by using a 2n * n MUX switch and an n * n output switch. The 2n * 2n switch is composed of two copiers CP1 to CP2, 2n * n MUX switches MS1 to MS2, and n * n output switches OS1 to OS2. '

Referring to FIG. 2, the copiers CP1 to CP2 respectively connected to the front ends of the MUX switches MS1 to MS2 copy the input 0 to n-1 cells and the n to 2n-1 cells, respectively, and then the MUX switches MS1 to MS2. Output to Accordingly, the 2n * n MUX switch MS1 inputs all 2n cells, and selects only the cells to be output to the output ports from port 0 to port n-1, and outputs them to the n * n output switch OS1. The 2n * n MUX switch MS2 inputs all 2n cells, and selects only the cells to be output from the dual port n to the port 2n-1 to the n * n output switch OS2. The n * n output switch OS1-OS2 inputs n input cells, respectively, and transmits them to the desired output port.

Therefore, the n * n output switch OS1-OS2 may use any type of switch, and the 2n * n MUX switch MS1-MS2 selects and transmits an input cell in a group form according to the output port to which each switch should transfer. Done. That is, in the case of the 2n * 2n switch, the 2n * n MUX switch MS1 selects a cell to be output from port 0 to n-1 and transfers it to the output switch OS1, and the 2n * n2 MUX switch MS2 is connected to the port n. Select the cell to be output as 2n-1 and transfer it to the output switch OS2. Therefore, in this case, only 1 bit is sufficient for the number of routing tags required for cell selection in the 2n * n MUX switches MS1-MS2.

When a large capacity N * N switch is implemented using the 2n * 2n switch as shown in FIG. 2, the 2n * n MUX switch can be continuously connected to the front end. 3 illustrates a process of implementing a 4n * 4n switch and an 8n * 8n switch by extending a small 2n * 2n switch.

As shown in FIG. 3, for continuous expansion, the 2n * n MUX switch may be continuously connected to the front end. Thus, in order to finally implement an N * N size switch, log ₂ (N / n) stages are required, and each stage requires (N / n) switches. The first stage and the log ₂ (N / n) stage consist of 2n * n MUX switches, and the last stage consists of n * n output switches. Therefore, a total N * N large capacity switch requires a total of (N / n) * log ₂ (N / n) 2n * n MUX switches and (N / n) n * n output switches.

4A and 4B illustrate a method of configuring an N * N mass switch using a 2n * n MUX switch and an n * n output switch. In the N * N switch having the configuration of FIGS. 4A and 4B, the switches for n * n outputs may be used without any type of switches, and the 2n * n MUX switches have an output buffered switch structure as shown in FIG. At this time, each MUX switch sees the routing tag of the cell according to the position of each switch among 2n inputs, and selects and outputs only the cells to be transmitted to the n output ports.

5A and 5B show the same configuration as that of FIGS. 4A and 4B in a simplified structure of the N * N switch device. 5A and 5B, t (A, C) means a stage number of a MUX switch corresponding to "A", and "C" means a number of a corresponding MUX switch in a corresponding stage.

In the N * N switch, t (A, C) is composed of N / 2nA 2n * n MUX switches, and inputs N / A cells to output N / 2A cells. And C at each stage has an integer value from 1 to 2 ^A. The cells output from t (A, C) are copied by the copiers and input into two switch groups, t (A + 1,2C-1) and t (A + 1,2C). And t (1,1) and t (1,2) of the first stage input all N cells. When the input and output of the switch group are connected in this way, the cells output from t (1,1) are transferred to t (2,1) and t (2,2), and from t (1,2) The output cells are delivered to t (2,3) and t (2,4). Similarly, the output of t (2,1) is passed to t (3,1) and t (3,2), and the output of t (2,2) is t (3,3) and t (3,4) ), The output of t (2,3) is delivered to t (3,5) and t (3,6), and the output of t (2,4) is t (3,7) and t Is passed to (3,8).

If the MUX switches are connected in the same manner as above, t (log ₂ (N / n), C) becomes one 2n * n MUX switch in the log ₂ (N / n) stage, and these MUX switches At each end, the n * n output switch is connected. By continuously connecting the MUX switches in the same manner as above, and connecting a copier to the front of these MUX switches, it is possible to implement an N * N scale switch as shown in FIGS. 4A and 4B.

An implementation method of the switch having the above configuration is as follows.

First, cells input through N input ports are connected to be input to t (1,1) and t (1,2), which are the first MUX switches. [N port input → input t (1,1), t (1,2)].

Secondly, the connection of the MUX switches from the second stage to the last stage, the output of t (A, C) of the corresponding stage is input of t (A + 1,2C-1), t (A + 1,2C). Connect so that [output of t (A, C) → input of t (A + 1,2C-1), t (A + 1,2C), where 1≤A≤log ₂ (N / n) -1, 1≤C ≤ 2 ^A ].

Thirdly, the output of t (log ₂ (N / n), C) is the input of the n * n output switch. [output of t (log ₂ (N / n), C) → input to n * n switch, where 1 ≦ C ≦ N / n).

Look at the implementation of the switch device implemented according to an embodiment of the present invention in the same way as described above. FIG. 6 shows the configuration of a 128 * 128 switch implemented using a 32 * 16 MUX switch and a 16 * 16 output switch. In the case of the switch as shown in FIG. 6, n = 16 and N = 128. FIG. 7 is a diagram schematically showing the configuration of a 128 * 128 switch as shown in FIG.

Looking at the input and output relationship of each MUX switch in the 128 * 128 switch having the configuration as shown in Figure 6 and 7 as follows.

1.128 port input → t (1,1), t (1,2) input

2. t (1,1) output → input to t (2,1), t (2,2)

3. t (1,2) output → input to t (2,3), t (2,4)

4. t (2,1) output → input to t (3,1), t (3,2)

5. t (2,2) output → input to t (3,3), t (3,4)

6. t (2,3) output → input to t (3,5), t (3,6)

7. t (2,4) output → input to t (3,7), t (3,8)

8. t (3,1) output → input to the first 16 * 16 output switch

9. t (3,2) output → input to the second 16 * 16 output switch

10. t (3,3) output → input to the third 16 * 16 output switch

11. t (3,4) output → input to the fourth 16 * 16 output switch

12. t (3,5) output → input to the fifth 16 * 16 output switch

13. t (3,6) output → input to the sixth 16 * 16 output switch

14. t (3,7) output → input to the seventh 16 * 16 output switch

15. t (3,8) output → input to the switch for the eighth 16 * 16 output

In FIG. 6, dotted lines indicate MUX switches belonging to t (A, C) of FIG. 7. Here, the number of switches belonging to t (A, C) is N / 2nA = 128 / (2 * 16 * A) = 4 / A. Therefore, t (1,1) and t (1,2) consist of four 32 * 16 MUX switches, t (2,1), t (2,2), t (2,3), t (2,4) consists of two 32 * 16 MUX switches, t (3,1), t (3,2), t (3,3), t (3,4), t (3, 5), t (3,6), t (3,7) and t (3,8) consist of one 32 * 16 MUX switch, respectively.

In order to transmit a cell in an N * N switch extended to the above structure, in the embodiment of the present invention has a cell structure as shown in Table 1 above. As shown in Table 1, the N * N switch adds a routing tag to the cell header for cell transmission, and switches the MUX switches to the corresponding output port by analyzing the routing tag of the cell header. will be. In the case of N * N switch, the number of bits of the routing tag is N / n bit for routing in the 2n * n MUX switch and k bit for outputting the cell to the port desired by the cell in the n * n output switch. Add up. Therefore, the number of bits of the routing tag required in the N * N switch is (N / n) + k bits.

Here, look at the cell routing operation of the N * N switch implemented in accordance with an embodiment of the present invention.

When a cell having a structure as shown in Table 1 is input, each of the MUX switches selects and transmits a port to which a cell is output by using a routing tag of the input cell. At this time, the number of bits of the required routing tag becomes (N / n) + k. Here, (N / n) represents the number of bits of the routing tag required in the MUX switches, and k represents the number of bits of the routing tag required in the switches for n * n outputs.

In the N * N large-capacity switch as shown in FIG. 4, the routing tag of the (N / n) bit becomes a bit representing each output group. In this case, the bit structure of the routing tag is configured as shown in Table 2 below.

TABLE 2

One 2 3 4 ­­­­­­ x x + 1 ­­­­­­ N / n-2 N / n-1 N / n ? ? ? ? ? ? ? ? ?

In Table 2, "x" represents an x-th routing tag and represents a cell output to an output port of (x-1) n to xn-1. "?" Is 0 or 1, and if the value under the xth routing tag is 0, it means that this cell is output to one or several of the output ports of (x-1) n to xn-1, and 1 If it means that the cell is not output.

In the routing tag as shown in <Table 2>, the first bit represents an output group of 0 to n-1, the xth bit represents an output group of (x-1) n to xn-1, and (N / The n) th bit represents an output group of Nn to N-1. Therefore, if the value of the xth routing tag bit is "0", it means that the cell should be transmitted to one or several output ports of (x-1) n ~ xn-1. This means that it should not be sent to the output port. In this case, multicasting and broadcasting may be performed by writing "0" to N / n routing tag bits so that each cell can be delivered to a desired number of outputs. In other words, if you want to output cells to all output ports, set all (N / n) routing tag bits to "0" and finally make the cells output to all output ports from the n * n output switch. .

In the N * N switch structure as shown in FIG. 4, a cell group to be passed by each switch group is different. In the case of t (1,1), the cell to be output to the upper N / 2 (0 to (N / 2) -1) port is output to the output port, and in the case of t (1,2), the lower N / 2 Outputs the cell to be output from the (N / 2 to N-1) port to the output port. In the case of t (2,1), the cell to be output to the upper N / 4 (0 to (N / 4) -1) port is output to the output port, and in the case of t (2,2), the upper N Outputs cells to be output from the / 4 (N / 4 ~ (N / 2) -1) port to the output port, and in the case of t (2,3), the upper N / 4 (N / 2 ~ (3N / 4) ) -1) Outputs the cell to be output to the port to the output port, and in case of t (2,4), outputs the cell to be output to the upper N / 4 (3N / 4 to N-1) port to the output port do. That is, t (A, C) may output a cell to be output to an output port of N (C-1) / 2 ^A to NC / 2 ^A- 1.

Since the xth bit of the routing tag represents the (x-1) n to xn-1 output ports, x = {N (C-1) at N (C-1) / 2 ^A = (x-1) n. N (C-1) / 2 ^A to NC / 2 ^A -1 output from x = NC / (n "2 ^A ) at / (n" 2 ^A )} + 1 and NC / 2 ^A -1 = xn-1 The port is represented by the x th routing tag bits that satisfy {N (C-1) / (n "2 ^A )} + 1≤x≤NC / (n" 2 ^A ) where x is an integer. Therefore, the t (A, C) is the x th routing tag bit satisfying {N (C-1) / (n "2 ^A )} + 1≤x≤NC / (n" 2 ^A ) (x is an integer) If either value is "0" (t (x) = 0), the cell is output.

Therefore, in a device extended to an N * N switch using the 2n * n MUX switch as shown in FIG. 4, when t cells with routing tags as shown in Table 2 are input, each t (A, C) is a cell. The process of determining whether to transmit to the output port side is described with reference to FIG. In FIG. 8, "t" represents a MUX switch group, "A" represents a MUX switch stage number of an N * N switch, and "C" represents a number of a MUX switch located at a corresponding stage. "N" represents the number of input / output ports of the switch, n represents the number of input / output ports of the output switch, and x represents the current routing tag bit.

Referring to FIG. 8, when routing starts, first, in step 811, x = 1 is designated as the first routing tag bit. In step 813, it is checked whether x is greater than N / n (x ≦ N / n). In this case, if x is not greater than N / n, since the last Leitung tag bit is not checked, N (C-1) / (n2 ^A ) + 1 ≦ x ≦ NC / Check if n2 ^A is satisfied. If this is not satisfied, x is incremented to designate the next routing tag bit in step 825. However, if the corresponding conditions are satisfied in steps 815 and 817, it is checked in step 819 whether the value f (x) of the corresponding x th routing tag bit is 0. If f (x) is 0, the process proceeds to step 821 to transmit the corresponding cell. Otherwise, the process proceeds to step 825.

As described above, each MUX switch group t determines whether or not to transmit the input cell by performing the same process as shown in FIG. 8 according to the switch stage number A where it is located and the switch number C in the corresponding stage number.

Referring to the self-routing operation of the MUX switches as described above with reference to FIG. 6, since N = 16 and N = 128, the number of routing tag bits is N / n = 8. Since the x th bit represents an output port group of (x-1) n to xn-1, the output port group represented by each bit is as follows.

1) Bit 1: 0 ~ 15

2) Bit 2: 16 ~ 31

3) Bit 3: 32 ~ 47

4) Bit 4: 48 ~ 63

5) Bit 5: 64 ~ 79

6) Bit 6: 80 ~ 95

7) Bit 7: 96 ~ 111

8) Bit 8: 112 ~ 127

And the cell that t (A, C) will output is between (N (C-1) / n2 ^A ) + 1 = 8 (C-1) / 2 ^A +1 and NC / n2 ^A = 8C / 2 ^A One of the routing tag bits is a cell.

1): 8 (C-1) / 2 ^A + 1 = 1, 8C / 2 ^A = 4 → cell in which one of the 1st to 4th bits of the routing tag is 0

2): 8 (C-1) / 2 ^A + 1 = 5, 8C / 2 ^A = 8 → cell in which one of the 5th to 8th bits of the routing tag is 0

3): 8 (C-1) / 2 ^A + 1 = 1, 8C / 2 ^A = 2 → cell in which one of the 1st and 2nd bits of the routing tag is 0

4): 8 (C-1) / 2 ^A + 1 = 3, 8C / 2 ^A = 4 → cell in which one of the 3rd to 4th bits of the routing tag is 0

5): 8 (C-1) / 2 ^A + 1 = 5, 8C / 2 ^A = 6 → cells in which one of the 5th to 6th bits of the routing tag is 0

6): 8 (C-1) / 2 ^A + 1 = 7, 8C / 2 ^A = 8 → cell in which one of the 7th to 8th bits of the routing tag is 0

7): 8 (C-1) / 2 ^A + 1 = 1, 8C / 2 ^A = 1 → cells in which one of the 1st bits of the routing tag is 0

8): 8 (C-1) / 2 ^A + 1 = 2, 8C / 2 ^A = 2 → cell in which one of the 2nd bits of the routing tag is 0

9): 8 (C-1) / 2 ^A + 1 = 3, 8C / 2 ^A = 3 → cell in which one of the 3rd bits of the routing tag is 0

10): 8 (C-1) / 2 ^A + 1 = 4, 8C / 2 ^A = 4 → cell in which one of the 4th bits of the routing tag is 0

11): 8 (C-1) / 2 ^A + 1 = 5, 8C / 2 ^A = 5 → cell in which one of the 5th bits of the routing tag is 0

12): 8 (C-1) / 2 ^A + 1 = 6, 8C / 2 ^A = 6 → cell in which one of the sixth bits of the routing tag is 0

13): 8 (C-1) / 2 ^A + 1 = 7, 8C / 2 ^A = 7 → a cell in which one of the seventh bits of the routing tag is zero

14): 8 (C-1) / 2 ^A + 1 = 8, 8C / 2 ^A = 8 → cell in which one of the eighth bits of the routing tag is 0

By routing the cells in the 2n * n MUX switch using the routing tag in the same way as above, each cell is output to the desired n * n switch.Then * n MUX switch uses k bit routing tag bits. Send the cell to the final output port. In this case, the cell routing method of the n * n output switch is different depending on which switch is used.

As described above, the large-capacity ATM switch according to the embodiment of the present invention is composed of multi-stage MUX switches and output switches, and the multi-stage MUX switch network transfers an input cell to output switches of the final stage. The output switch serves to transmit a cell to be input in the MUX switch network to a final destination. Therefore, the large-capacity switch device according to the embodiment of the present invention can implement a large-capacity switch capable of multicasting and broadcasting using small-capacity switches, and the maximum switch capacity that can be implemented in one board is limited, so it is simple to use a limited switch capacity. It is possible to make a large capacity, and to transfer cells in a simple, fast and self-routing manner, and to minimize the performance deterioration due to the multi-stage by using the output buffer type switch as the MUX switch.

Claims (7)

In the N * N large capacity AMT switch device, It consists of log ₂ (N / n) MUX switch stages, each stage consists of N / n MUX switches, the final switch stage consists of n * n output switches, and N input ports comprise the first stage. Connected to the MUX switch groups t (1,1) and t (1,2) of the C-th stage of A stage with 1≤A≤log ₂ (N / n) -1 and 1≤C≤2 ^A The output ports of the MUX switch groups t (A, C) are connected to the input ports of t (A + 1,2C-1) and t (A + 1,2C) via the copier, respectively, and the final MUX switch group t A large-capacity ATM switch device characterized in that the output ports of (log ₂ (N / n), C) is configured to be connected to the input ports of the n * n output switches. The method of claim 1, wherein the MUX switches, A port selector configured to input 2n cells, analyze routing tag bits of the input cells, and select and output cells of the set bits; A packer configured of 2n packets and storing cells output from the port selector; A large-capacity ATM switch device comprising: an output unit configured to read cells stored in the encapsulation unit and output them to n output ports. The method according to claim 1 or 2, wherein the routing tag, Located in the cell header, a high-capacity AT switch device characterized by consisting of (N / n) bits representing each output group of the MUX switch and k bits representing the output switches. In the large capacity AT switch device, It consists of log ₂ (N / n) MUX switch stages, each stage consists of N / n MUX switches, the final switch stage consists of n * n output switches, and N input ports comprise the first stage. Connected to the MUX switch groups t (1,1) and t (1,2) of the C-th stage of A stage with 1≤A≤log ₂ (N / n) -1 and 1≤C≤2 ^A The output ports of the MUX switch groups t (A, C) are connected to the input ports of t (A + 1,2C-1) and t (A + 1,2C) via the copier, respectively, and the final MUX switch group t (log ₂ (N / n), C) output ports are connected to the input ports of the n * n output switches, From the switch group t (A, C) to which the cell is input, x determines a routing tag bit that satisfies the condition of N (C-1) / (n2 ^A ) + 1≤x≤NC / n2 ^A , And a bit determined from the routing tags of the input cells and transmitting the corresponding cell when there is a set bit. The method of claim 4, wherein the MUX switches, A port selector configured to input 2n cells, analyze routing tag bits of the input cells, and select and output cells of the set bits; A packer configured of 2n packets and storing cells output from the port selector; A large-capacity ATM switch device comprising: an output unit configured to read cells stored in the encapsulation unit and output them to n output ports. The method according to claim 4 or 5, wherein the routing tag, Located in the cell header, a high-capacity AT switch device characterized by consisting of (N / n) bits representing each output group of the MUX switch and k bits representing the output switches. It consists of log ₂ (N / n) MUX switch stages, each stage consists of N / n MUX switches, the final switch stage consists of n * n output switches, and N input ports comprise the first stage. Connected to the MUX switch groups t (1,1) and t (1,2) of the C-th stage of A stage with 1≤A≤log ₂ (N / n) -1 and 1≤C≤2 ^A The output ports of the MUX switch groups t (A, C) are connected to the input ports of t (A + 1,2C-1) and t (A + 1,2C) via the copier, respectively, and the final MUX switch group t In the routing method of a large-capacity ATM switch device configured to connect output ports of (log ₂ (N / n), C) to input ports of n * n output switches, From the switch group t (A, C) to which the cell is input, x determines a routing tag bit that satisfies the condition of N (C-1) / (n2 ^A ) + 1≤x≤NC / n2 ^A , Self-routing method of a high-capacity AT switch device characterized in that for checking the bits determined from the routing tag of the input cells and transmits the corresponding cell when there is a set bit.

Images