KR100226771B1 - Manufacturing method for flash memory - Google Patents

Abstract

The present invention relates to a method of manufacturing a flash memory in which a bit line is formed in a self-aligned manner after forming a floating gate to simplify a process and to be suitable for a highly integrated memory device. To this end, a gate insulating film is grown on the active region, and a first polysilicon layer, a first silicon nitride layer, and a first insulating layer are sequentially stacked on the gate insulating film, and the first insulating layer and the first silicon are formed. Forming a plurality of floating gates by sequentially etching the nitride layer and the first polysilicon layer, and forming a second silicon nitride layer on the entire surface including the floating gate and then etching the sidewalls on both sides of the floating gate. Forming a bit, removing the first insulating layer and performing bit line ion implantation using a sidewall as a mask, and removing the sidewall and the first silicon nitride layer, and performing punch-through ion implantation. Growing an oxide film on the surface of the floating gate; A step of performing ion implantation, and comprises a step of lamination to form a front control the second polysilicon layer and a second insulating layer for the gate, including the floating gate.

Description

Flash memory manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a flash memory suitable for forming a bit line and forming an inter-cell isolation process by a self-aligning method after forming a floating gate.

Hereinafter, a conventional flash memory manufacturing method will be described with reference to the accompanying drawings.

Conventional flash memory cells are divided into an ETOX ^TM (EPROM Tunnel Oxide) structure and a separate gate structure.

The double-separated gate structure has a disadvantage that the unit cell size is larger than that of the ETOX ^TM , but there is no problem of over-erasing and it is possible to configure a virtual grounded memory array.

FIG. 1A illustrates a flash memory cell array having a virtual gate type split gate structure.

As shown in FIG. 1A, the virtual gate type split gate structure is suitable for a highly integrated memory because there is no need to isolate each bit line by configuring one bit line as a source or a drain.

FIG. 1B is a layout view of a memory cell having a conventional gate structure having a separate gate structure, and FIGS. 1C to 3D are cross-sectional views taken along the X and Y axes of FIG. 1B.

As shown in FIGS. 1C and 1D, a memory cell having a separate gate structure having a conventional virtual grounding method has a high concentration of impurity regions 2 buried by high concentration N ⁺ impurity ion implantation into a P-type semiconductor substrate 1. A plurality of isolation oxide films 3 are formed at intervals and intersect the buried high concentration impurity regions 2.

A gate oxide film 4 is formed on the entire surface of the semiconductor substrate 1 except the isolation oxide film 3, and a polysilicon layer is formed on the entire surface of the semiconductor substrate 1 including the isolation oxide film 3. The floating gate 5b is formed so as to overlap and partially overlap the impurity region 2 having a high concentration.

The first interlayer insulating film 6 is formed on the entire surface of the semiconductor substrate 1 including the floating gate 5b, and the control gate line 7a and the cap are narrower than the floating gate on the first interlayer insulating film 6. An oxide film 8 is formed.

The sidewall oxide film 9 is formed on the side of the cap oxide film 8 and the control gate line 7a, and the erase gate line 11a is configured to overlap one line per two control gate lines on the control gate line 7a. do.

Here, one erase gate line 11a can erase the charges of the two floating gates 5b.

The flash memory thus configured can be used in a virtual scaffolding manner.

In other words, when an arbitrary bit line is sourced, an adjacent bit line is used as a drain.

When injecting electrons into the floating gate 5b, the source is grounded, a voltage of about 7V is applied to the drain, and 12V is applied to the control gate 7a. Hot electrons are generated near the drain to generate the floating gate. Electrons are injected into 5b).

When the electrons are removed from the floating gate 5b, when a high voltage of about 20V is applied to the erasing gate 11a, a polysilicon and polysilicon interlayer tunnel oxide film between the floating gate 5b and the eliminating gate 11a is formed. The electrons move to the erase gate 11a.

Referring to the accompanying drawings, a conventional flash memory manufacturing method having the above configuration is as follows.

2A to 2I are process cross-sectional views taken along line AA ′ of FIG. 1B, and FIGS. 3A to 3I are process cross-sectional views taken along line B-B ′ of FIG. 1B.

First, as shown in FIGS. 2A and 3A, a high concentration N ⁺ impurity ions are selectively implanted into the P-type semiconductor substrate 1 to form a plurality of buried high concentration impurity regions 2 at regular intervals, and the high concentration impurity region 2 is formed. The CVD oxide film is deposited on the formed semiconductor substrate 1, and then a photoetching process is performed to form a plurality of isolation oxide films 3 at regular intervals to intersect the high concentration impurity region 2.

Subsequently, as shown in FIGS. 2B and 3B, a gate oxide film 4 is formed on the entire surface of the semiconductor substrate 1 on which the isolation oxide film 3 is not formed, and the semiconductor substrate 1 including the isolation oxide film 3 is formed. The polysilicon layer 5 to be used as a floating gate is formed on the front surface.

Subsequently, as shown in FIGS. 2C and 3C, the photoresist PR1 is coated on the polysilicon layer 5, the floating gate line is defined by an exposure and development process, and the patterned photoresist is used as an etching. In the process, the polysilicon layer 5 is selectively removed to form the floating gate line 5b.

In this case, the floating gate line 5a overlaps the high concentration impurity region 2 by a predetermined interval.

2D and 3D, after removing the photoresist PR1, the first interlayer insulating film 6 is formed on the entire surface of the semiconductor substrate 1 including the floating gate line 5a and the isolation oxide film 3. The polysilicon layer 7 for the control gate, the cap oxide film 8 and the photoresist PR2 are sequentially formed.

Next, the photoresist PR2 is patterned by an exposure and development process to define a control gate line.

Subsequently, as shown in FIGS. 2E and 3E, the cap oxide layer 8, the control gate polysilicon layer 7, and the first interlayer insulating layer 6 are selectively selected by an etching process using the photoresist PR2 as a mask. To form the control gate line 7a.

At this time, each control gate line 7a overlaps the isolation oxide film 3 by a predetermined interval.

2F and 3F, the photoresist PR2 is removed, a sidewall forming oxide film is deposited on the entire surface of the semiconductor substrate 1, and then etched back to form a cap oxide film 8, a control gate line 7a, Sidewalls 9 are formed on the side surfaces of the first interlayer insulating film 6.

Subsequently, as shown in FIGS. 2G and 3G, the floating gate lines 5a are etched using the sidewalls as masks to form respective floating gates 5b.

At this time, a part of the side wall 9 and the isolation oxide film 3 are also etched.

As shown in FIGS. 2H and 3H, a second interlayer insulating film 10 and a polysilicon layer 11 for an erase gate are stacked on the entire surface of the semiconductor substrate 1 including the cap oxide film 8 and the sidewalls 9. Then, photoresist PR3 is coated on the erase gate polysilicon layer 11.

The photoresist PR3 is patterned by an exposure and development process to define an erase gate region.

Next, as shown in FIGS. 2I and 3I, the erase gate polysilicon layer 11 and the second interlayer insulating layer 10 are selectively removed by an etching process using the patterned photoresist PR3 as a mask. An erase gate line 11a is formed.

However, the conventional flash memory as described above has the following problems.

First, since the bit line must be formed before the device isolation film is formed, the process proceeds in the order of the bit line formation, the isolation film formation, and the floating gate formation, so that misalignment of the floating gate and the bit line is inevitably generated.

Second, as the bit line is formed at the beginning of the process and the process proceeds, an increase in the cell size considering the diffusion of the bit line junction is required.

The present invention has been made to solve the above problems, by forming a bit line by self-alignment after forming the floating gate and forming a thick oxide film thereon to protect the bit line portion in the cell isolation process performed in the subsequent process An object of the present invention is to provide a method for manufacturing a highly integrated flash memory which does not cause a misalignment problem.

1A illustrates a conventional flash memory cell array.

1B is a layout diagram of a conventional flash memory cell.

FIG. 1C is a cross-sectional view taken along the line A-A 'of FIG. 1B

FIG. 1D is a cross-sectional view along the line B-B 'of FIG. 1B

2a to 2i are process cross-sectional views taken along line A-A 'of FIG. 1b.

3A to 3I are cross-sectional views taken along the line BB ′ of FIG. 1B.

4 is a layout diagram of a flash memory cell of the present invention.

5a to 5f are process cross-sectional views taken along line II ′ of FIG. 4.

6a to 6i are cross-sectional views of the process according to II-II 'of FIG.

Explanation of symbols for main parts of the drawings

100 substrate 103 first polysilicon layer

104: first silicon nitride layer 107: impurity region for bit line

109: polyoxide film 110, 111: impurity region for punch-through prevention

113: second polysilicon layer 119: tunneling oxide film for erasure

120: third polysilicon layer

In the flash memory manufacturing method of the present invention for achieving the above object, a gate insulating film is grown on an active region, and a first polysilicon layer, a first silicon nitride layer, and a first insulating layer are sequentially formed on the gate insulating film. Forming a plurality of floating gates by sequentially etching the first insulating layer, the first silicon nitride layer, and the first polysilicon layer; and forming a second silicon nitride layer on the entire surface including the floating gate. Forming and etching sidewalls on both sides of the floating gate, removing the first insulating layer, and performing bitline ion implantation using the sidewalls as a mask, and the sidewalls and first silicon nitride. Removing the layer and performing ion implantation for punch-through prevention and growing an oxide film on the surface of the floating gate; And implanting drain junction ions into the semiconductor substrate on one side of the floating gate, and laminating a second polysilicon layer and a second insulating layer for a control gate on the entire surface including the floating gate.

Hereinafter, a method of manufacturing a flash memory of the present invention will be described with reference to the accompanying drawings.

4 is a layout diagram of a flash memory cell according to the present invention.

As shown in FIG. 4, the flash memory of the present invention includes a plurality of floating gates 42 formed in one direction on a semiconductor substrate 41 at a predetermined interval from each other, and in a direction perpendicular to the floating gate 42. A plurality of control gates 43 formed at a predetermined interval, erase gates 44 formed to overlap a portion with the control gate 43 between the control gates 43, and the gates together And a cell region 45 formed to be.

5A through 5F are cross-sectional views taken along line II ′ of FIG. 4, and FIGS. 6A through 6I are process cross-sectional views taken along line II-II ′ of FIG. 4, and FIGS. 5 and 6 will be described at the same time.

First, as illustrated in FIGS. 5A and 6A, the flash memory of the present invention defines a field region in the semiconductor substrate 100, and then forms a field oxide film 101 in the field region to define an active region.

At this time, the field oxide film 101 is formed using a LOCOS process.

Next, as shown in FIGS. 5B and 6B, an oxide film 102 is grown on the semiconductor substrate 100 in the active region as a gate insulating film, and the first polysilicon layer 103 and the first silicon to be used as floating gates thereon. The nitride layer 104 and the first CVD oxide layer 105 are sequentially formed.

As shown in FIG. 5B, a photoresist (not shown) is applied on the first CVD oxide layer 105 and then patterned through an exposure and development process.

The patterned photoresist is used as a mask to selectively remove the first CVD oxide layer 105, the first silicon nitride layer 104, and the first polysilicon layer 103 thereunder.

6B is a cross-section taken along the line II-II 'of FIG. 4, so that the first polysilicon layer 103, the first silicon nitride layer 104, and the first CVD oxide layer 105 are etched as described above. The losing part is not shown.

Subsequently, as illustrated in FIGS. 5C and 6C, the semiconductor substrate 100 including the patterned first CVD oxide layer 105, the first silicon nitride layer 104, and the first polysilicon layer 103 is formed on the entire surface of the semiconductor substrate 100. After forming the second silicon nitride layer, the semiconductor substrate 100 is etched back until the surface of the semiconductor substrate 100 is exposed. As shown in FIG. 5C, the first CVD oxide layer 105 and the first silicon nitride layer ( 104 and sidewalls 106 made of a second silicon nitride layer are formed on both sides of the first polysilicon layer 103.

After the first CVD oxide layer 105 is removed by etching, impurity ions are implanted into the semiconductor substrate 100 using the sidewalls 106 and the first polysilicon layer 103 as masks. (See Figure 5c)

6C shows a state in which the first CVD oxide layer 105 is removed.

Subsequently, an oxide film 107 for device isolation is grown on the semiconductor substrate 100 into which the bit line impurities are implanted, and the impurity ions are diffused through a diffusion process to form a first impurity region 108.

Next, the sidewall 106 and the first silicon nitride layer 104 are etched and removed (see FIG. 5D). The exposed first polysilicon layer 103 is removed as shown in FIGS. 5E and 6D. Oxidation is performed to form the polyoxide film 109.

As shown in FIG. 5E, source / drain may be formed in the semiconductor substrate 100 on both sides of the floating gate 103 through punch-through prevention ion implantation using the floating gate (first polysilicon layer) 103 as a mask. Impurity regions 110 and 111 are formed.

At this time, the punch-through prevention ion is not implanted into the lower portion of the floating gate 103 due to the poly oxide film 109.

Subsequently, the second impurity region 112 is implanted by ion implantation only into the drain region 111 through the drain junction ion implantation having a predetermined angle.

The ion implantation process may be applicable after exposing the drain region using a photoresist instead of the tilt ion implantation ion implanted only into the drain region. The punch-through prevention ion is of the opposite conductivity type to the first impurity region 108 and the tilt ion implanted only in the drain region is of the opposite conductivity type to the punch-through prevention ion.

Subsequently, as shown in FIGS. 5F and 6E, the second polysilicon layer 113 and the second CVD oxide film for heat treatment after completion of the tilt ion implantation and the formation of a control gate on the front surface including the polyoxide film 109 are performed. Forming layer 114 completes the process according to I-I 'of FIG. 4 (see FIG. 5F).

Subsequently, as shown in FIG. 6E, a second CVD oxide layer 114 is formed on the second polysilicon layer 113, and then a photoresist (not shown in the drawing) is formed on the second CVD oxide layer 114. Is applied).

Subsequently, after the photoresist is patterned, the second CVD oxide layer 114 and the second polysilicon layer 113 below are selectively removed using the patterned photoresist as a mask.

An oxide film is deposited on the entire surface of the substrate 100 including the second polysilicon layer (control gate) 113 and then etched back on both sides of the second CVD oxide layer 114 and the second polysilicon layer 113. The first sidewall 115 is formed (see FIG. 6E).

Subsequently, as shown in FIG. 6F, the first polysilicon layer 103 is etched using the first sidewall 115 and the second CVD oxide layer 114 as a mask.

And forming a third silicon nitride layer on the entire surface, and then etching back the second sidewall 116 of the third silicon nitride layer 114 over the second CVD oxide layer 114 including the first polysilicon layer 103. ).

Subsequently, as illustrated in FIG. 6G, the third impurity region 117 is formed by implanting impurity ions for device isolation using the second sidewall 115 and the second CVD oxide layer 114 as a mask, followed by an oxidation process. Then, the device isolation region 118 is formed.

Subsequently, as shown in FIG. 6H, only the second sidewall 116 formed of the third silicon nitride layer is removed, and then a tunneling oxide oxide layer 119 is grown on the exposed surface of the first polysilicon layer 103. .

A third polysilicon layer 120 for erasing gate is formed on the entire surface.

Subsequently, as shown in FIG. 6I, a photoresist (not shown) is applied onto the third polysilicon layer 120 and then patterned by an exposure and development process.

By using the patterned photoresist as a mask to selectively remove the lower third polysilicon layer 120 to form the erase gate 120a, the process according to II-II 'of FIG. 4 is completed.

As described above, the flash memory manufacturing method of the present invention has the following effects.

First, since the bit line is formed by the self-aligning method after the floating gate is formed, the problem caused by misalignment is eliminated.

Second, since bit line formation is performed after the floating gate is formed, the bit line diffusion effect and cell size increase due to the heat treatment process are prevented.

Third, planarization is advantageous and the process is simplified.

Claims (8)

Growing a gate insulating film on the active region and sequentially laminating a first polysilicon layer, a first silicon nitride layer, and a first insulating layer on the gate insulating film, the first insulating layer, and the first silicon nitride Forming a plurality of floating gates by sequentially etching the layer and the first polysilicon layer, Forming a second silicon nitride layer on the entire surface including the floating gate and then etching to form sidewalls on both sides of the floating gate; Performing a bit line ion implantation using the sidewalls as a mask after removing the first insulating layer, and performing ion implantation for preventing punch-through after removing the sidewalls and the first silicon nitride layer, and removing the surface of the floating gate. Growing an oxide film on the semiconductor substrate, implanting drain junction ions into the semiconductor substrate on one side of the floating gate, and laminating a second polysilicon layer and a second insulating layer for the control gate on the entire surface including the floating gate. Flash memory manufacturing method comprising a step. The method of claim 1, wherein the bit line ions and the punch-through prevention ions are opposite to each other. The method of claim 1, wherein the drain junction ion implantation is performed using a tilde ion implantation method. 4. The method of claim 3, further comprising a selective ion implantation method using a mask instead of the tilt ion implantation method. The method of claim 1, wherein the sidewall is formed of silicon nitride. Forming a first polysilicon layer on the entire surface of the semiconductor substrate including the active region, laminating a first insulating layer, a second polysilicon layer, and a second insulating layer on the first polysilicon layer; Selectively removing the second insulating layer and the second polysilicon layer to form a plurality of control gates having a predetermined distance from each other and having a second insulating layer stacked thereon; and first sidewalls on both sides of the second insulating layer and the control gate. Forming a second layer, etching the first polysilicon layer using the first sidewall and the second insulating layer as a mask, and a second insulating layer on both sides of the first insulating layer including the first polysilicon layer. Forming a sidewall, Performing impurity ion implantation for cell isolation on semiconductor substrates on both sides using the second sidewall as a mask; And removing the second sidewall, forming a tunneling oxide film on the surface of the floating gate, forming a second polysilicon layer on the front surface, and then patterning the erase gate to form an erase gate. Way. 7. The method of claim 6, wherein the material of the first insulating layer is silicon nitride. 7. The method of claim 6 wherein the material of the first sidewall is an oxide and the material of the second sidewall is silicon nitride.