KR100223480B1 - A circuit of generating high voltage of non-volatile semiconductor memory device - Google Patents

Abstract

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of sensing a high voltage level output from a high voltage pumping circuit and controlling nonvolatile The present invention relates to a high-voltage generating circuit for a semiconductor memory device, and more particularly, to a high-voltage generating circuit for a semiconductor memory device which includes a reference voltage generator for generating a reference voltage of a predetermined level in response to an enable signal applied from the outside; And outputs a pulse signal having a first period in response to the drive signal and outputs a pulse signal in response to the control signal in response to the enable signal, a predetermined drive signal, and a predetermined control signal, An oscillation unit outputting the pulse signal having a second period; A high voltage pumping unit generating a high voltage in response to the oscillation signal output from the oscillation unit; And a controller for receiving the high voltage output from the high voltage pumping unit and detecting whether the high voltage is pumped to a voltage level lower than the desired voltage level by a predetermined control signal and converting the first distribution voltage into a predetermined level A first voltage distributor for outputting the voltage; A second voltage distribution unit receiving the high voltage output from the high voltage pumping unit and detecting whether the high voltage is pumped to a desired voltage level in response to the control signal and outputting a second distribution voltage obtained by converting the high voltage into a predetermined level, ; And a second voltage dividing unit that receives the reference voltage output from the reference voltage generating unit and the first and second dividing voltages output from the first and second voltage dividing units, A comparator for comparing the comparison signal with a predetermined level; A driving unit for outputting the driving signal applied to the oscillation unit in response to the enable signal and the comparison signal; A first control unit responsive to the enable signal and the comparison signal for outputting the first control signal applied to the first voltage divider; And a second control unit responsive to the first control signal and the enable signal for outputting the second control signal applied to the second voltage distribution unit and the oscillation unit.

Description

A high voltage generating circuit for a nonvolatile semiconductor memory device.

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of sensing a high voltage level output from a high voltage pumping circuit and controlling nonvolatile To a high voltage generating circuit of a semiconductor memory device.

In the case of a semiconductor memory device, particularly an electrically erasable and programmable nonvolatile semiconductor memory device, in performing an erase operation for erasing data stored in a memory cell and a program operation for storing data in the memory cell, the FN tunneling Fowler-Nordheim tenneling) and hot electron injection (hot electron injection). Although not shown in the figure, the memory cell of the nonvolatile semiconductor memory device is typically formed with a source region and a drain region with a channel region formed in a p-type semiconductor substrate interposed therebetween. A gate oxide, a floating gate, an ONO film, and a control gate are sequentially formed on the channel. An erase operation is performed before the program operation for storing data in the memory cell is performed, which is performed through the F-N tunneling. The F-N tunneling means discharging electrons accumulated on the floating gate of the memory cell to the source region, and a high voltage is applied to the source region of the memory cell.

When the erase operation is completed, the memory cell to be programmed is programmed, and the programming method used at this time is the Hot Electron Injection method. The Hot Electron Injection means that electrons in the channel region adjacent to the drain region of the memory cell are injected into the floating gate of the memory cell. At this time, a high voltage is applied to the control gate of the memory cell. In order to perform the erase and program operation according to the above-described method, a high voltage between 15 volts and 20 volts is usually required. Generally, in the case of a semiconductor memory device operating under a low power supply voltage, a high voltage generating circuit for internally generating the high voltage is built in the chip, and the erase and program operation takes several ms to perform several ms.

FIG. 1 is a block diagram showing a high voltage generating circuit of a semiconductor memory device according to the prior art.

1 includes a reference voltage generating unit 10, an oscillating unit 20, a high voltage pumping unit 30, a voltage distributing unit 40, a comparing unit 50, and a driving unit 60 ). The reference voltage generator 10 outputs a reference voltage Vref of a predetermined level in response to an enable signal ENABLE applied through the input terminal 1. [ The oscillation unit 20 outputs an oscillation signal S_osc having a predetermined period F0 in response to the enable signal ENABLE and the predetermined driving signal S_driv. The high voltage pumping unit 40 performs a voltage pumping operation in response to the oscillation signal S_osc outputted from the oscillation unit 20 and outputs a high voltage Vpgm of a certain level (for example, 18-20 volts) do. The voltage divider 40 outputs the divided voltage Vdevide converted from the high voltage Vpgm output from the high voltage pumping unit 30 to a predetermined voltage level in response to the enable signal ENABLE . The voltage divider 40 includes resistors R1 and R2 for voltage division of the high voltage Vpgm and a current I3 between the output terminal 2 and the ground terminal 3 in response to the enable signal ENABLE. And an NMOS transistor M1 for forming a path. The comparison unit 50 receives the reference voltage Vref output from the reference voltage generation unit 10 and the distribution voltage Vdevide output from the voltage distribution unit 40, And outputs a comparison signal S_comp at a predetermined level. The driving unit 60 outputs the driving signal S_driv applied to the oscillation unit 20 in response to the comparison signal S_comp output from the comparison unit 50 and the enable signal ENABLE, And is provided with a NAND gate G1 and an inverter I1.

FIG. 2 shows an operation timing chart at the time of generation of a high voltage according to the prior art. Referring to FIGS. 1 and 2, the operation of generating a high voltage according to the related art will be described as follows.

As shown in FIG. 2, when the enable signal ENABLE indicating the generation of the high voltage transitions from a low level to a high level, the reference voltage generator 10, the oscillator 20, The high voltage pumping unit 30, the voltage distribution unit 40, the comparing unit 50 and the driving unit 60 are both enabled to perform the high voltage pumping operation. First, a reference voltage Vref of a predetermined level (for example, 1.5 volts) is generated by the reference voltage generator 10. The reference voltage generator 10 is a well-known CMOS reference voltage generator circuit and its detailed description is omitted. At this time, the reference voltage Vref generated from the reference voltage generator 10 is input to one of the input terminals of the comparator 50. The NMOS transistor M1 of the voltage divider 40 is turned on by the enable signal ENABLE transitioned to a high level. Thereby, a current path is formed between the output terminal 2 of the high-voltage pumping unit 30 and the ground terminal 3 to which the ground voltage VSS is applied. The distribution voltage Vdevide distributed to the node 1 by the resistors R1 and R2 of the voltage distributor 40 is applied to the other input terminal of the comparator 50. [ Here, since the voltage level of the output terminal 2 is about 0 volts in an initial state of high voltage generation operation, the comparator 50 outputs a high level comparison signal S_comp.

The driving unit 60 receives the comparison signal S_comp at a high level and the enable signal ENABLE and outputs a driving signal S_driv at a high level. The oscillation unit 20 is driven to output an oscillation signal S_osc having a predetermined period and the high voltage pumping unit 30 is driven by the oscillation signal S_osc to start a high voltage pumping operation . At this time, as the voltage level output to the output terminal 3 rises while the high voltage pumping unit 30 is driven, the current flowing through the NMOS transistor Ml of the voltage distributor 40 increases, The voltage level rises. And outputs the comparison signal S_comp of a low level from the comparator 50 when the voltage level of the node 1 rises to reach the same level as the reference voltage Vref. When the voltage level of the comparison signal S_comp exceeds the trip point of the NAND gate G1 of the driving unit 60, the oscillation unit 20 is disabled. As a result, the pumping operation of the high-voltage pumping unit 30 is stopped, thereby obtaining a high-level voltage Vpgm of a desired level. Here, in order to obtain the high voltage Vpgm at a desired voltage level, a desired high voltage level can be obtained by adjusting the resistance values of the resistors R1 and R2 of the voltage distributor 40. [

However, according to the high-voltage generation circuit of the conventional nonvolatile semiconductor memory device, in order to reduce the active currrent, each resistance value of the voltage distributor 40 must be increased and a resistance of 1M or more is usually connected . When the resistance value is increased to reduce the active current, the response speed of the distribution voltage Vdevide output from the node 1 due to the variation of the high voltage level is slowed down. As a result, a ripple of high voltage is generated. Further, as shown in FIG. 2, after the high voltage level reaches the desired voltage level, the high voltage level is sensed and the oscillation unit 20 is disabled. At this time, a delay (for example, 300 nS) occurs until the pumping operation of the high voltage pumping unit 30 is stopped by the oscillation unit 20, and the oscillation unit 20 continues to operate during this period. During this period, the number of times of pumping by the high voltage pumping unit 30 is Td / F0. (Where, Td = sensing delay time, F ₀ = the oscillation period of the oscillation signal output from the oscillation unit) In addition, the pumping operation is disabled by the high voltage is lowered by the comparison section 50 after a predetermined level of descending relative to the desired high voltage level The high voltage level continues to fall until the pumping operation is resumed, and the overall high voltage level variation (high voltage error) is as shown in FIG. Therefore, when the high voltage level due to the delay of the detection speed of the high voltage level becomes higher than the desired voltage level, over-programming or over-erasing occurs and the degree of shift of the threshold voltage becomes larger than the voltage level of the desired threshold voltage, There was also a problem that caused.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and it is therefore an object of the present invention to provide a nonvolatile semiconductor memory device capable of detecting a high voltage level output from a high- Voltage generating circuit of a semiconductor memory device.

1 is a block diagram showing a configuration of a high voltage generating circuit of a semiconductor memory device according to the related art;

2 is an operation timing diagram according to the prior art;

3 is a block diagram showing a configuration of a high voltage generating circuit of a semiconductor memory device according to a preferred embodiment of the present invention;

4 is a circuit diagram showing a detailed circuit of a reference voltage generator according to a preferred embodiment of the present invention;

5 is a circuit diagram showing a detailed circuit of an oscillation unit according to a preferred embodiment of the present invention;

6 is a circuit diagram showing detailed circuitry of a high-voltage pumping unit according to a preferred embodiment of the present invention;

FIG. 7 is a circuit diagram showing a detailed circuit of a comparison unit according to a preferred embodiment of the present invention; FIG.

8 is an operation timing diagram according to a preferred embodiment of the present invention,

DESCRIPTION OF REFERENCE NUMERALS

10: reference voltage generator 20: oscillator

30: High-voltage pumping unit 40, 42: Voltage distribution unit

50: comparator 60:

70, 80:

According to an aspect of the present invention, there is provided a semiconductor memory device including: a reference voltage generator for generating a reference voltage at a predetermined level in response to an enable signal applied from the outside; And outputs a pulse signal having a first period in response to the drive signal and outputs a pulse signal in response to the control signal in response to the enable signal, a predetermined drive signal, and a predetermined control signal, An oscillation unit outputting the pulse signal having a second period; A high voltage pumping unit generating a high voltage in response to the oscillation signal output from the oscillation unit; And a controller for receiving the high voltage output from the high voltage pumping unit and detecting whether the high voltage is pumped to a voltage level lower than the desired voltage level by a predetermined control signal and converting the first distribution voltage into a predetermined level A first voltage distributor for outputting the voltage; A second voltage distribution unit receiving the high voltage output from the high voltage pumping unit and detecting whether the high voltage is pumped to a desired voltage level in response to the control signal and outputting a second distribution voltage obtained by converting the high voltage into a predetermined level, ; And a second voltage dividing unit that receives the reference voltage output from the reference voltage generating unit and the first and second dividing voltages output from the first and second voltage dividing units, A comparator for comparing the comparison signal with a predetermined level; A driving unit for outputting the driving signal applied to the oscillation unit in response to the enable signal and the comparison signal; A first control unit responsive to the enable signal and the comparison signal for outputting the first control signal applied to the first voltage divider; And a second control unit responsive to the first control signal and the enable signal for outputting the second control signal applied to the second voltage distribution unit and the oscillation unit.

In this embodiment, the reference voltage generator includes a plurality of resistors and a plurality of MOS transistors.

In this embodiment, the oscillation unit includes a plurality of delay means serially connected to receive the oscillation signal and delay it for a predetermined time; And output means for outputting the oscillation signal in response to the predetermined signal, the driving signal, and the enable signal output from the delay means at the last stage of the delay means.

In this embodiment, each of the delay means includes an inverting means for inverting a signal output from the previous stage; First charging means for determining the first period (F0) of the oscillation signal by charging the signal or discharging the signal in response to a predetermined signal outputted from the inverting means; And second charging means for determining a second period of the oscillation signal by charging a predetermined signal outputted from the inverting means or discharging the charged signal in response to the second control signal.

In this embodiment, the inverting means of each delay means is provided as an inverter.

In this embodiment, the first charging means of each delay means is provided as capacitor means.

In this embodiment, the second charging means includes switching means for switching in response to the second control signal; And a capacitor means for charging a predetermined signal transmitted through the switching means or discharging the charged signal through the switching means.

In this embodiment, the switching means is provided with an n-channel conduction type MOS transistor.

In this embodiment, the output means is provided as a 3-input NAND gate.

In this embodiment, the high voltage pumping portion is provided with a plurality of MOS transistors, capacitors, and an inverter.

In this embodiment, the first voltage divider comprises resistance means and switching means.

In this embodiment, the switching means is an n-channel conduction type MOS transistor enabled in response to the first control signal.

In this embodiment, the second voltage divider comprises resistance means and switching means.

In this embodiment, the switching means is an n-channel conduction type MOS transistor enabled in response to the second control signal.

In this embodiment, the comparison unit includes a plurality of PMOS transistors and a plurality of NMOS transistors.

In this embodiment, the driving unit is provided with a NAND gate and an inverter.

In this embodiment, the first control unit is provided with the latched NAND gates.

In this embodiment, the second controller is provided as a NAND gate that outputs the second control signal in response to the enable signal and the first control signal.

By such a circuit, it is possible to prevent over-programming or over-erasing of the non-volatile semiconductor memory device by reducing the ripple phenomenon caused by the sensing delay time for sensing and controlling the high voltage level output from the high voltage generating portion .

Reference will now be made in detail to the preferred embodiments of the present invention with reference to Figures 3-8.

3 is a block diagram showing the configuration of the high voltage generating circuit of the semiconductor memory device according to the preferred embodiment of the present invention.

3 includes a reference voltage generating unit 10, an oscillating unit 20, a high voltage pumping unit 30, a first voltage distributor 40, a second voltage divider 40, A distribution section 42, a comparison section 50, a driving section 60, and first and second control sections 70 and 80. The reference voltage generator 10 outputs a reference voltage Vref of a predetermined level (about 1.5 volts) in response to the enable signal ENABLE. The oscillating unit 20 responds to the enable signal ENABLE, the driving signal S_driv output from the driving unit 60 and the second control signal S_cont2 output from the second control unit 80, And outputs an oscillation signal S_osc for driving the high-voltage pumping section 30. [ The oscillation unit 20 outputs the oscillation signal S_osc having the first period F0 while the driving signal S_driv is applied. The oscillation unit 20 outputs the oscillation signal S_osc of the second period F1 that is longer than the first period F0 by a predetermined time while the second control signal S_cont2 is applied.

The high voltage pumping unit 30 outputs a high voltage Vpgm of a desired level by performing a high voltage pumping operation in response to the oscillation signal S_osc output from the oscillation unit 20. [ The first voltage divider 40 detects a high voltage (for example, about 18 volts) lower than the desired high voltage Vpgm (for example, about 20 volts) output from the high voltage generator 30 And outputs a first divided voltage Vdevide1 converted to a predetermined voltage level, and is provided with resistors R1 and R2 and an NMOS transistor M1. That is, when it is pumped down to a predetermined level lower than the desired high voltage Vpgm, a voltage equal to the reference voltage Vref is output. For this, the values of the resistors R1 and R2 must be set appropriately. At this time, the NMOS transistor M1 used as the switching means of the first voltage distributor 40 is enabled by the first control signal S_cont1 output from the first controller 70. A current path is formed between the output terminal 2 from which the high voltage Vpgm is outputted and the ground terminal 2 to which the ground voltage VSS is applied and the first voltage distributor 40 is enabled The first distribution voltage S_devide1 is output.

The comparator 50 receives the reference voltage Vref and the first distribution voltage Vdevide1 and compares the voltage levels of the two signals Vref and Vdevide1 with each other. If the reference voltage Vref is at a high level, it outputs a high level comparison signal S_comp, and in the opposite case, it outputs a low level comparison signal S_comp. The driving unit 60 receives the comparison signal S_comp output from the comparator 50 and the enable signal ENABLE and outputs the driving signal S_driv applied to the oscillation unit 20, And is provided with a NAND gate G1 and an inverter I1. The first controller 70 responds to the comparison signal S_comp output from the comparator 50 and the enable signal ENABLE to the switching transistor Ml of the first voltage divider 40 And outputs the applied first control signal S_cont1. The first control unit 70 is composed of the NAND gates G2 and G3 that are latched and serves as a 1-bit cell storage unit.

The second control unit 80 outputs the second control signal S_cont2 in response to the first control signal S_cont1 output from the first control unit 70 and the enable signal ENABLE. The second voltage divider 42 detects whether the high voltage Vpgm output from the high voltage generator 30 is pumped to a desired voltage level (for example, about 20 volts) And outputs the second divided voltage Vdevide2, which is obtained by converting the first divided voltage Vdevide2 into the second divided voltage Vdevide2, and includes the resistors R3 and R4 and the NMOS transistor M2. That is, when the voltage is pumped to the desired high voltage Vpgm, the same voltage as the reference voltage Vref is output. At this time, the NMOS transistor M2 used as the switching unit of the second voltage distributor 42 is enabled by the second control signal S_cont2 output from the second control unit 80. [ A current path is formed between the output terminal 2 from which the high voltage Vpgm is outputted and the ground terminal 3 to which the ground voltage VSS is applied and the second voltage distributor 42 is enabled The second distribution voltage S_devide2 is output.

FIG. 4 is a circuit diagram showing a detailed circuit of a reference voltage generator according to a preferred embodiment of the present invention. The reference voltage generator 10 shown in FIG. 4 outputs a reference voltage Vref of a predetermined level (for example, 1.5 volts) in response to an enable signal ENABLE applied from the outside, and the resistors R5, R and MOS transistors M4 - M6.

FIG. 5 is a circuit diagram showing a detailed circuit of an oscillation unit according to a preferred embodiment of the present invention.

The oscillation unit 20 according to the preferred embodiment of the present invention shown in FIG. 5 includes an enable signal ENABLE applied from the outside, a driving signal S_driv output from the driving unit 60 shown in FIG. 3, 2 oscillation signal S_osc in response to the second control signal S_cont2 output from the second control unit 80. [ The oscillation unit 20 outputs the oscillation signal S_osc having the first period F0 while the driving signal S_driv is applied. The oscillation unit 20 outputs the oscillation signal S_osc of the second period F1 that is longer than the first period F0 by a predetermined time while the second control signal S_cont2 is applied. The oscillation unit 20 includes a plurality of delay means 22 and an output means 26. Each of the delay means 22 comprises an inverting means 23, a first charging means 24 and a second charging means 25 for determining the oscillation period of the oscillation signal S_osc. The inverting means (23) of each delay means (22) inverts the phase of the signal applied from the previous stage and outputs it.

The first charging means 24 is provided as a capacitor C1 and charges a signal output from the inverting means 23, for example, when the power source voltage VCC is outputted. If the ground voltage VSS is outputted from the inverting means 23, the charges charged in the first charging means 24 are discharged to the ground voltage VSS. The cycle of the oscillation signal S_osc is determined by the charge and inversion of the capacitor C1 of each delay unit 22 as described above. Here, the period determined by the first charging means 24 is referred to as a first period F0. Next, when the second control signal S_cont2 transitions from a low level to a high level, the NMOS transistor M3 of the second charging means 25 is enabled and the capacitor C1 of the first charging means 24 is turned on, The capacitor C2 of the second charge means 25 operates. The oscillation signal S_osc having a second period F1 that is longer than the first period F0 by a predetermined time is output by the capacitors C1 and C2.

FIG. 6 is a circuit diagram showing detailed circuitry of a high voltage pumping unit according to a preferred embodiment of the present invention. The high-voltage pumping unit 30 shown in FIG. 6 performs a pumping operation in response to an oscillation signal S_osc having a predetermined period applied from the outside. As a result, a high voltage Vpgm of a predetermined level (for example, 18 volts to 20 volts) used in erasing and program operation is generated. The high voltage pumping unit 30 includes an inverter I7, a plurality of capacitors C3 to C8, and a plurality of MOS transistors M7 to M13.

FIG. 7 is a circuit diagram showing a detailed circuit of a comparing unit according to a preferred embodiment of the present invention. The comparator 50 shown in FIG. 7 receives the reference voltage Vref output from the reference voltage generator 10 and predetermined distribution voltages S_devide1 and S_devide2, and compares them. If the distribution voltages S_devide1 and S_devide2 are lower than the reference voltage Vref, the comparator 50 outputs a high level comparison signal S_comp. When the reference voltage Vref is lower than the distribution voltages S_devide1 and S_devide2, the comparator 50 outputs the comparison signal S_comp at a low level. The comparator 50 includes a plurality of MOS transistors M14 to M18.

8 shows an operation timing diagram according to a preferred embodiment of the present invention. Referring to FIGS. 3 to 8, the description will be made as to how the ripple phenomenon is reduced through the high voltage generating operation according to the present invention.

First, when the enable signal ENABLE for notifying the generation of the high voltage is low level, the DC path of the first voltage divider 40 and the second voltage divider 42, that is, the high voltage Vpgm is outputted The current path between the output terminal 2 and the ground terminal 3 to which the ground voltage VSS is applied is maintained in an interrupted state. When the enable signal ENABLE transitions from a low level to a high level, a reference voltage Vref of a predetermined level (for example, 1.5 volts) is generated from the reference voltage generator 10, Is output. At this time, since the level of the high voltage Vpgm output from the high voltage pumping unit 30 is 0 volts, the first distribution voltage Vdevide1 applied to the comparison unit 50 will be applied at approximately 0 volts. Because the reference voltage Vref is higher than the first distribution voltage Vdevide1, the comparator 50 outputs a high-level comparison signal S_comp.

The driving unit 60 outputs the comparison signal S_comp at a high level and the driving signal S_driv at a high level in response to the enable signal ENABLE. The oscillation unit 20 receiving the drive signal S_driv of high level outputs the oscillation signal S_osc of the first period F0. Thereby, the high voltage pumping unit 30 performs a high voltage pumping operation and starts to output a high voltage Vpgm at which the voltage level rises as the pumping operation proceeds. The first control unit 70, which receives the comparison signal S_comp and the enable signal ENABLE at the same time that the driving unit 60 outputs the driving signal S_driv of a high level, and outputs a first control signal S_cont1 of a high level. The switching transistor Ml of the first voltage distributor 40 is enabled by the first control signal S_cont1 of a high level to be connected between the output terminal 2 and the ground terminal 3, .

The first distributed voltage Vdevide1, which detects and converts the first high voltage Vpgm ', which is lower than the desired high voltage level by a predetermined level, is supplied with the same voltage as the reference voltage Vref output from the reference voltage generator 10 The values of the resistors R1 and R2 of the first voltage divider 40 are set. Accordingly, when it is sensed that the high voltage Vpgm output from the high voltage pumping unit 30 through the first voltage distributor 40 is pumped to the first high voltage Vpgm ', the comparing unit 50 And a low level comparison signal S_comp is output. The driving unit 60 temporarily outputs the driving signal S_driv transited from a high level to a low level. The first controller 70 also outputs a low level first control signal S_cont1 to disable the first voltage divider 40. [ At this time, since the first controller 70 is composed of the NAND gates G2 and G3, which are latched to each other, the first control unit 70 operates as a 1-bit cell storage unit, S_cont1).

The first control signal S_cont1 of the low level and the enable signal ENABLE of the high level cause the NAND gate G4 of the second control unit 80 to output the high level the second control signal S_cont2 of the high level is output and the second voltage divider 42 is enabled. The values of the resistors R3 and R4 are set so that the second distribution voltage Vdevide2 output from the second voltage distributor 42 can sense the desired high voltage level. The oscillation unit 20 receives the second control signal S_cont2 of high level output from the second control unit 80 and outputs the second control signal S_cont2 to the first period The oscillation signal S_osc having the second period F1 which is longer than the oscillation signal S_osc of the first oscillation signal F0 by a predetermined time is output. Thus, the second voltage divider 42 outputs the second divided voltage Vdevide2 having the same voltage level as the reference voltage Vref when the high voltage Vpgm is pumped to a desired voltage level.

In other words, the NMOS transistor M3 of the second charging means 25 of the oscillating unit 20 is turned on by the second control signal S_cont2 of a high level to turn on the second charging means 25 And the capacitor C1 of the first charge means 24 are connected in parallel to increase the charge and discharge time. Thus, the high-voltage pumping unit 30 outputs a high voltage whose high-voltage capacity is reduced by the oscillation signal S_osc having a long oscillation period. When the high voltage continuously pumped by the oscillation signal S_osc having the second period F1 is pumped to a desired voltage level, the second voltage divider 42 generates a voltage Vref equal to the reference voltage Vref Level second distribution voltage Vdevide2. The comparator 50 receiving the second distribution voltage Vdevide2 outputs a low level comparison signal S_comp to disable the oscillation unit 50. [

Is pumped to the first high voltage Vpgm ', which is lower than the desired high voltage Vpgm by a predetermined level, by the oscillation signal S_osc having the first period F0, as shown in Fig. At this time, the first voltage divider 40 is disabled and the second voltage divider 42 is enabled. Thus, the second charging means 25 of the oscillating unit 20 is enabled to output the oscillation signal S_osc having the second period F1 which is longer than the first period F0 by a predetermined time. The oscillation signal S_osc having the second period F1 performs the pumping operation by the high voltage pumping unit 30 but the amount of the pumping signal S_osc compared to the oscillation signal S_osc having the first period F0, This results in a small high voltage. As a result, the ripple phenomenon caused by the high voltage level sensing delay can be reduced, and the overall high voltage error can be reduced.

As described above, a desired high voltage can be obtained through the oscillation signal having the second period longer than the first period by pumping the oscillation signal having the first period to the first high voltage level. As a result, the pumping capacity of the high voltage pumped for the sensing delay time is reduced by the oscillation signal having the second period, and the voltage to be ripple is reduced. Accordingly, the overvoltage and undervariation of the nonvolatile semiconductor memory device can be prevented by reducing the high voltage error occurring during the sensing delay time, and the program performance can be improved.

Claims (18)

A reference voltage generator 10 for generating a reference voltage Vref of a predetermined level in response to an enable signal ENABLE applied from the outside; And receives a pulse signal S_osc having a first period F0 in response to the drive signal S_driv in response to the enable signal ENABLE, a predetermined drive signal S_driv and a predetermined control signal S_cont2, An oscillation unit 20 for outputting the pulse signal S_osc having a second period F1 that is longer than the first period F0 by a predetermined time in response to the control signal S_cont2 after outputting the pulse signal S_osc; A high voltage pumping unit 30 generating a high voltage Vpgm in response to the oscillation signal S_osc output from the oscillation unit 20; (Vpgm ') output from the high-voltage pumping unit (30) and responsive to a predetermined control signal (S_cont1), the high voltage (Vpgm) is lowered to a voltage level A first voltage distributor 40 for sensing whether the voltage is pumped and outputting a first distribution voltage S_device1 converted to a predetermined level; And a control unit for receiving the high voltage Vpgm output from the high voltage pumping unit 30 and detecting whether the high voltage Vpgm is pumped to a desired voltage level in response to the control signal S_cont2, A second voltage distributor 42 for outputting a second distribution voltage S_devide2; The reference voltage Vref output from the reference voltage generator 10 and the first and second distribution voltages S_devide1 and S_devide2 output from the first and second voltage distributor 40 and 42, A comparator 50 for receiving a comparison signal S_comp at a predetermined level obtained by comparing the reference voltage Vref with the first and second divided voltages S_devide1 and S_devide2; A driving unit 60 for outputting the driving signal S_driv applied to the oscillation unit 20 in response to the enable signal ENABLE and the comparison signal S_comp; A first control unit 70 for outputting the first control signal S_cont1 applied to the first voltage distributor 40 in response to the enable signal ENABLE and the comparison signal S_comp; And outputs the second control signal S_cont2 applied to the second voltage distributor 42 and the oscillator 20 in response to the first control signal S_cont1 and the enable signal ENABLE. 2 high voltage generating circuit of a nonvolatile semiconductor memory device including a control section (80). The method according to claim 1, The reference voltage generating unit 10 includes a plurality of resistors R5 and R6 and a plurality of MOS transistors M4 to M6. The method according to claim 1, The oscillation unit 20 includes a plurality of delay means 22 connected in series to receive the oscillation signal S_osc and delay it for a predetermined time; An output for outputting the oscillation signal S_osc in response to the predetermined signal output from the delay unit 22 at the last stage of the delay means 22, the drive signal S_driv, and the enable signal ENABLE, (26). ≪ Desc / Clms Page number 13 > The method of claim 3, Each of the delay means (22) includes an inversion means (23) for inverting a signal output from the previous stage; First charging means 24 for determining the first period F0 of the oscillation signal S_osc by discharging the signal or discharging the signal in response to a predetermined signal outputted from the inverting means 23, and; A second period (F1) of the oscillation signal (S_osc) is determined by charging a predetermined signal outputted from the inversion means (23) or discharging the charged signal in response to the second control signal (S_cont2) 2 charge means (25). 5. The method of claim 4, The inverting means (23) of each delay means (22) is provided with an inverter (I3), and the high voltage generating circuit of the nonvolatile semiconductor memory device. 5. The method of claim 4, The first charge means (24) of each delay means (22) is provided as a capacitor means (C1). 5. The method of claim 4, The second charging means (25) comprises switching means (M3) switched in response to the second control signal (S_cont2); And a capacitor means (C2) for charging a predetermined signal transferred through the switching means (M3) or for discharging the charged signal through the switching means (M3). 8. The method of claim 7, Wherein the switching means (M3) is a n-channel conduction type MOS transistor. The method of claim 3, Wherein said output means (26) comprises a 3-input NAND gate (G5). The method according to claim 1, The high voltage pumping unit 30 includes a plurality of MOS transistors M7 to M13, capacitors C3 to C8, and an inverter I7. The method according to claim 1, The first voltage divider (40) comprises resistance means (R1, R2) and switching means (M1). 12. The method of claim 11, Wherein the switching means (M1) comprises an n-channel conductivity type MOS transistor enabled in response to the first control signal (S_cont1). The method according to claim 1, The second voltage divider (42) comprises resistance means (R3, R4) and switching means (M2). 14. The method of claim 13, Wherein the switching means (M2) comprises an n-channel conduction type MOS transistor enabled in response to the second control signal (S_cont2). The method according to claim 1, The comparator (50) comprises a plurality of PMOS transistors (M14, M15) and a plurality of NMOS transistors (M16 - M18). The method according to claim 1, The driving unit 60 includes a NAND gate G1 and an inverter I1. The high voltage generating circuit of the nonvolatile semiconductor memory device includes: The method according to claim 1, The first control unit (70) is provided with the latched NAND gates (G2, G3). The method according to claim 1, The second control unit 80 includes a nonvolatile semiconductor memory (not shown) having a NAND gate G4 for outputting the second control signal S_cont2 in response to the enable signal ENABLE and the first control signal S_cont1, The high voltage generating circuit of the device.