KR100223351B1 - Separable video camera - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video camera suitable for connecting a digital storage device or a data compression LSI, wherein the camera head can be freely exchanged and connected to a camera control unit, and any combination of various camera heads including different numbers of pixels can be used. Can be connected to a signal processing device operating at an arbitrary horizontal scanning frequency and can supply video signals to the signal processing device with a small number of cables. A synchronous signal indicating the pixel period of the image pickup device in the camera head by storing the data to be stored in the ROM, a built-in ROM in the camera head, and a variable gain circuit for changing the level of the iris control circuit or the output signal. With the horizontal and vertical positions The camera head is provided with a means for superimposing synchronizing signals and an analog interface for outputting a video signal before superimposed color separation, and an operating frequency of an image pickup device or a camera signal processing circuit in the camera when the video camera is connected to an external signal processing device. Means for setting the frequency to an integer multiple of the horizontal scanning frequency of the signal processing apparatus, and accommodating the image pickup device and the means for generating timing pulses for driving the image pickup device in a first housing portion (camera head) and A camera signal processing circuit for processing an output signal to generate a video signal and a signal processing device for processing or processing the video signal are housed in a second housing physically separated from the first housing. The output signal of the image pickup device sent through the transmission line by connecting the housing part with a transmission line such as a cable is a pixel. Call that was configured that an analog signal are sequentially arranged.

With this configuration, the signal level at the connection between the camera head and the control unit can be kept constant regardless of the camera head, so that the sensitivity deviation can be suppressed and a new signal type analog interface different from the existing TV signal can be obtained. It is possible to realize a video camera having a video signal, to reduce the number of wires between the camera head and the control unit, to reduce the number of wires between the camera head and the control unit, and to signal processing apparatus of any horizontal scanning frequency. Can be connected to a video camera, and the number of cables can be reduced significantly compared with the case of digital transmission.

Description

Detachable Video Camera

1 is a diagram showing an example of a video camera of the present invention.

2 is a diagram showing another example of the video camera of the present invention.

3 is a diagram showing an application example using the video camera of FIG.

4 is an external view showing an application example using the video camera of FIG.

5 is a diagram showing one example of a camera head used in the present invention.

6 shows another example of a camera head used in the present invention.

Fig. 7 is a diagram showing one example of pixel arrays of an image pickup device used in the video camera of the present invention.

8 is a diagram showing an example of a camera head in which a synchronization signal is superimposed on an output signal of an image pickup device according to the present invention.

9 is a diagram showing an output signal of an image pickup device used in the present invention and a signal representing a pixel period.

10 is a diagram showing a signal in which a synchronization signal and a signal representing a pixel period are superimposed on an output signal of an imaging device and an output signal of the imaging device used in the present invention.

FIG. 11 is a diagram showing another example of a camera head in which a synchronization signal is superimposed on an output signal of an image pickup device according to the present invention. FIG.

12 is a view showing another example of a camera head in which a synchronization signal is superimposed on an output signal of an image pickup device according to the present invention.

FIG. 13 is a diagram showing an example of the control data control unit in FIG. 12; FIG.

FIG. 14 is a diagram showing an example of input data, a transmission clock, and a load pulse in the control data control unit of FIG.

FIG. 15 shows an example of the operation of the decoder circuit of FIG.

FIG. 16 is a configuration diagram showing another example of the control data control unit in FIG.

17 is a diagram showing another example of the video camera of the present invention.

18 illustrates the operation of the jitter prevention circuit in the video camera of FIG.

Drawing to make.

19 is a diagram showing another example of the video camera of the present invention.

20 is a diagram showing another example of the video camera of the present invention.

FIG. 21 is a diagram showing waveforms of output signals of the camera head section in FIG. 20; FIG.

22 is a diagram showing another example of the video camera of the present invention.

23 is a diagram showing another example of the video camera of the present invention.

24 is a diagram showing another example of the video camera of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video camera suitable for connecting a digital memory device or a data compression LSI, and more particularly to a video camera in which a camera head having a lens and an image pickup device is separated from a main body having a signal processing circuit or the like.

Conventional discrete video cameras include CCD Micro-Miniature Color Camera, IEEE Trans., CE-33,2, pp. As described in 85 (1987), a housing portion (hereinafter referred to as a camera control unit) including a signal processing circuit and another housing portion (hereinafter referred to as a camera head) including an imaging device were always used as a pair. . Even if the imaging device is of the same type, there is a variation in electrical characteristics for each imaging device. Therefore, if the camera head assembled with one camera control unit is connected to another camera control unit, the image quality is deteriorated. In addition, camera heads using different types of image pickup devices such as image pickup devices having different number of pixels could not be connected together. Therefore, it was not possible to switch images or combine images by connecting several camera heads to one camera control unit. For this reason, in the prior art, it is not possible to freely exchange (replace) cameraheads or to connect multiple cameraheads.

On the other hand, a conventional video camera captures only one frequency determined by the television (TV) method employed in the video camera, as described in the New Publication, ICD 91-99, pp. 9-14 (September 1991). Since the device was driven, only the video signal of the horizontal scanning frequency determined by the TV system could be generated. Therefore, when a conventional video camera is used as a means for inputting information into a signal processing device such as a personal computer or a display device, it cannot be connected if the horizontal scanning frequency of the video camera and the horizontal scanning frequency of the signal processing device are different. In addition, when both the camera signal processing circuit which processes the output signal of the image pickup device in the video camera and the above-described signal processing device process the signal digitally, the digital camera of the parallel bit configuration is used as the signal processing device in the video camera. Since the signal is transmitted, very many cables are needed to connect the video camera and the signal processing apparatus.

A first object of the present invention is to provide a detachable video camera which can be freely exchanged with a simple camera head having only a lens, an image pickup device, a driving circuit, a synchronization signal generator, an adder, and the like and connected to a camera control unit.

A second object of the present invention is to provide a detachable video camera that can freely combine a plurality of camera heads having different numbers of pixels and the like by connecting the camera head and the camera control unit through a common interface. will be.

A third object of the present invention is to provide a video camera which can be connected to a signal processing apparatus such as a personal computer or a display device operating at an arbitrary horizontal scanning frequency.

A fourth object of the present invention is to provide a video camera capable of supplying a video signal to a signal processing device such as a personal computer or a display device with a small number of cables.

In order to achieve the first object, the present invention stores ROM (lead-only memory) data inherent in the image pickup device or the camera head, and the data indicating the electrical characteristics of the camera head, and incorporates the ROM into the camera head. Therefore, the sensitivity data or the deviation data for each color separation filter of the image pickup device and the data of the type or arrangement of the color separation filter are held in the ROM embedded in the camera head, and the camera control unit reads these data from the camera head or Since this data can be transferred to the control unit, accurate color reproduction can be achieved even if the camera head is replaced. Similarly, since the number of pixels, aspect ratio, and driving frequency of the image pickup device are also maintained in the ROM, camera heads having a different number of pixels can be connected. In order to reduce the deviation of the camera head itself, the camera head has a built-in variable gain circuit for changing the level of the iris control circuit and the output signal. Therefore, the signal level at the connection between the camera head and the control unit can be made constant regardless of the camera head, so that the sensitivity deviation can be suppressed.

In order to achieve the second object, the present invention provides a means for superimposing a synchronizing signal representing a pixel period of the imaging device on an output signal from the imaging device. For example, by providing a means for superimposing a signal up and down (up and down) for each pixel in a horizontal retrace period for several cycles, and changing the signal fetch timing and the like on the camera control unit side in accordance with the waveform of this synchronization signal. As a result, the correct level for each pixel of the image pickup device can be supplied to the camera control unit. Further, by providing a means for superimposing the synchronization signals indicating the positions in the horizontal and vertical directions in the horizontal and vertical retrace periods, the horizontal synchronization and the vertical synchronization of the camera head and the camera control unit can be matched. By providing an analog interface in the camera head in which the synchronizing signal indicating the pixel period and the horizontal and vertical synchronizing signals are superimposed on the output of the image pickup device, a new signal different from the existing TV signal.

A video camera with an analog interface can be realized. In addition, since the color signals are not separated from the signals of the analog interface, the number of wirings of the camera head and the control unit can be reduced. In addition, since the camera head and the control unit can be driven by different oscillation circuits, there is no need to send a high-speed pulse from the control unit to the camera head or from the camera head to the control unit. In the case where the synchronizing signal indicating the pixel period is a rising / falling signal for each pixel, the frequency of the synchronizing signal becomes the same as the carrier frequency of the color signal output from the image pickup device, so that the synchronizing signal is controlled at the phase where the maximum amplitude is obtained. When the unit fetches a signal, it has the effect that an accurate signal level for each pixel of the image pickup device can be obtained.

In order to achieve the third object of the present invention, when the video camera is connected to an external signal processing device such as a personal computer or a display device, the operating frequency of the image pickup device or camera signal processing circuit in the camera is processed by the signal processing. Means were set for setting the frequency to an integer multiple of the horizontal scanning frequency of the apparatus. Therefore, since the image pickup device and the camera signal processing circuit in the video camera can be operated at an integer multiple of the horizontal scanning frequency of the signal processing device, the synchronization is not disturbed. Therefore, a signal processing device of any horizontal scanning frequency can be connected to the video camera.

In order to achieve the fourth object, the present invention accommodates an image pickup device and means for generating timing pulses for driving the image pickup device in a first housing portion (camera head), and processes an output signal of the image pickup device. A camera signal processing circuit for generating a video signal and a signal processing device for processing or processing the video signal are housed in a second housing which is physically separated from the first housing. The parts were connected by transmission lines such as cables. The output signal of the image pickup device sent through this transmission line is an analog signal in which pixel signals are arranged in a sequential order. Therefore, even if the camera signal processing circuit and the signal processing apparatus operate by digital processing, since they are integrated in one housing, it is not necessary to provide a cable or the like between them. In addition, since the camera signal processing circuit and the signal processing apparatus are housed in a housing separate from the camera head, the camera head becomes light and easy to use, and the signals transmitted therebetween are signals in which pixel signals are arranged in sequential order. Therefore, the number of transmission channels is small. Therefore, the number of cables can be significantly reduced as compared with the case of digital transmission.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram showing an example of a video camera of the present invention. This video camera consists of a camera head 1, a camera control unit 2 and cables 5a, 5b, 5c and 5d connecting them. The camera head 1 includes an imaging device 20, a CDS circuit 21, a driving circuit 22, a data interface 23, and an EEPROM 24. On the other hand, the camera control unit 2 includes an A / D converter 50, a luminance signal generating circuit 51, a color signal generating circuit 53, a gamma circuit 52, 72, 73, 74, And a signal processing circuit 54, a microcomputer 55, and a power supply circuit 56.

The output of the image pickup device 20 driven by the drive circuit 22 is connected to the input of the CDS circuit 21. The output of the CDS circuit 21 is connected to the input of the A / D converter 50 via a cable 5a. The output of the A / D converter 50 is connected to the inputs of the luminance signal generating circuit 51 and the color signal generating circuit 53. The output of the luminance signal generation circuit 51 is connected to the input of the gamma circuit 52. The output of the gamma circuit 52 is output to the outside through the output terminal 11. The three outputs of the color signal generation circuit 53 are connected to the inputs of the gamma circuits 72, 73 and 74, respectively. Outputs of the gamma circuits 72, 73 and 74 are connected to the inputs of the signal processing circuit 54. The output of the signal processing circuit 54 is output to the outside through the output terminal 12. The microcomputer 55 is connected to the luminance signal generating circuit 51, the color signal generating circuit 53 and the signal processing circuit 54, and is connected to the input of the data interface 23 via the cable 5b. The two outputs of the data interface 23 are connected to the drive circuit 22 and the EEPROM 24. The power supply circuit 56 is connected to the imaging device 20, the CDS circuit 21, the drive circuit 22, the data interface 23 and the EEPROM 2 via the cables 5c and 5d.

Supply power to 4).

FIG. 7A is a diagram showing an example of the pixel arrangement of the image pickup device used in the video camera of FIG. The signal obtained by the image pickup device 20 is subjected to noise reduction processing by the CDS circuit 21. In the case where the imaging element of the pixel array shown in FIG. 7A is used, the signal of the point sequence of (G + Cy) and (Mg + Ye) and (Mg + Cy) and (G + Ye) shown in FIG. Point sequential signal is output from the camera head, and this signal is converted into a digital signal by the A / D converter 50. The luminance signal generating circuit 51 generates a luminance signal from this digital signal, while the color signal generating circuit 53 performs color separation from this digital signal to generate red, blue and green color signals. The gamma circuits 52, 72, 73, and 74 correct the nonlinear characteristics of the CRT on these luminance and color signals. The signal processing circuit 54 generates a color difference signal from the red, blue, and green signals after the gamma processing. The luminance signal and the color difference signal after the gamma processing are output through the output terminals 11 and 12 as digital signals. In addition, the microcomputer 55 controls the luminance signal generating circuit 51, the color signal generating circuit 53, and the signal processing circuit 54, and is stored in the EEPROM 24 via the data interface 23. Data is read, new data is written, or the driving circuit 22 is controlled. Using this video camera, the small camera head and the camera control unit can be connected with a small number of cables. Therefore, even when the digital signal processing circuit of the camera is incorporated in the personal computer, the shooting direction can be set regardless of the position of the personal computer. A system that can be freely set can be easily realized.

On the other hand, the EEPROM 24 built in the camera head 1 has data unique to the camera head, for example, data indicating gain for each color separation filter of the imaging device, data indicating the number of pixels of the imaging device, and aspect ratio of the imaging device. Data indicating the order of data, data indicating the sequence number of the color separation filter of the image pickup device, and the like. This stored data is transmitted to the microcomputer 55 via the cable 5b and the data interface 23, and the microcomputer 55 according to this data is the luminance signal generating circuit 51 and the color signal generating circuit 53. And the signal processing circuit 54. Therefore, even when the camera head is replaced with another head, color reproducibility and luminance reproducibility are not impaired. In addition, the camera control unit 2 supplies power to the camera head 1 via (5c) and (5d). Therefore, it is not necessary to incorporate an extra power supply circuit in the camera head 1. In this video camera, EEPROM is used as a storage medium. Any nonvolatile memory can be used as long as it does not write data to the camera head 1, and for example, EPROM can be used.

2 is a view showing another example of the video camera of the present invention. This video camera consists of a camera head 1, a camera control unit 2 and cables 5a, 5b and 5c connecting them. The camera head 1 includes an image pickup device 20, a CDS circuit 21, an AGC circuit 26, a drive circuit 22, a data interface 23, an EEPROM 24, a DD (direct current-direct current) converter ( 25), a level detection circuit A (34). Here, the D. D. converter refers to a converter that generates another DC voltage at an arbitrary direct current (DC) voltage, for example, to generate a DC voltage of 10V at a DC voltage of 3V. On the other hand, the camera control unit 2 includes an A / D converter 50, a luminance signal generating circuit 51, a color signal generating circuit 53, a gamma circuit 52, 72, 73 and 74, And a signal processing circuit 54, a microcomputer 55, a power supply circuit 56, a modulation circuit 61, and D / A converters 66 and 60. The output of the image pickup device 20 driven by the drive circuit 22 is connected to the input of the CDS circuit 21. The output of the CDS circuit 21 is connected to the input of the AGC circuit 26. The output of the AGC circuit 26 is connected to the input of the A / D converter 50 via the input of the level detection circuit 34 and the cable 5a. The output of the level detection circuit A 34 is connected to the gain variable terminal of the AGC circuit 26. The output of the A / D converter 50 is connected to the inputs of the luminance signal generating circuit 51 and the color signal generating circuit 53. The output of the luminance signal generation circuit 51 is connected to the input of the gamma circuit 52. The output of the gamma circuit 52 is connected to the input of the output terminal 11 and the D / A converter 60, and the output of the D / A converter 60 is connected to the output terminal 9. On the other hand, the three outputs of the color signal generation circuit 53 are connected to the inputs of the gamma circuits 72, 73 and 74, respectively. Outputs of the gamma circuits 72, 73, and 74 are respectively connected to the inputs of the signal processing circuit 54. The output of the signal processing circuit 54 is connected to the input of the output terminal 12 and the modulation circuit 61. The output of the modulation circuit 61 is connected to the input of the D / A converter 66 and the output of the D / A converter 66 is connected to the output terminal 10. The microcomputer 55 is connected to the luminance signal generating circuit 51, the color signal generating circuit 53 and the signal processing circuit 54, and is connected to the input of the data interface 23 via the cable 5b. Three outputs of the data interface 23 are connected to the driving circuit 22, the EEPROM 24 and the AGC circuit 26. The power supply circuit 56 is connected to the D. D. converter 25 via a cable 5c. The DD converter 25 includes an imaging device 20, a CDS circuit 21, an AGC circuit 26, a drive circuit 22, a data interface 23, an EEPROM 24, and a level detection circuit A 34. ) And a clock is supplied from the driving circuit 22.

The signal obtained from the image pickup device 20 is subjected to noise reduction processing by the CDS circuit 21, the signal level is uniformly adjusted by the AGC circuit 26, and converted into a digital signal by the A / D converter 50. do. The luminance signal generating circuit 51 and the color signal generating circuit 53 generate the luminance signal and the red, blue, and green color signals from this digital signal. The gamma circuits 52, 72, 73 and 74 correct these nonlinear characteristics of the CRT on these signals. The signal processing circuit 54 generates a color difference signal from the red, blue, and green signals after the gamma processing, and outputs the luminance signal and the color difference signal after the gamma processing through the output terminals 11 and 12 as digital signals. On the other hand, the digital color difference signal is modulated by the modulation circuit 61, and the modulated signal and the luminance signal are converted into analog signals by the D / A converters 66 and 60 to output the output terminal 10 and It is output through (9). In addition, the microcomputer 55 controls the luminance signal generating circuit 51, the color signal generating circuit 53, and the signal processing circuit 54, and is stored in the EEPROM 24 via the data interface 23. Data may be read or new data may be read or the driving circuit 22 and the AGC circuit 26 may be controlled.

Since the camera head 1 incorporates the D. D. converter 25, the wiring of the power supply supplied from the camera control unit 2 can be reduced. In addition, since the camera control unit 2 has a modulation circuit 61 and D / A converters 60 and 66, it is possible to output a standard analog signal. Since the camera head 1 has the level detection circuit A 34, the output signal level can be made constant. Therefore, in addition to the effect equivalent to that of FIG. 1, the video camera is provided with a clock of the DD converter so that bit interference can be prevented and a standard analog signal is output. Even when a data compression circuit or a data storage circuit is connected, the captured image can be projected (displayed) on a TV monitor.

3 is a diagram showing the configuration of an imaging system using the video cameras of FIGS. The system of FIG. 1 consists of a camera head 1 and an imaging device main body 80, and a camera gun control unit 2 is included in the imaging device main body 80. As shown in FIG. The imaging device main body 80 further includes a data compression circuit 81 and a recording circuit 82. The output of the camera head 1 corresponds to the cable 5 ((5a), (5b), (5c), (5d) in FIG. 1, and (5a), (5b), (5c) in FIG. ) Is connected to the input of the camera control unit 2. The camera control unit 2 outputs analog luminance signals and modulated color signals at the output terminals 9 and 10. The output of the camera control unit 2 is connected to the input of the data compression circuit 81 and the output of the data compression circuit 81 is connected to the input of the recording circuit 82.

4 is a view showing the appearance of the apparatus to which the system of FIG. 3 is applied. In the system shown here, the analog signal output of the imaging device main body 80 shown in FIG. 3 is connected to the monitor 3. In addition, the cable 5 is detachable by the connector 4.

According to the system shown in FIG. 3 and FIG. 4, it is unnecessary to extend every digital signal line which connects the digital output of the camera control unit to a personal computer or an image compression device, or to move the personal computer or the image compression device. In addition, since the camera head is connected by a detachable connector, the camera head can be easily replaced.

5 is a diagram illustrating another example of the camera head. The camera head 1 includes an iris driving circuit 28, a lens 29, an iris 32, an imaging device 20, a CDS circuit 21, an AGC circuit 33, a position detection circuit A 32, and a level. The detection circuit A 34, the drive circuit 22, the microcomputer 36, the EEPROM 24, the power supply circuit 37, the cables 5a, 5b, and 5c are provided. Light incident through the lens 29 and the iris 32 is photoelectrically converted by the imaging device 20. The photoelectrically converted signal is input to the CDS circuit 21. The output of the CDS circuit 21 is connected to the input of the AGC circuit 33. The output of the AGC circuit 33 is connected to the cable 5a and the level detection circuit A 34. The level detecting circuit A 34 outputs a signal to the microcomputer 36 and sets its reference level by the microcomputer 36. The microcomputer 36 is connected to the iris drive circuit 28, the AGC circuit 33, the drive circuit 22, the position detection circuit A 31, the EEPROM 24 and the cable 5b. The output of the drive circuit 22 is connected to the image pickup device 20 and the CDS circuit 21. The position detection circuit A 31 detects the operation information of the iris. The power supply circuit 37 includes an iris driving circuit 28, an imaging device 20, a CDS circuit 21, an AGC circuit 33, a position detecting circuit A 31, a level detecting circuit A 34, and a driving circuit ( 22), the microcomputer 36 and the EEPROM 24 are supplied with power.

The CDS circuit 21 performs noise reduction processing on the signal obtained from the imaging device 20. The microcomputer 36 controls the gain of the iris drive circuit 28 and the AGC circuit 33 in accordance with the detection results of the level detection circuit A 34 and the position detection circuit A 31. The microcomputer 36 outputs the data unique to the camera head, for example, data representing the gain for each color separation filter of the imaging device, data representing the number of pixels of the imaging device, and the aspect ratio of the imaging device via the cable 5b. Data, data indicating an arrangement order of color separation filters of the image pickup device, and the like are read from the camera head 1. Using this camera head also has the same effect as the video camera described above. The camera head has a built-in position detection circuit A for detecting the state of the iris and a level detection circuit A for detecting the output signal level of the AGC circuit, and controls the iris and AGC circuits in accordance with the detection result. The output signal level of the head can be made constant. The camera control unit can change the reference level of the level detection circuit A or change the iris control method via a microcomputer.

6 is a diagram showing another example of the camera head. This camera head has an autofocus function added to the camera head of FIG. 5, and in addition to the components shown in FIG. 5, the lens driving circuit 27, the position detection circuit B 30, and the level. The detection circuit B 35 is provided. The output of the AGC circuit 33 is input to the level detection circuit B 35, and the outputs of the position detection circuit B 30 and the level detection circuit B 35 are input to the microcomputer 36. The microcomputer 36 controls the lens drive circuit 27 in accordance with these detection results.

On the other hand, in the present invention, since the camera head outputs an analog signal to the output signal of the image pickup device 20 without performing signal processing such as color separation, CCD imaging of the pixel array as shown in FIG. In the case of an element, the output signals of the image pickup element are output in the order of dots as (G + Cy) and (Mg + Ye) or (Mg + Cy) and (G + Ye) as shown in FIG. If signal processing is to be executed by the signal processing circuit of an external control unit which is asynchronous with the camera head, the signal processing circuit cannot determine which color component. In addition, the signal processing circuit needs to match the synchronization in the horizontal direction with the synchronization in the vertical direction.

8 is a diagram showing an example of a configuration for synchronizing them in the camera head of the present invention. In addition to the image pickup device 20 and the driving circuit 22, the camera head has a synchronization signal generation section 103, an adder 104, an analog interface 105, and a power supply interface 106. The output signal of the synchronous signal generator 103 generated according to the output signal of the imaging device 20 driven by the drive circuit 22 and the output signal of the drive circuit 22 is supplied to the adder 104. The output signal of the adder 104 is supplied to the analog interface 105. The power supply interface 106 supplies power from the unit to the camera. The synchronization signal generation unit 103 is a synchronization signal for acquiring horizontal synchronization and vertical synchronization between the camera and the camera based on the pulse signal generated by the driver circuit 22 and the pixel period of the image pickup device 20. To generate a synchronization signal. The adder 104 superimposes these synchronization signals on portions of the output signal of the image pickup device 20 that are not directly related to the image, such as during a blanking period. The output signal of the adder 104 is output to the outside via the analog interface 105.

The signal shown in Fig. 9A is the same as the output signal of the image pickup device shown in Fig. 7B. 9B is a diagram showing a synchronization signal indicating a pixel period of this signal. 10A is a diagram showing the entire image of the output signal of the imaging device. The above-described synchronization signal indicating the pixel period and the synchronization signal for synchronizing in the horizontal direction and the vertical direction are superimposed on portions not directly related to the image, such as during the blank period of the signal of FIG. The signal as shown is generated. Therefore, the image output signal of the camera head can have synchronization and pixel period information in the horizontal and vertical directions of the camera. The signal processing circuit of the control unit can use this information to match the synchronization in the horizontal and vertical directions with the fetch timing of the signal. In other words, the camera head is a camera with a new signal type analog interface different from the existing TV signal. Also, as shown in FIG. 10C, even when only the horizontal synchronizing signal and the vertical synchronizing signal are superimposed without superimposing the synchronizing signal indicating the pixel period of the imaging device 20, the phase of the pixel period is known from the horizontal synchronizing signal. Also, as shown in FIG. 10, even when only the synchronization signal indicating the pixel period is superimposed without overlapping the horizontal synchronization signal and the vertical synchronization signal, the horizontal synchronization signal and the vertical synchronization signal can be seen from the control unit side. For example, when the synchronization signal indicative of the pixel period is first raised, the horizontal synchronization is performed, and when the synchronization signal has a length of four times, it can be regarded as a vertical synchronization signal. Even in this configuration, since the analog interface signal is not separated in color, the number of wirings is reduced, and the camera head is simpler than a conventional video camera since only the imaging element, the driving circuit, the synchronization signal generator, and the adder are incorporated. .

FIG. 11 is a diagram showing the configuration of the camera head in which the CDS circuit 21 and the AGC circuit 26 are added to the configuration of the camera head in FIG.

The output signal of the image pickup device 20 driven by the drive circuit 22 is supplied to the CDS circuit 21. The output signal of the CDS circuit 21 is supplied to the AGC circuit 26. The output signal of the synchronization signal generator 103 generated in accordance with the output signal of the AGC circuit 26 and the output signal of the driving circuit 22 is supplied to the adder 104. The output signal of the image pickup device 20 is subjected to noise reduction processing by the CDS circuit 21, and controlled by the AGC circuit 26 to a constant signal level. The synchronizing signal generating section 103 is a synchronizing signal for synchronizing in the horizontal and vertical directions on the control unit side and the camera head side on the basis of the pulse signal generated by the driving circuit 22 and the pixel period of the imaging device. Generates a signal representing. The signal generated by the synchronization signal generator 103 is superimposed by the adder 104 on the output signal of the AGC circuit 26 in a part not directly related to the moving image during the blank period. The output signal of the adder 104 is output to the outside via the analog interface 105.

FIG. 12 is a diagram illustrating an example of a configuration in which a control interface 301 is provided in the embodiment of FIG. 11 and the camera head is externally controlled or information of the camera head is sent to the outside. The camera head includes an image pickup device 20, a drive circuit 22, a synchronization signal generator 103, an adder 104, an analog interface 105, a power supply interface 106, a CDS circuit 201, and an AGC circuit ( 202, a control interface 301, a focus unit 302, an iris unit 303, a ROM 304, and a control data control unit 305. The output signal of the image pickup device 20 driven by the drive circuit 22 is supplied to the CDS circuit 201. The output signal of the CDS circuit 201 is supplied to the AGC circuit 202. The output signal of the synchronous signal generator 103 generated in accordance with the output signal of the AGC circuit 202 and the output signal of the drive circuit 22 is supplied to the adder 104. The output signal of the adder 104 is supplied to the analog interface 105. The power supply interface 106 supplies power to the camera from the outside. The control interface 301 is connected to the control data control unit 305. The control data control unit 305 supplies data to the focus unit 302, the iris unit 303, the driving circuit 22, and the AGC circuit 202. On the other hand, the focus unit 302, the iris unit 303, the AGC circuit 202, and the ROM 304 supply data to the control data control unit 305.

The output signal of the image pickup device 20 is subjected to noise reduction processing by the CDS circuit 201, and is brought to a constant signal level by the AGC circuit 202. The synchronizing signal generating section 103 is a synchronizing signal for synchronizing in the horizontal and vertical directions on the control unit side and the camera head side on the basis of the pulse signal generated by the driving circuit 22 and the pixel period of the imaging device. Generates a signal representing. These synchronizing signals and signals representing the pixel periods are superimposed by the adder 104 on the output signal of the AGC circuit 202 in a portion which is not directly related to the image, such as during the blank period. The output signal of the adder 104 is output to the outside via the analog interface 105.

The focus unit 302 transmits the data of detecting the position of the lens to the control data control unit 305. The control data control unit 305 controls the focus motor of the focus unit 302 in accordance with the data. On the other hand, the iris part 303 sends the data which detected the iris opening degree to the control data control part 305. FIG. The control data control unit 305 controls the iris in accordance with the data and changes the amount of incident light of the imaging device. The output signal of the AGC circuit 202 is sent to the control data control unit 305. The control data control unit 305 controls the gain of the AGC circuit 202 in accordance with the data. In addition, the control data control unit 305 controls the driving circuit 22 to control the accumulation time, the lead interval, and the read frequency of the charge of the imaging device 20, in particular. In addition to this, the control data control unit 305 uses the focus unit 302, the iris unit 303, the AGC circuit 202, and the drive circuit 22 based on external control data according to scene determination results. Change the behavior of).

The ROM 304 holds data unique to the imaging device. The data unique to the imaging device are, for example, the number of pixels, the aspect ratio, the spectral characteristics of the color filter, the gain matrix coefficient when generating the RGB signal with respect to the sensor output, and the variation of the characteristics as described above. In addition, the ROM 304 may hold only data indicating the type of the imaging device 20. The data of the ROM 304 is supplied to the control data control unit 305. The control data controller 305 outputs the data of the ROM 304 to the outside via the control interface 301.

By using this camera head, as a result of performing detailed new judgment or the like on the control unit side, it is possible to control the camera head from the control unit side when it is determined that it is better to change the control data inside the camera. Also, similar to the video cameras shown in FIGS. 1 and 2, the data unique to the imaging device is maintained. Therefore, even if the camera head is replaced, the control unit can read this data to cope with differences in camera types, characteristic variations, and the like. There is a number. In addition, the object to control does not need to be all of the above-mentioned things, and other things may be sufficient.

FIG. 13 is a diagram showing a detailed configuration of the control data control unit 305 provided in the camera head of FIG. The control data control unit 305 includes a clock input terminal 401 for transmission, a terminal 402 for input data, a serial-parallel conversion circuit 404, a decoder circuit 406, a latch circuit 407, 408, 409 and 410, AGC circuit control data output terminal 411, drive circuit control data output terminal 412, iris part control data output terminal 413, autofocus control data output terminal 414, ROM Data input terminal 415, parallel-to-serial conversion circuit 416, output data terminal 417, load pulse input terminal 418, iris part position detection data input terminal 419, autofocus part position detection data input A terminal 420, a microcomputer 421, a selector 422, and a signal level detection data input terminal 423 are provided.

The clock input terminal 401 for transmission is connected to the serial-parallel conversion circuit 404 and the parallel-serial conversion circuit 416. The input data terminal 402 is connected to the series-parallel conversion circuit 404. The load pulse input terminal 418 is connected to the decoder circuit 406. Output data of the serial-parallel conversion circuit 404 is supplied to the latch circuits 407, 408, 409, 410 and the decoder circuit 406. The output data of the decoder circuit 406 is supplied to the latch circuits 407, 408, 409, 410, the parallel-to-serial conversion circuit 416, and the selector 422. Output data of latch circuits 407, 408, 409, 410, data of iris part position detection data input terminal 419, data and signal level of autofocus part position detection data input terminal 420 The data of the detection data input terminal 423 is supplied to the microcomputer 421. On the other hand, the microcomputer 421 includes an AGC circuit control data output terminal 411, a drive circuit control data output terminal 412, an iris control data output terminal 413, an autofocus control data output terminal 414, and a selector. Supply data to 422. The ROM data input terminal 415 is connected to the selector 422. The output data of the selector 422 is supplied to the parallel-serial conversion circuit 416. The output data of the parallel-serial conversion circuit 416 is supplied to the terminal for output data.

FIG. 14 shows an example of signals and data inputted to the transmission clock input terminal 401, the input data terminal 402, and the load pulse input terminal 418. FIG. As shown in Fig. 14, input data is transmitted serially in accordance with the transmission clock. The transmitted input data is serial-parallel converted by the serial-parallel conversion circuit 404 and separated into control data and address data.

FIG. 15 shows an example of an address of the decoder circuit 406. The address data is 8 bits and the control data is 4 bits. The camera address is an address indicating to which camera the control signal is sent by the external signal processing device when a plurality of cameras are connected to an external signal processing device. For example, (a8, a7, a6, When a5) = (0,0,0,0), camera # 1 is represented, and when (a8, a7, a6, a5) = (0,0,0,1), camera # 2 is represented. The function address is an address indicating which part of the camera the control data is sent to. For example, if (a4, a3, a2, a1) = (0, 0, 0, 0), the AGC circuit is used. , (a4, a3, a2, a1) = (0, 0, 0, 1) indicates a driving circuit.

Only the latch circuit designated by the address data among the latch circuits 407, 408, 409, and 410 latches the serial-to-parallel input data when the load pulse falls and supplies the data to the microcomputer. do. The microcomputer 421 controls the iris unit, the autofocus unit, and the AGC circuit by the position detection data of the iris unit, the position detection data of the autofocus unit, and the signal level detection data, which are usually data inside the camera. On the other hand, when it is determined that the control data has been changed on the control unit side by detailed new judgment or the like, the iris unit, autofocus unit and AGC circuit are directly controlled by the control signal input from the control unit side. The microcomputer 421 also supplies data of the internal state of the camera head to the selector 422. The data of the R0M data and the internal state of the camera head are selected by the selector 422 only when respective lead addresses are specified, and are converted in parallel-serial and are output in series at the output data terminal.

As described above, the camera head normally executes control independently of the camera head. However, the camera head can be further controlled by inputting control data on the control unit side. In addition, since the part to be controlled and the camera to be controlled are specified by the address data, the control data lines can be used in common, and since the control data are inputted and outputted in series, the number of lines connected to the control interface can be reduced.

FIG. 16 is a diagram showing a configuration in which the load pulse 418 in the camera head shown in FIG. 13 is removed. In this camera head, when control data is input for the prescribed number of bits, the data is automatically latched. Therefore, the number of wires connected to the control interface by the load pulse can be reduced.

17 is a block diagram showing another example of a video camera according to the present invention. This video camera consists of a camera head unit 1 and a digital signal processing apparatus (camera control unit) 2, which are connected by a signal transfer unit. The video camera includes an image pickup device 20, a drive pulse output section 22 for generating drive pulses for driving the same, and a fixed oscillation section 608, and a camera head section 1 for storing them in one housing; The camera signal processor 603 is divided into a camera signal processor 603 which processes the output signal of the camera head 1 and generates a video signal. In addition, the camera signal processing unit 603 forms a digital signal processing apparatus 2 together with a signal processing apparatus 604 that uses a video signal generated and output, and the digital signal processing apparatus 2 includes a camera head unit ( It is housed in one housing different from the housing which accommodated 1). The two housings are connected by a signal transmission unit (cable, etc.) 5 and a signal is transmitted from the camera head 1 to the digital signal processing apparatus 2 via the signal transmission unit 5. Delivered. The digital signal processor 2 includes a camera signal processor 603, a signal processor 604, an A / D (analog / digital) converter 50, a luminance signal generator 51, and a color difference signal generator 53 ), Jitter prevention unit 612, interpolation circuit 613, phase detection unit 614, Vco (voltage controlled oscillator) 615, clock output unit 616, phase detection unit 617 and Vco (618) Has As the signal processing device 604, a device such as a personal computer, a display device, a memory, etc., which is conventionally connected to an image pickup device and processes or processes the output image signal thereof, has been used. However, this video camera is integrated with the camera signal processing unit 603. It is stored in one housing, and is connected to the camera head part 1 by the signal transmission part 5. This signal transmission section is detachable.

Here, when the horizontal scan frequency of the camera head unit 1 is fh, the driving pulse output unit 22 outputs the vertical synchronizing signal VS and the horizontal synchronizing signal HS of the horizontal scanning frequency fh and the frequency n at the output of the fixed oscillator 608. Generate an operating clock of xfh. Provided that n is any positive integer. The imaging device 20 operates by these horizontal and vertical synchronization signals and an operation clock. In the image pickup device 20, for example, as shown in Fig. 7A, pixels of each color are arranged for each horizontal line. By sequentially reading the signals of the respective pixels of the image pickup device 20 as described above, the analog signals of the point sequence in which the pixel signals G + Cy and the pixel signals Mg + Ye are alternately arranged at a frequency n × fh. At the frequency n and fh, the analog signal of the point sequence in which the pixel signals Mg + Cy and the pixel signals G + Ye are alternately arranged is output from the imaging element 20 alternately for each field. The analog signal A is supplied to the camera signal processing unit 603 of the digital signal processing apparatus 2 via the signal transmission unit 5 together with the vertical synchronization signal VS and the horizontal synchronization signal HS. The camera signal processor 603 converts the supplied analog signal A into a digital signal B by the A / D converter 50, and the digital signal is converted into the luminance signal generator 51 and the color difference signal generator 53. The digital luminance signal Y and the digital color difference signal C are generated. These are supplied to the jitter prevention portion 612.

On the other hand, the oscillation frequency of the Vco 615 is variable over a wide range. The output of this Vco 615 is supplied to the clock output part 616, and the operation clock D of frequency nxfh is produced | generated by processing, such as division. This operation clock D is supplied to the phase detection unit 614, and divided by n to detect a phase error with the horizontal synchronization signal HS from the camera head unit 1. As shown in FIG. The oscillation frequency or phase of the Vco 615 is controlled by the detection output of the phase detection unit 614 so that this phase error is eliminated. As a result, the operation clock D has the frequency exactly equal to n times the horizontal scanning frequency fh, and the phase is synchronized with the horizontal synchronization signal HS so that the timing with each pixel signal of the analog signal A from the image pickup device 20 is increased. Will match. This operation clock D is supplied to the A / D conversion section 50 as a sampling pulse and to the luminance signal generating section 51 and the chrominance signal generating section 53 as timing pulses.

The camera signal processing unit 603 is supplied with a horizontal synchronization signal HS 'used therein from the signal processing device 604, and is phased with the horizontal synchronization signal HS from the camera head unit 1 by the phase detection unit 617. An error is detected. Vco 618 is variable in oscillation frequency over a wide range, and its output is a horizontal synchronous signal HS 'used in the signal processing apparatus 604. In this Vco 618, the oscillation frequency and phase are controlled by the detection output of the phase detector 617 so that the above phase error is eliminated. Therefore, the horizontal synchronizing signal HS 'obtained at Vco 618 has a frequency equal to the horizontal scanning frequency fh of the camera head 1, and the phase is synchronized with the horizontal synchronizing signal HS. Here, when the signal processing device 604 is a memory device of a video signal, the memory device 604 operates as an operation clock multiplying the horizontal synchronization signal HS 'by an integer multiple, and the camera head unit 1 Is reset by the vertical synchronization signal VS supplied from In this way, the signal processing apparatus 604 can operate in synchronization with the camera head unit 1.

The jitter prevention unit 612 is an image signal capable of processing in the signal processing device 604 an image signal composed of the luminance signal Y from the luminance signal generation unit 51 and the color difference signal C from the color difference signal generation unit 56. An interpolation circuit 613 made of a memory or the like is provided as a conversion to. This operation will be described with reference to FIG.

Here, the luminance signal will be described. The luminance signal Y output from the luminance signal generator 51 has the frequency of the pixel signal n × fh, so the number of pixel signals per horizontal line is n. In this case, as shown in FIG. 18, the center of the pixel signal of the luminance signal Y (in this case, generally the center point of the period of the pixel signal) and the operation clock D from the clock output unit 616. FIG. The timings of are consistent. On the other hand, if the frequency of the operation clock E of the signal processing device 604 is m times the horizontal scanning frequency (where m is any positive integer), the luminance signal Y 'handled by the signal processing device 604 is 1. The number of pixels per horizontal line is m.

If m = n, the operating clock D and the operating clock E have the same frequency, but the phases are not necessarily identical. In this case, when the luminance signal Y from the luminance signal generator 51 is supplied to the signal processing device 604 as it is, the luminance signal Y is processed at the timing of the operation clock E, so that the operation clock E is the luminance signal. When the timings coincide at the boundary portions of the adjacent pixel signals of Y, it is unclear which of these pixel signals the timing of the processing by the operation clock E becomes. In this case, for example, the contour portion of the image is not constant between pixel signals adjacent to each processing line by the processing timing so that the contour shifts to one pixel right on one horizontal line or one pixel left on another horizontal line. It also moves. This is different for each field, and the outline is swayed horizontally in the reproduced image by the luminance signal processed in this way. This is jitter.

In order to prevent this, the jitter prevention unit 612 is provided, and the luminance signal is written using the interpolation circuit 613 made of a memory or the like as the light clock, and the operation clock E of the signal processing device 604. Is read as a lead clock. As shown in FIG. 18, the center of each pixel signal (in this case, generally the center point of the period of each pixel signal) coincides with the timing of the operation clock E as shown in FIG.

The case where m = n has been described above. However, when m ≠ n, the process of converting the luminance signal Y of the n pixel signals per horizontal line into the luminance signal Y 'of the m pixel signals per horizontal line is also interpolated. It is executed in the circuit 613. FIG. 18 is a diagram showing a case of nm. In this case, as shown, an average pixel signal of two predetermined pixel signals is obtained to reduce the number of pixel signals per horizontal line, or rare in each horizontal line. There is a method of reducing rare pixel signals. Either way, it is desirable to reduce the number of pixel signals by processing over the entire line in each horizontal line, so that only the left and right ends of the image are removed. Conversely, in the case of nm, the pixel signal may be processed to be sparsely added over the entire horizontal line.

Even when the number of pixel signals is increased or decreased as described above, with respect to the luminance signal Y 'obtained by the jitter prevention unit 612, the center of each pixel signal coincides with the timing of the operation clock E of the signal processing apparatus 604. The above is also true for the color difference signal.

In this embodiment, the camera signal processing unit 603 is integrally provided in various signal processing devices 604, such as a personal computer, a display device, and a memory device, and the digital signal processing device 2 is used as one camera. The head unit 1 can be used in common for each digital signal processing apparatus 2, and each digital signal processing apparatus 2 has various kinds of cameras having different synchronization frequencies or different pixel signals per horizontal line. It can use for the head part 1 in common.

In addition, in the case where the digital signal processing apparatus 2 can be used for various types of camera heads 1, when the number of pixel signals per horizontal line is different for each of the camera heads 1, for example, Since the number of pixel signals to be removed is different, the processing of the jitter prevention unit 612 must be changed for each type of camera head unit 1 connected to the digital signal processing apparatus 2. For this purpose, for example, a processing circuit for converting the number of pixel signals per horizontal line may be provided for each type of camera head unit 1, and this may be switched for each connected camera head unit 1, and the number of pixel signals per horizontal line may be changed. Whether or not the camera head unit 1 is connected is provided with information indicating the type of the camera head unit 1, for example, so that the digital signal processing apparatus 2 detects it or from the clock output unit 616. The frequency between the operation clock D and the operation clock E of the signal processing device 604 can be compared and detected.

As described above, in this embodiment, the frequency of the operation clock of the camera signal processing unit 603 in the camera head unit 1 and the digital signal processing unit 2 is n times the horizontal scanning frequency fh of the signal processing unit 604. The camera signal processing unit 603 can output the video signal having the same horizontal scanning frequency as the horizontal scanning frequency fh of the signal processing apparatus 604.

In addition, since the camera head 1 and the signal processing device 604 can take horizontal and vertical synchronization, the camera head 1 can be connected to the signal processing device 604 without disturbing synchronization. In addition, the camera head 1 and the digital signal processing apparatus 2 are connected by a signal transmission section 5 which transmits a point-sequential analog signal of a pixel signal, and executes digital transmission which requires a large number of cables. Between the camera signal processing unit 603 and the signal processing device 604 which do not carry out digital transmission, and are stored in the same housing and do not need to carry out transmission by cables. 604 can be supplied. In addition, since the camera head 1 and the digital signal processing apparatus 2 are physically separated from each other, there is a degree of freedom in the shooting range so that the shooting angle can be changed or the subject can be changed without moving the whole system. It becomes easy. In addition, the signal processing device can be changed by the jitter preventing unit 612 even in the camera head 1 having the same horizontal scanning frequency as the signal processing device 604 and the number of pixels per horizontal line. At 604, the video signal can be supplied without problem (unreasonably).

19 is a block diagram showing another example of a video camera according to the present invention. In addition to the components of the video camera shown in FIG. 17, a phase detector 619, a Vco 620, and a fixed oscillator 621 are provided. Each component of the video camera shown in FIG. 17 is denoted by the same reference numeral, and redundant description thereof is omitted. Although the video camera shown in FIG. 17 matches the sync frequency of the camera head 1 with the sync frequency of the signal processing device 604, this embodiment shown in FIG. The synchronization frequency of 604 coincides with the synchronization frequency of the camera head 1.

The signal processing device 604 is provided with a fixed oscillation unit 621. The fixed oscillator 621 generates a horizontal synchronization signal HS 'having a horizontal scan frequency fh. This horizontal synchronizing signal HS 'is a horizontal synchronizing signal of the signal processing apparatus 604. For this reason, like the video camera shown in FIG. 17, the phase detection part 617 and the Vco 618 are not provided. The horizontal synchronization signal HS 'is supplied to the camera head portion 1 via the signal transmission portion 5. On the other hand, the camera head unit 1 is provided with a phase detection unit 619 and a Vco 620 instead of the fixed oscillation unit 608 in the video camera of FIG. 17, and is supplied with a horizontal synchronization supplied through the signal transmission unit 5. The signal HS 'is supplied to the phase detector 619. The driving pulse output unit 22 generates an operation clock of an frequency n times the frequency of the horizontal synchronous signal HS, the vertical synchronous signal VS, and the horizontal synchronous signal at the output of the Vco 620, and the phase detection unit 619 Detects a phase error between the horizontal synchronization signal HS and the horizontal synchronization signal HS 'from the signal processing device 604. The oscillation frequency is variable over a wide range of the Vco 620, and the oscillation frequency or phase is controlled by the detection output of the phase detection unit 619 so that this phase error is eliminated.

In this way, the frequency of the horizontal synchronizing signal HS output from the drive pulse output unit 22 is equal to the frequency fh of the horizontal synchronizing signal HS 'of the signal processing apparatus 604, and the driving pulse output unit 22 The frequency of the output operation clock is also n times the horizontal scanning frequency fh. The other operation is the same as that of the video camera shown in FIG. In this video camera, the camera head unit 1 can be operated in synchronization with the signal processing apparatus 604. Therefore, even if another type of camera head portion 1 is connected to the signal processing apparatus 604, the camera head portion 1 can operate in synchronization with the signal processing apparatus 604, and the camera head portion 1 Is connected to a signal processing device 604 operating at a different frequency, the camera head unit 1 operates in synchronism with the signal processing device 604 connected thereto.

20 is a block diagram showing another example of a video camera according to the present invention. The same components as those of the video camera of FIG. 17 are denoted by the same reference numerals, and redundant description thereof will be omitted. In addition to the components of the video camera of FIG. 17, the video camera includes a synchronization signal inserter 622, a horizontal and vertical sync signal extractor 623, a pixel sync signal extractor 624, a comparator 625, and a variable delay. Has a circuit 626. In the camera head unit 1, the drive pulse output unit 22 has the vertical synchronizing signal VS, the horizontal synchronizing signal HS and the frequency of the horizontal scanning frequency fh at the output of the fixed oscillation unit 608 as shown in FIG. An operating clock of n × fh is generated, but the pixel synchronization signal PS is also generated intermittently in the horizontal scanning period. The pixel synchronous signal PS has a frequency whose n is the same as that of the operation clock and is in phase synchronization with this operation clock. These vertical synchronizing signals VS, horizontal synchronizing signals HS and pixel synchronizing signals PS are supplied to the synchronizing signal insertion section 622 where they are superimposed on the output signals of the image pickup device 20. The output signal A 'of the synchronization signal insertion unit 622 to which these synchronization signals are added is supplied to the camera signal processing unit 603 in the digital signal processing apparatus 2 via the signal transmission unit 5.

21A is a diagram showing an example of the output signal A 'of the synchronization signal insertion section 622. FIG. The vertical synchronization signal VS is inserted every field and the horizontal synchronization signal HS is inserted every horizontal line. Here, the vertical synchronization signal VS has a larger amplitude and time width than the horizontal synchronization signal HS, but of course, only one of the amplitude and time width of the vertical synchronization signal VS may be larger than the horizontal synchronization signal HS. In other words, the vertical synchronization signal and the horizontal synchronization signal may be separated from the signal A 'separately. The pixel synchronous signal PS is inserted in the blank period immediately after the vertical synchronous signal VS or the horizontal synchronous signal HS every horizontal line. The pixel synchronous signal PS is composed of sine waves or pulses of a plurality of cycles, for example, a color burst signal, and its frequency is equal to the frequency n × fh of the pixel signal in the signal A '. The phases are also synchronized.

21B is a waveform diagram showing another example of the output signal A 'of the synchronization signal insertion section 622. FIG. Here, the pixel synchronizing signal PS serves as a horizontal synchronizing signal and a vertical synchronizing signal, and is inserted in every horizontal line. The number of cycles of the pixel synchronizing signal PS is different in the case of serving as the horizontal synchronizing signal HS and in the case of serving as the vertical synchronizing signal VS. That is, since the number of cycles of the pixel synchronization signal PS is increased for each field, the pixel synchronization signal PS can be used as the vertical synchronization signal VS when the number of cycles is large, and also as the horizontal synchronization signal HS when the number of cycles is large. In order to be able to separate the pixel synchronization signal PS from the signal A ', the pixel synchronization signal PS is a sinusoidal signal whose polarity alternately changes at the center of the blank level of the signal A'. Further, even if other methods such as varying the amplitude of the pixel synchronization signal PS in accordance with the horizontal and vertical synchronization signals are used, the pixel synchronization signal PS can also be used as the horizontal and vertical synchronization signals.

Returning to FIG. 20, the output signal A 'of the camera head unit 1, as shown in FIG. 21A supplied through the signal transmission unit 5 from the camera signal processing unit 603, extracts the horizontal vertical synchronization signal. Supplied to the circuit 623, the horizontal vertical synchronizing signal extraction circuit 623 extracts the vertical synchronizing signal VS and the horizontal synchronizing signal HS. And as shown in FIG. 17, this vertical synchronization signal VS is used to reset the signal processing apparatus 604. As shown in FIG. The horizontal synchronizing signal HS is supplied to the phase detecting unit 617 to be used to form the horizontal synchronizing signal HS 'of the frequency fh in the signal processing apparatus 604, and is supplied to the phase detecting unit 614 to supply the clock output unit 616. Is used to generate an operating clock D of frequency n × fh.

In addition, as shown in FIG. 21B, when the pixel synchronization signal PS is inserted, the pixel synchronization signal PS is extracted by clipping at a level lower than the blank level of the signal A ', and the envelope (PS) is extracted. By detecting the envelope, a pulse having a different time width can be obtained in the vertical synchronization signal portion and the horizontal synchronization signal portion, and the vertical synchronization signal VS and the horizontal synchronization signal HS can be obtained by detecting the difference in the time width. . Of course, when the amplitude of the pixel synchronous signal PS inserted in the signal A 'is different between the vertical synchronous signal portion and the horizontal synchronous signal portion, the difference in the amplitude of the pulse obtained by envelope detection is detected. The horizontal synchronization signal HS can be obtained.

The signal A 'supplied through the signal transfer section 5 is also supplied to the pixel synchronization signal extraction section 624 to extract the pixel synchronization signal PS. Here, when the pixel synchronous signal PS is inserted into the signal A 'as shown in Fig. 21B, the pixel synchronous signal PS is extracted by clipping as described above. As shown in Fig. 21A, when the pixel synchronizing signal PS is inserted into the signal A ', a gate signal is formed from the vertical synchronizing signal VS extracted from the horizontal and vertical synchronizing signal extracting circuit 623 and the horizontal synchronizing signal HS. In this way, the pixel synchronization signal PS is extracted from the signal A '.

The pixel synchronization signal PS extracted by the pixel synchronization signal extraction unit 624 is supplied to the comparison unit 625, and the phase error with the operation clock D from the clock output unit 616 is detected. The operation clock D is delayed by the variable delay circuit 626, but the variable delay circuit 626 is controlled in accordance with the detection output of the comparator 625 so that the detected phase error is eliminated. As a result, the frequency of n × fh from the variable delay circuit 626 and the timing of the pixel synchronization signal PS extracted by the pixel synchronization signal extraction unit 624 coincide with each other. An operating clock D 'is obtained in which the center of the signal coincides with the timing. The operation clock D 'is applied to the A / D converter 50 as a sampling pulse, to the luminance signal generator 51 and the color difference signal generator 53 as a timing pulse, and to the jitter prevention unit 612 as a light clock. They are supplied respectively, and the same process as shown in FIG. 17 is performed with respect to the signal A '.

As described above, in this camera, since the synchronous signal is added to the output signal of the image pickup device 20 and transmitted to the digital signal processing apparatus 2, the number of wirings of the signal transmission section 5 as compared with that shown in FIG. In other words, the number of cables can be further reduced, and the camera head 1 and the signal processing device 604 can also be synchronized. In the camera signal processing unit 603, the operation clock D 'whose timing coincides with the pixel synchronization signal PS added to the signal A' is obtained and operated using the operation clock D '. The center and timing of the pixel signal at < RTI ID = 0.0 > 'are < / RTI >

22 is a block diagram showing another example of a video camera according to the present invention. In addition to the components of the video camera shown in FIG. 17, a CDS / AGC circuit 627 and an AGC detection circuit 628 are provided. The same parts as those in FIG. 17 are denoted by the same reference numerals, and redundant description thereof is omitted.

The output signal of the imaging device 20 is supplied to the CDS / AGC circuit 627, and the noise generated when the lead pixel is switched in the imaging device 20 is eliminated, and the AGC control from the AGC detection circuit 628 is performed. The signal is a signal of a constant level. The output signal of this CDS / AGC circuit 627 is supplied to the digital signal processing apparatus 2 as the output signal A of the camera head unit 1. The output signal of this CDS / AGC circuit 627 is also supplied to the AGC detection circuit 628, and an AGC control signal is generated in accordance with the level change of this signal A. The gain of the CDS / AGC circuit 627 is controlled in accordance with this AGC control signal, and the level variation of the output signal of the imaging device 20 is eliminated.

In this manner, an effect similar to that shown in FIG. 17 is obtained, and there is an effect that a stable video signal with no level fluctuations from which noise is removed can be obtained. It goes without saying that the CDS / AGC function can be added to cameras other than those shown in FIG.

23 is a block diagram showing another example of a video camera according to the present invention. The camera head unit 1 and the camera signal processing unit 603 of the video camera in FIG. 17 and the like described above are integrated into a camera signal processing device 629, and the signal processing device is connected to the camera signal processing device 629. 604 is connected. The camera signal processing apparatus 629 includes a Vco 630, a frequency setting unit 631, an input terminal 632, and the like. In addition, the same code | symbol is attached | subjected to the same part as what was demonstrated in the drawing mentioned before, and the overlapping description is abbreviate | omitted. The camera signal processing device 629 is housed in one housing, and the signal processing device 604 can be connected and disconnected by a signal transmission unit such as a cable. Here, unlike the above embodiment, the camera signal processing apparatus 629 does not use the synchronization signal and operates only in the operation clock in which the driving pulse output unit is generated. By controlling this operation clock by the signal processing apparatus 604, the camera signal processing apparatus 629 and the signal processing apparatus 604 are synchronized.

In the camera signal processing device 629, the vertical synchronization signal VS 'is supplied as a reset pulse from the connected signal processing device 604. The drive pulse output section 22 is reset by this vertical synchronization signal VS 'and divides the output of the Vco 630 to generate an operation clock F. This operation clock F is supplied to the frequency setting unit 631. In the frequency setting section 631, the horizontal synchronizing signal HS 'is also supplied from the signal processing device 604, and a positive integer value n is set at the input terminal 632, whereby the operating clock F is divided by n and horizontal. The phase error with the synchronization signal HS 'is detected. The frequency setting unit 631 controls the oscillation frequency and phase of the Vco 630 so that this phase error is eliminated. As a result, the frequency of the operation clock F output from the drive pulse output unit 22 is n times the frequency of the horizontal synchronization signal HS 'of the signal processing device 604, that is, n × fh.

The imaging device 20 operates at this operation clock F and outputs an analog signal in which pixel signals are arranged in sequential order at a frequency nxfh. The timing of the operation clock coincides with the center of each of these pixel signals. This analog signal is processed in the CDS / AGC circuit 627 and supplied to the A / D conversion section 50, similar to the camera shown in FIG. 22, to supply the operation clock F from the drive pulse output section 22. The sampling pulse is converted into a digital signal. The digital signal is supplied to the luminance signal generating unit 51 and the color difference signal generating unit 53, and processed using the operation clock F as the timing pulse to generate the digital luminance signal and the digital color difference signal. These digital luminance signals and digital chrominance signals are processed in the same manner as in the above-described embodiment by the jitter prevention unit 612 using the operation clock F as the light clock and the operation clock E of the signal processing device 604 as the lead clock. The signal is converted into a video signal that can be handled by the signal processing device 604 at the frequency fh and supplied to the signal processing device 604. In this manner, also in this video camera, the camera signal processing device 629 can be operated in synchronization with the signal processing device 604.

Here, the value of n specified by the input terminal 632 may be any positive integer. Therefore, the frequency of the operation clock F of the camera signal processing apparatus 629 can be arbitrarily set and fine adjustment of this frequency is also possible. For this reason, any frequency may be sufficient as the horizontal scanning frequency fn of the signal processing apparatus 604, and therefore, the signal processing apparatus 604 is not specifically limited, either. In other words, even if the horizontal scanning frequency connects any signal processing device 604 to the camera signal processing device 629, the camera signal processing device 629 can process the video signal that the connected signal processing device 604 can process. You can create

Further, by specifying the constant n at the input terminal 632 so that the aspect ratio of the processing result of the signal processing apparatus 604 is correct, the camera signal processing apparatus 629 can output a video signal with an accurate aspect ratio.

The constant n can be designated by this personal computer by connecting a personal computer or the like to the input terminal 632. In particular, when the signal processing device 604 is a personal computer, the constant n can be specified in the signal processing device 604.

24 is a block diagram showing another example of a video camera according to the present invention. Similarly to FIG. 23, this camera is integrated with a camera head portion and a camera signal processing portion. The camera signal processor 629 also has a calculator 633. In addition, the same parts as described in the above drawings are given the same reference numerals and redundant description thereof will be omitted.

In this camera, instead of designating the constant n at the input terminal 632, the camera shown in FIG. 23 is provided with a calculation unit 633 and an operation clock F and signal processing output from the drive pulse output unit 22. The constant n is calculated from the horizontal synchronization signal HS 'of the apparatus 604, and the calculated constant n is set in the frequency setting unit 631. The calculation unit 633 is configured by, for example, a counter or the like, and is initialized for each horizontal synchronizing signal HS 'of the signal processing apparatus 604 to count the operation clock F, and the count value immediately before the count is made and is initialized next. Let said integer n be said. Of course, the timing pulse for initializing the counter or reading the count value (that is, the constant n) is formed by the horizontal synchronization signal HS 'of the signal processing device 604.

Therefore, if k is an arbitrary integer and the frequency of the operation clock F output from the drive pulse output unit 22 is k × fh, the constant n calculated by the calculation unit 633 is an integer part of the integer k. If this is represented by [k], it is [k] <k. However, the equal sign is a case where k is an integer. When the calculated constant [k] is set in the frequency setting unit 631, the frequency f of the signal F / [k] obtained by dividing the operating clock F by [k] is obtained when the constant k is not an integer.

f = α × fh (where 1α2)

It becomes That is, fhf2fh is obtained. For example, if k = 100.5 (the frequency 100.5 x fh of the operation clock F at this time is an integer multiple of the horizontal scanning frequency when viewed from the imaging device 20 side, i.e., the imaging device 20). The horizontal scan frequency on the side of) and the horizontal scan frequency on the side of signal processing device 604 are not the same, and this case is assumed to be the initial state here.) The constant [k] is 1∞. The frequency f of the signal obtained by dividing the operation clock F is 1.005 x fh (in this case, α is 1.005).

The frequency setting unit 631 further detects the phase error of the signal of frequency α × fh and the horizontal synchronization signal HS 'divided by the operation clock F [k], and controls the Vco 630 so that the phase error disappears. . As a result, the portion below the decimal point (0.05 in the above example) is absorbed, and the frequency of the operation clock F becomes an integer multiple of the frequency fh of the horizontal synchronization signal HS '.

Thus, in this embodiment, whatever the frequency of the operation clock F of the camera signal processing apparatus 629 is an integer multiple of the horizontal scanning frequency fh of the signal processing apparatus 604 to be connected. For this reason, without setting the constant n as in the camera shown in FIG. 23, the horizontal scanning frequency from the camera signal processing apparatus 629 is the same as the Suffolk scanning frequency fh of the signal processing apparatus 604, and the signal processing apparatus ( A video signal that can be processed by 604 can be obtained.

Claims (23)

An image pickup device for photoelectric conversion of an optical image, a timing generation circuit for driving the image pickup device and outputting a point sequential signal representing information of each pixel to the image pickup device, and the image pickup device in the blank period of the output signal from the image pickup device. A first housing including a circuit for superimposing a synchronization signal representing a pixel period, a luminance signal generation circuit for generating a luminance signal from the superimposed signal, a color signal generation circuit for generating a color signal from the superimposed signal, in the superimposed signal Means for extracting the synchronization signal, means for controlling the processing timing of the color signal generation circuit in accordance with the extracted synchronization signal, and connecting between the first housing and the second housing and A video having a transmission line for supplying an output signal to said luminance signal generation circuit and said color signal generation circuit; MERA Systems. The video camera system of claim 1, wherein the second housing further comprises means for generating a horizontal synchronizing signal and a vertical synchronizing signal from the extracted synchronizing signal. The video camera system of claim 1, wherein the transmission line is included in one cable together with a power line for supplying power from the second housing to the first housing. 2. The video camera system according to claim 1, wherein said second housing further comprises a recording device for recording image data obtained from said luminance signal and said color signal. An image pickup device for photoelectrically converting an optical image, a timing generation circuit for driving the image pickup device and outputting a point sequence signal representing information of each pixel to the image pickup device, and an empty period of the point sequence signal output from the image pickup device. And a superimposed circuit for superimposing a synchronization signal representing a pixel period of the imaging device and an analog interface for outputting the superimposed signal. 6. The video camera according to claim 5, wherein the superimposition circuit also superimposes a horizontal synchronizing signal and a vertical synchronizing signal in the empty period of the coral in the point sequence. 6. The video camera according to claim 5, further comprising an automatic gain control circuit which detects the level of the output signal of the image pickup device and keeps the level of the output signal constant by changing the gain in accordance with the detection result. 8. The video camera according to claim 7, further comprising a control interface for inputting control information from the outside, wherein said automatic gain control circuit changes the level of its output signal in accordance with said control information. 6. The video camera according to claim 5, further comprising a control interface for inputting control information from the outside and means for controlling the timing of pulses output from the timing pulse generating circuit according to the control information. 6. The video camera according to claim 5, further comprising a memory for holding control data inherent to the imaging device and a control interface for outputting data held in the memory to the outside. A signal processing device for processing and processing an image at a predetermined horizontal scanning frequency and outputting the horizontal synchronizing signal to an input digital video signal, a camera signal processing device housed in a housing, and the digital video signal A first transmission line transmitted from the camera signal processing apparatus to the signal processing apparatus and a second transmission line transmitting a signal relating to the horizontal scanning frequency from the signal processing apparatus to the camera signal processing apparatus, the camera signal The processing apparatus includes an imaging device for photoelectric conversion of an optical image, a drive pulse generation circuit for generating an operation clock for driving the imaging device, an analog / digital converter for converting an analog signal output from the imaging device into a digital signal, and the digital device. A signal generation circuit for generating the digital video signal from the signal and the operation clock Means for controlling said drive pulse generating circuit so that a frequency becomes an integer multiple of said horizontal scan frequency. 12. The video camera system according to claim 11, wherein the integer multiple frequency is a frequency at which the aspect ratio of the image generated by the signal processing device is most accurate. A video camera for supplying a video signal to a signal processing apparatus for processing or processing an image at a predetermined horizontal scanning frequency, comprising: an imaging device for photoelectric conversion of an optical image; and a driving pulse for generating an operation clock for driving the imaging device A generating circuit, an analog / digital converter for converting an analog signal output from the image pickup device into a digital signal, a signal generating circuit for generating the digital image signal from the digital signal, and the predetermined horizontal scanning frequency in the signal processing apparatus. Means for inputting a signal and controlling said drive pulse generating circuit such that the frequency of said operating clock is an integer multiple of said horizontal scan frequency. The video camera according to claim 13, wherein the integer multiple frequency is a frequency at which the aspect ratio of the image generated by the signal processing device is most accurate. 2. The apparatus of claim 1, wherein the first housing has a memory for holding control data inherent to the imaging device, and the second housing controls the luminance signal generation circuit and the color signal control circuit in accordance with control data read from the memory. Video camera system having a controller. 16. The data held by the memory according to claim 15, wherein the data held by the memory includes data indicating gain for each color separation filter of the imaging device, data representing the number of pixels of the imaging device, data representing the aspect ratio of the imaging device, or data of the imaging device. A video camera system that is data representing an array sequence of color separation filters. The brightness signal generating circuit of claim 1, wherein the second housing has a signal processing circuit for processing a signal output from the brightness signal generating circuit and a color signal generating circuit, and generates the brightness signal so as to become an image signal that the signal processing circuit can process. A video camera system having an interpolation circuit for interpolating a signal output from a circuit and a color signal generation circuit. An imaging device for photoelectric conversion of an optical image, a driving circuit for driving the imaging device, a circuit for superposing a horizontal synchronization signal and a vertical synchronization signal on an output signal of the imaging device, and a fixed oscillation unit for supplying an operation clock to the driving circuit; A luminance signal generation circuit for generating a luminance signal from an output signal of the first housing and the first housing, a color signal generation circuit for generating a color signal from an output signal of the first housing, an operation of the luminance signal generation circuit and a color signal generation circuit A clock output unit for outputting a clock, an oscillator for supplying a reference clock to the clock output unit, a circuit for extracting a horizontal synchronization signal and a vertical synchronization signal from an output signal of the first housing, and a clock of the oscillator according to the extracted synchronization signal The video camera system comprising a second housing having a phase detection unit for determining a. 19. The apparatus of claim 18, wherein the second housing has a signal processing circuit for processing a signal output from the brightness signal generating circuit and a color signal generating circuit, and generates the brightness signal so as to become an image signal that can be processed by the signal processing circuit. A video camera system having an interpolation circuit for interpolating a signal output from a circuit and a color signal generation circuit. An image pickup device for photoelectric conversion of an optical image, a drive circuit for driving the image pickup device, a first housing having an oscillator for supplying an operation clock to the drive circuit, and a luminance signal for generating a luminance signal from an output signal of the first housing. A generation circuit, a color signal generation circuit for generating a color signal from the output signal of the first housing, a signal processing circuit for processing the signals output from the luminance signal generation circuit and the color signal generation circuit, and adding a horizontal synchronization signal and a vertical synchronization signal; And a second housing having an oscillator for outputting an operation clock of a signal processing circuit, wherein the second housing sends a horizontal synchronization signal and a vertical synchronization signal to the first housing, and the first housing transmits the horizontal synchronization signal. And a phase detector for determining a clock of the oscillator according to the vertical synchronization signal. 21. The video camera system according to claim 20, further comprising an interpolation circuit for interpolating signals output from said luminance signal generating circuit and color signal generating circuit so that said signal processing circuit becomes a video signal that can be processed. 12. The video camera system according to claim 11, wherein said camera signal processing apparatus has an interpolation circuit for interpolating signals output from said luminance signal generating circuit and color signal generating circuit so as to become an image signal that said signal processing apparatus can process. The video camera according to claim 13, further comprising an interpolation circuit for interpolating signals output from said luminance signal generation circuit and color signal generation circuit so as to become an image signal that said signal processing apparatus can process.