KR100223043B1 - Pattern matching method and method having fixed length shifting - Google Patents

Abstract

The present invention relates to a pattern matching discrimination method and apparatus having a fixed-length moving amount for quickly searching for a desired pattern in a given input data sequence. By storing the information and performing pattern matching, it reduces the time required to find the same pattern, optimizes the hardware implementation, and provides the advantage that it can be used for video codecs, broadband terminals, high-definition TV, multimedia, etc. that require high-speed processing. do.

Description

Pattern matching determination method and apparatus thereof having fixed length of movement

The present invention relates to a method and apparatus for determining pattern matching with a fixed amount of movement, and more particularly, to a method and apparatus for determining pattern matching with a fixed length of movement for quickly finding a desired pattern in a given input data sequence. It is about.

At present, all data with statistical redundancy are transmitted after compressing the data using Variable Length Code (VLC) to maximize transmission efficiency. The VLC is a code that uses a method of allocating fewer bits to a symbol having a high occurrence rate by examining a frequency of occurrence of the symbol.

VLC can reduce the bit rate efficiently compared to a code having a fixed length. In addition, VLC can reduce statistical redundancy of data, compress video and audio data at high rates, and effectively reduce data on storage and transmission media.

However, VLC has the following problems.

First, when decoding an arbitrary bit string with VLC, it should be decoded in the form of symbols having different lengths during decoding by encoding with different lengths according to the statistical distribution. In order to decode such a VLC, hardware complexity is increased compared to fixed length codes.

The second is that the transmission error can be decoded with a code other than the original code to which the code string was transmitted. Therefore, the transmission error continues to affect the next code since the decoder decodes with the wrong code until the decoder knows this.

In order to prevent this, the current variable length encoder inserts a synchronization code having a fixed length into the bit string to enable transmission error or random access to the coded bit string.

The reason is that when using variable length code, specifically Huffman code, if the variable length code is continuous, the synchronization point, that is, the starting position of any variable length code, is not known. Variable length code is used, but its efficiency is not good.)

Therefore, the synchronization code having a specific pattern is periodically inserted.

In MPEG, etc., this is called start code. In MPEG video, 000001xx (xx is an identifier at the beginning of a slice, a picture, a group of pictures, a sequence of pictures, etc.) at the beginning. Insert a start symbol).

And for the uniqueness of the synchronization code, no variable length code is assigned the pattern 000001.

Therefore, when a digital TV using MPEG or the like is turned on, the video decoder inside it first searches for a start code (specifically, a sequence start code).

Then, the picture start code is found after decoding the parameters related to the determined sequence. Likewise, after decoding the parameter for one picture, finding the slice start code again, repeating the same process, variable length decoding is performed.

On the other hand, in the variable-length decoder, if any error is found in the de-decoded bit stream, the data currently being decoded is in an error state, so the data is discarded and a new starting point is found and resynchronized.

When the resynchronization code is found, the VLC data input thereafter is correctly encoded. In MPEG standardization, start codes are inserted into a coded bit string. This start code not only indicates the start of each layer but can also access any layer in the coded bitstream. Where fast processing speeds such as broadband terminals, high-definition TVs or multimedia are required, this resynchronization algorithm not only allows the decoder to handle transmission errors at high speeds but also allows random access.

The basic theory for determining a pattern with a fixed amount of movement that provides this advantage is as follows.

Assume that an arbitrary bit string is given below.

s ₁ , s ₂ , s ₃ ,. , s _i , s _{i + 1} ,. Let, s _L and L the length of the bit string. An arbitrary match pattern (hereinafter referred to as PAT) is found from a given bit string, and a PAT is constructed as follows. PAT = p ₁ , p ₂ ,... , p _n (n L). To find the comparison operation, define STR as a bit string that is compared with a given bit string in one step. Let n be the length of the PAT and l be the length of the STR. Consider the case where the value of l is equal to the value of n. Let us represent the current state used to compare STR and PAT as S (t) and the next state as S (t + 1). If PAT and STR are S (t), then P ₁ at p _k (k Assume that s _{n-k + 1} to sn, later in STR, matches n). P ₁ , p ₂ ,... , p _k and s _{n-k + 1} ,. Let s _n-1 and s _n match. Let k be the number of forward matches (N _F ). P _{k + 1} of PAT at S (t + 1),... , p _n is s ₁ of STR... , s _nk In this case, let nk be the number of reverse matches (NB).

If we find the pattern we want, the sum of N _F and N _B is n and the desired pattern, called PAT, can be found between S (t) and S (t + 1). The values of N _F and N _B range from 0 to n-1.

Referring to the algorithm for pattern matching determination with a fixed amount of conventional movement through the above and the theory, as shown in Figure 1, any PAT is 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, A pattern that is called 0, and compares to this PAT is 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0 Let 0, 0, 0, 0, 0, 0, 1, 1, 1, 0. At this time, n, the length of the PAT, and ℓ, the length of the STR, were both 10.

The 10-bit STR is compared to the PAT at each clock. Each STR compares forward from the first bit of the PAT.

Of STR in S (t)... , 0, 0 and PAT 0, 0,... The value of N _F is 2 since 0, 0... Of STR in S (t + 1). And PAT… , 0, 0, so N _B is 2. Since the sum of N _F and N _B does not equal 10 (n = 10), there is no PAT between S (t) and S (t + 1). Of STR at S (t + 1). , 0, 0, 0, 0 and 0, 0, 0, 0,. The value of NF is 4 because 0, 0, 0, 0, 0, 0,... Of STR in S (t + 2). And PAT… The value of N _B is 6 since 0, 0, 0, 0, 0, 0 matches. In such a case, the sum of N _F and N _B is 10 (n = 10). Therefore, it can be seen that there is a desired pattern between S (t + 1) and S (t + 2).

In conclusion, in order to have a fixed amount of movement in one clock, it is necessary to consider the bits existing between the input STRs after the current input STR. In the following states, the maximum number of bits to include a match pattern is n-1 and the minimum number of bits is one. Therefore, the range of values of N _F and N _B can range from 1 to n-1.

The prior art as described above has a hardware design having a fixed amount of movement using the number of forward matches and the number of backward matches.

Therefore, the time it takes to find the same pattern while moving by one bit is too long, the operation frequency of the hardware is also increased, and there is a problem that the recovery time is long when a transmission error occurs.

In addition, since additional hardware such as an adder is required, there is a disadvantage in that it is not optimal hardware.

SUMMARY OF THE INVENTION The present invention has been made in view of the conventional problems and disadvantages described above, and an object thereof is to provide a method and apparatus for finding a desired pattern such as a resynchronization code at high speed for a high speed resynchronization to a given input data sequence. In particular, it aims to optimize the hardware implementation by storing the minimum information necessary for the current state among the data values of the previous state and then performing pattern matching.

1 is a diagram showing an algorithm of a conventional pattern matching determination method with a fixed amount of movement.

2 (a) is n Explanatory diagram of data flow diagram and pattern matching with fixed amount of movement according to the present invention when l.

2 (b) is n Explanatory diagram of data flow diagram and pattern matching with fixed amount of movement according to the present invention when l.

3 is a block diagram of a pattern matching discrimination apparatus having a fixed length of movement according to the present invention.

4 is an exemplary diagram showing an example of application to a variable encoder of an MPEG2 video decoder of the present invention.

* Explanation of symbols for main parts of the drawings

31: Input buffer 32: Latch 1

33: latch 2

34: Programmable Logic Array (PLA)

35: buffer controller 41: input buffer

42: latch 1 43: latch 2

44: barrel shifter 45: PLA

46: Accumulator

In order to achieve the above object, an input buffer for storing an input bit string,

First storage means for storing one bit string in the input buffer, and second bit for storing the bit string stored in the first storage means when the desired pattern and the bit string stored in the first storage means do not have a pattern match. Storage means,

Comparison means for judging pattern matching by arranging the bit strings in the first and second storage means in a row; and

When the result of the comparison is a pattern matching, the comparison means comprises a buffer controller for receiving a signal indicating the pattern matching and information on the amount of movement.

Further, in order to achieve the above object, storing one bit string from the input buffer in the first storage means;

If the desired pattern and the bit strings stored in the first storage means are not pattern matched, the bit strings stored in the first storage means are stored in the second storage means, and one bit string is received from the input buffer again to the first storage means. Storing; And

And determining the pattern matching by arranging the bit strings in the first and second storage means in a row in the comparison means.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition to the prior art, the present invention uses a method of storing a current bit corresponding to N _F in a latch and comparing it with the STR input in the next state when the pattern matching fails.

2 (a) shows that when the value of n is 4 and the value of ℓ is 6, three bits of the STR input to the current state and the previous state STR are compared with the PAT of the current state. Therefore n In the case of L, the number of bits to be compared with one clock in order to have a fixed amount of movement has a value of l + n-1 (= l + N _F ). The comparative operation number N ranges from l × n to l + n−1.

When l is smaller than n, it is as follows. Since the number of bits input to one clock is less than n, the input STR must be stored until it is larger than the length of the match pattern.

If we assume that the value of l is 4 and the value of n is 6, we start comparing the PAT after two STRs have been entered in the initial state. Since the value of n is 6, the value of N _F is maximum. The corresponding bits must be compared with the next incoming input bit stream after storage. The number of bits to be compared to one clock is 9 (= N _F + ℓ).

2 (b) shows a flowchart of data stored in a latch in the above case. Therefore, the fewer input bits, the greater the latency. n In the case of L, the number of bits to be compared with one clock in order to have a fixed amount of movement has a value of l + n-1. The range of the comparison operation number N is Lxn to L + n-1.

3 shows a pattern matching determination device having a fixed amount of movement. The input bit string is stored in the input buffer 31 and outputs a bit string whenever required by an external module. If it is confirmed that there is an error in the bit string output by the external module, the bit string must be resynchronized.

In order for the PAT to shift the length by one, one bit must be input into the latch 1 (32) every clock. The operation in the initial state is as follows. One STR is stored in latch 1 (32) and then PLA (34) lines up the bits stored in STR and latch 2 (33) and compares it to the PAT. If pattern matching fails, a bit in the range of latch 1 (32) to N _F is stored in latch 2 (32). ℓ In case of n-1, the number to be stored is n-1. In the opposite case, the number of bits to be stored is ℓ. If the desired PAT is found, the PLA 34 transmits the pattern_discovery signal and information of the amount to move to the buffer controller 35. In the next state, the buffer controller 35 finds the starting point of the bit string and transmits the bit string to an external module.

4 shows an embodiment in which the method according to the present invention is applied to an MPEG2 video decoder. In the video decoder, a structure such as that of FIG. 4 is mainly used. Information used to encode Discrete Cosine Transform (DCT) coefficients in MPEG2 includes a run and a signed level. The maximum length of this sign is the sum of the length of the sign of the run and level with an escape followed by a fixed length.

The escape code is 6 bits, the run fixed length code is 6 bits, and the length of the code used to indicate the level is 12 bits, so the total length is 24 bits.

Therefore, the maximum number of input bits of the variable-length coder has a structure in which 24 bits are input in every clock in parallel. In the variable length encoder, the barrel shift 44 which requires 48 bits as inputs and 24 bits as outputs using two 24-bit latches 41 and 42 to process them in one clock is required. Therefore, the required number of bits that must be matched to find 24 bits of sync sign with 24 bits of input per clock is 47 = 24 + 24-1.

Therefore, when data error occurs or random access is required and resynchronization is performed using the variable length encoder structure, the upper 23-bit pattern of the 24 bits of latch 1 (42) and the bits stored in latch 2 (43) and 32-bit sync code is compared using the PLA (45).

Therefore, as shown in FIG. 4, the amount of movement input to the barrel shift 44 used for encoding the variable length code is set to 0, and an input control signal is inputted to the input buffer 41 so that the next 24 bits are latched 1 (for every clock). 42).

If the start code is found, the PLA 45 verifies the desired sync code by decoding the 8-bit information after the start code indicating the type of the sync code in the accumulator 46. If the desired code is used, new data is not stored in the latch 1 42 at the next clock through the input control signal, and the accumulator 46 is used to shift the next position of the sync code. After resynchronization, the variable length encoder operates normally.

As described above, the present invention reduces the time required to find the same pattern by performing pattern matching after storing the minimum information necessary for the current state among the data values of the previous state in performing pattern matching. Optimized implementation provides advantages that can be used for video codecs, broadband terminals, high-definition TVs, and multimedia that require high-speed processing.

In particular, it is very applicable to the architecture used for the variable length encoder of the video decoder.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

Claims (8)

An input buffer for storing an input bit string, First storage means for storing one bit string in the input buffer, and second storage for storing the bit string stored in the first storage means when the bit pattern does not match the desired pattern and the first storage means. Sudan, Comparison means for judging pattern matching by arranging the bit strings in the first and second storage means in a row; and And a buffer controller for receiving information about an amount equal to a signal representing pattern matching in the comparison means, when the result of the comparison is pattern matching. The method of claim 1, In storing the bit string of the first storage means that is not pattern-matched in the second storage means, the pattern matching having a fixed length moving amount, storing the bits constituting the number of forward matches in the second storage means. Discrimination device. The method according to claim 1 or 2, And the first and second storage means are latches. The method of claim 1, The comparison means is a pattern matching determination device having a fixed length of movement, characterized in that the PLA. Storing one bit string from the input buffer in the first storage means; If the desired pattern and the bit strings stored in the first storage means are not pattern matched, the bit strings stored in the first storage means are stored in the second storage means, and one bit string is received from the input buffer again to the first storage means. Storing; And And determining whether or not to match the pattern by arranging the bit strings in the first and second storage means in a row in the comparison means. The method of claim 5, When the desired pattern and the bit string stored in the first storage means are not pattern-matched, in storing the bit string stored in the first storage means in the second storage means, the bits constituting the forward match number are stored in the second storage means. Pattern matching determination method having a fixed length of movement, characterized in that. The method according to claim 5 or 6, And the first and second storage means are latches. The method of claim 5, The comparison means is a pattern match determination method having a fixed length of movement, characterized in that the PLA.