KR100221326B1 - A pipeline system using the hierarchical structure - Google Patents

Abstract

The present invention relates to a pipelined system having a hierarchical buffer structure. The pipelined system of the present invention is a primary system that primarily switches and outputs data according to first switching information SI1 included in an input data stream. Buffering means (400); Secondary buffering means (500) for secondly switching and outputting data according to second switching information (SI2) included in the data stream from the primary buffering means (400); Tertiary buffering means (600) for receiving data from the secondary buffering means (500) and acting as a buffer; And a plurality of functional units 700 which receive data from the tertiary buffering means 600 and perform respective functions, and according to the present invention, using the switching information included in the input data stream. By hierarchically transferring data to a plurality of functional units provided in parallel, the number of virtual functional units can be increased to not only improve parallelism but also greatly improve data processing capacity of the pipeline.

Description

Pipeline system with hierarchical buffer structure

The present invention relates to a pipeline system having a hierarchical buffer structure. In particular, the present invention relates to a plurality of functional units (FUs) provided in parallel by using switching information included in an input data stream. The present invention relates to a pipeline system having a hierarchical buffer structure designed to increase parallelism by increasing the number of virtual functional units, as well as to greatly improve data throughput of the pipeline.

In general, pipelining provides a means of realizing temporal parallelism in digital computers. The concept of pipeline in a computer is similar to the concept of a production line in a production plant.

In order to perform pipelining, the input process must be subdivided into a sequence of subprocesses, each of which is performed by a particular hardware stage operating concurrently with other stages in the pipeline. do. Successive processes form a flow in the pipe and are performed in an overlapped fashion at the subprocess level. This type of pipe method can dramatically increase the throughput of digital computers.

Subsequently, when classifying pipeline processors, various types of pipeline processors are classified according to processing levels and pipeline configurations and control strategies.

First, Handlers are classified into arithmetic pipelining, instruction pipelining, and processor pipelining according to processing levels.

1 illustrates arithmetic pipelining

2 illustrates instruction pipelining

3 illustrates processor pipelining

And Ramamoorthy and Li have a single function / multifunction pipeline, a static / dynamic pipeline, a scalar / vector pipeline, depending on the pipeline configuration and control strategy. Classified as

Looking at the monofunctional / multifunctional pipeline first, a pipeline unit with a fixed dedicated function is called "unifunctional". Cray-1 has 12 single function pipeline units for various scalar, vector, fixed point and floating point operations. Multifunctional pipes can then perform different functions at different times or simultaneously by interconnecting different subsets of stages in the pipeline. The TI-ASC has four multifunction pipeline processors, each of which can reconfigure many arithmetic logic operations at different times.

And, looking at the static / dynamic pipeline, the static pipeline can only estimate one functional configuration at a time. Static pipelines are single functional or multifunctional. Pipelining is possible in static pipes only if the same type of instruction is executed continuously. Functions performed by static pipelines should not change often. Dynamic pipeline processors, on the other hand, allow for multiple functional configurations to exist simultaneously. In this regard, dynamic pipelines must be multifunctional. Dynamic configuration requires much more sophisticated control and sequencing mechanisms than in static pipelines. Most computers have a single functional or multifunctional static pipe.

In addition, pipeline processors that depend on the instruction or data type are also classified into scalar pipelines and vector pipelines. The scalar pipeline processes a series of scalar operands under the control of the "DO" loop. Instructions in small "DO" loops are often prefetched into the instruction buffer. The scalar operands required for repeating scalar instructions are moved to a data cache to continuously supply the operands to the pipeline. The IBM System / 360 Model 91 is a typical example of a device with a scalar pipeline. However, there is no cache in Model 91. On the other hand, the vector pipeline is specially designed to process vector instructions for vector operands. A computer with vector instructions is called a vector processor, and the design of this vector processor extends from the design of a scalar pipeline. The processing of vector operands in the vector pipeline is under the control of firmware and hardware rather than under software control as in the scalar pipeline.

Next, the linear pipelining (linear pipelining) is as follows.

In a pipeline with constant delay, all tasks (the smallest unit of work processed by the computer) have the same processing time in all stations. Stations in an ideal production line run concurrently with sufficient resource usage. However, substantially consecutive stations do not have the same delay. The optimal distribution of a production line is influenced by many factors, including the quality of the working unit (efficiency and acceptability), the required processing speed and the cost of the entire production line.

Looking at the predecessor of the set of subtasks {T ₁ , T ₂ , ..., T _k } for a given task T, the task T that follows until the preceding task T _i (i <j) ends Indicates that _j does not start. The interdependencies of all subtasks form a precedence graph, and the linear pipeline can process a series of subtasks according to the linear preceding graph.

4 is a basic structural diagram of a linear pipeline processor, where L is a latch, C is a clock, and S _i is an i-th stage.

The pipeline shown in FIG. 4 consists of a cascade of processing stages, which are pure combinations that perform arithmetic or logic operations on the data stream flowing through the pipe. It is a combinational circuit. The stages are also separated by high speed interface latches. These latches are fast registers to maintain immediate results between stages. The flow of information between adjacent stages is controlled by a common clock applied to all latches simultaneously.

Next, the clock period, speedup, efficiency, and throughput of the linear pipeline will be described.

1) Clock period

The logic circuit in each stage S _i has a time delay, denoted τ _i . If the time delay of each interface latch is τ ₁ , the clock period of the linear pipeline may be expressed as follows.

The inverse of the clock period is represented by the frequency f = 1 / τ of the pipeline processor.

5 illustrates the overlapping operation of the linear pipeline

Once the pipe is filled, it will output one result per clock period independent of the number of stages. Ideally, a linear pipeline with k stages can handle n tasks within a T _k = k + (n-1) clock period, where k cycles are used to fill the pipeline or to complete the execution of the first task. N-1 cycles are required to complete the remaining n-1 tasks. Such number of tasks may be performed in a nonpipeline processor having the same function within a T ₁ = n * k time delay.

2) Speedup

The speedup of a k-stage linear pipeline processor for the same non-pipeline processor may be defined as follows.

The maximum speed increase a linear pipeline can provide is k, where k is the number of stages in the pipe. This maximum speed increase cannot be achieved completely because of data dependence between instructions, interrupts, program branch and other factors. The wait state caused by unordered instruction execution consumes many pipeline cycles.

After defining the clock period in Equation 1 and defining the speed increase in Equation 2, two units for measuring the performance of the linear pipeline processor will be described. The time interval in the space-time diagram shown in FIG. There is a time interval and a stage space, and a product of the time interval and the stage space is called a time-space span. A given time-space span can exist in a busy or idle state, but not both states at the same time. This concept is used to measure the performance of pipelines.

3) efficiency

The efficiency of a linear pipeline is measured by the percentage of busy time-space span over the total time-space span corresponding to the sum of all busy and idle time-space spans. That is, the efficiency of the pipeline can be defined as follows.

Where n represents the number of tasks (ie, instructions), k represents the number of pipeline stages, and τ represents the clock period of the linear pipeline. When n → ∞, it becomes η → 1, which means that the larger the number of tasks going through the pipeline, the better the efficiency of the pipeline. From Equation 2 and Equation 3, η = S _k / k can be obtained, which provides the efficiency of the linear pipeline from another perspective as the ratio of the actual speed increase to the ideal speed increase k. If n »k at steady state of pipeline, efficiency η should approach 1. However, this ideal case does not hold all the time due to program branches, interrupts, data dependencies and other factors.

4) Throughput

Throughput is defined as the number of results (tasks) that can be completed by the pipeline per unit of time, and this ratio reflects the computational power of the pipeline. That is, the throughput is defined as follows.

Where n is equal to the total number of tasks performed during the observation period kτ + (n-1) τ. Ideally, when η → 1, then ω = 1 / τ = f, which means that the maximum throughput of the linear pipeline is equal to frequency, which corresponds to one output result per clock period.

6 is a structural diagram of a plurality of conventional pipelines. The conventional plurality of pipelines includes a functional unit determination unit 100, a network 200, and a plurality of functional units 300-1 to 300-n.

Here, the functional unit determination unit 100 may include a function pipeline identifier (FP Id) of data streams (consists of a function pipeline identifier, first data, and second data) input from a memory (not shown). E) to generate a control signal to determine the function unit (FU).

In addition, the network 200 performs a switching role according to a control signal generated from the functional unit determiner 100.

In addition, the plurality of functional units 300-1 to 300-n have a parallel structure and perform independent functions according to the switching selection of the network 200, wherein each functional unit 300-1 is performed. Multiple stages within ˜300-n) are in series for sequential operation.

The conventional multiple pipeline as described above is an improvement of the linear pipeline described above, but the network 200 to properly transfer data to a plurality of functional units 300-1 to 300-n in parallel. Because of using, not only increases the volume of hardware, but also lowers the frequency of the clock and increases the consumption of the clock.

Accordingly, the present invention has been made to solve the above problems, and by hierarchically transferring data to a plurality of function units (FU) provided in parallel by using the switching information included in the input data stream It is an object of the present invention to provide a pipeline system having a hierarchical buffer structure that is designed to increase parallelism by increasing the number of virtual functional units and to greatly improve the data throughput of the pipeline.

A pipeline system having a hierarchical buffer structure according to the present invention for achieving the above object comprises: primary buffering means for primaryly switching and outputting data according to first switching information included in an input data stream; Secondary buffering means for secondaryly switching and outputting data in accordance with second switching information included in the data stream from said primary buffering means; Tertiary buffering means for receiving data from the secondary buffering means and acting as a buffer; And a plurality of functional units which receive data from the tertiary buffering means and perform respective functions.

According to the present invention as described above by using the switching information included in the input data stream to pass the data hierarchically to a plurality of functional units provided in parallel to increase the number of virtual functional units to improve parallelism as well as pipeline Can significantly improve the data throughput.

1 illustrates arithmetic pipelining

2 illustrates instruction pipelining

Figure 3 illustrates processor pipelining

4 is a basic structural diagram of a linear pipeline processor;

Figure 5 illustrates the overlapping operation of the linear pipeline

6 is a structural diagram of a plurality of conventional pipelines,

7 is a diagram illustrating a pipeline system having a hierarchical buffer structure according to the present invention.

* Explanation of symbols for main parts of the drawings

100: function unit determination unit 200: network

300-1 to 300-n: Plural function unit 400: Primary buffering means

400-1: primary storage unit 400-2: primary selection signal generator

400-3: primary switching unit 500: secondary buffering means

500A: secondary primary buffering means 500A-1: secondary primary storage

500A-2: secondary first selection signal generator 500A-3: secondary first switching unit

500B: secondary secondary buffering means 500B-1: secondary secondary storage

500B-2: secondary secondary selection signal generator 500B-3: secondary secondary switching unit

600: tertiary buffering means 600-1: tertiary primary storage unit

600-2: tertiary secondary storage unit 600-3: tertiary secondary storage unit

600-4: tertiary fourth storage unit 700: multiple functional units

700-1: first functional unit 700-2: second functional unit

700-3: third functional unit 700-4: fourth functional unit

S _i : i th stage L: latch

C: Clock M _i : i-th memory block

Proc. n: nth processor : j th subtask of the i th task

Hereinafter, the present invention will be described with reference to the accompanying drawings.

7 is a schematic diagram of a pipeline system having a hierarchical buffer structure according to the present invention, comprising: primary buffering means 400; Secondary buffering means 500; Tertiary buffering means 600; And a plurality of functional units 700. When the number of functional units 700 increases, the order of the buffering means (primary, secondary, tertiary, quaternary ...) is also increased. In this case, the input data stream is composed of SI1, SI2, and DATA, wherein SI1 represents first switching information corresponding to one bit, SI2 represents second switching information, and DATA represents data to be used in a functional unit. . SI1 and SI2 correspond to a functional unit identifier (fu Id.) As described in the prior art. As shown in FIG. 7, the primary buffering means 400 includes a primary storage unit 400-1; A primary selection signal generator 400-2; And a primary switching unit 400-3, the primary storage unit 400-1 has one input port and two output ports, and a first-in first-out method (FIFO). To process the data.

The secondary buffering means 500 includes secondary secondary buffering means 500A; And a secondary second buffering means (500B), wherein the secondary first buffering means (500A) includes a secondary first storage portion (500A-1); A second first selection signal generator 500A-2; And a secondary first switching unit 500A-3, and the secondary second buffering means 500B includes a secondary second storage unit 500B-1; A secondary second selection signal generator 500B-2; And a secondary second switching unit 500B-3. The secondary first storage unit 500A-1 and the secondary second storage unit 500B-1 have one input port and two output ports, and have a first-in first-out method (FIFO). Data is processed according to Out).

Meanwhile, the tertiary buffering means 600 includes a plurality of tertiary storage units, that is, a tertiary first storage unit 600-1, a tertiary second storage unit 600-2, and a tertiary third storage unit ( 600-3) and the tertiary fourth storage unit 600-4 have a parallel structure. Since the tertiary storage units 600-1 to 600-4 are final buffering means for transferring data to each functional unit at a later stage, the tertiary storage units 600-1 to 600-4 need to have one input port and one output port. First-In First-Out).

Finally, the functional units 700 include a plurality of functional units, that is, a first functional unit 700-1, a second functional unit 700-2, a third functional unit 700-3, and a fourth functional unit. (700-4) is a parallel structure.

Next, operation of the embodiment of the present invention configured as described above will be described.

This section describes the case where buffering is performed in the third order by providing only four functional units.

Referring to FIG. 7, the primary buffering means 400 primarily switches and outputs data according to the first switching information SI1 included in the input data stream. In detail, the primary storage unit In 400-1, the data stream is received and temporarily stored, and then two data are output. In the first selection signal generator 400-2, two first switching devices from the first storage 400-1 are output. Receives the information SI1 and outputs a primary data selection signal fds, and the primary switching unit 400-3 receives two data from the primary storage unit 400-1 and selects the primary data. Secondary first buffering means 500A constituting secondary buffering means 500 at a later stage by first switching two data in accordance with the primary data selection signal fds from the signal generator 400-2. And second secondary buffering means 500B, respectively.

The secondary buffering means 500 receives a data stream from the primary switching unit 400-3 of the primary buffering means 400, and receives the data stream according to the second switching information SI2 included in the data stream. Secondary switching output.

That is, the secondary first buffering means 500A secondly switches and outputs first data (data to be used in the first functional unit and the second functional unit) according to the second switching information SI2. As shown in FIG. 2, the secondary first storage unit 500A-1 receives the data stream from the primary switching unit 400-3 of the primary buffering unit 400, temporarily stores the data stream, and outputs two data by two. The secondary first selection signal generator 500A-2 receives two second switching information SI2 from the secondary first storage unit 500A-1 and receives a secondary first data selection signal sds-1. ) And the secondary first switching unit 500A-3 receives two first data from the secondary first storage unit 500A-1 and the secondary first selection signal generator 500A-. The second first data is secondarily switched according to the secondary first data selection signal sds-1 from And each of the output to the third buffering means 600, the third first storage means 600-1 and the third second storing means (600-2) for configuring.

Similarly, the secondary second buffering means 500B secondaryly switches and outputs second data (data to be used in the third functional unit and the fourth functional unit) in accordance with the second switching information SI2, more specifically. Looking at the secondary secondary storage unit 500B-1 receives a data stream from the primary switching unit 400-3 of the primary buffering means 400, and temporarily stores the data stream and then outputs two data. In addition, the secondary second selection signal generator 500B-2 receives two second switching information SI2 from the secondary second storage unit 500B-1 and receives a secondary second data selection signal ( sds-2), and the second secondary switching unit 500B-3 receives two second data from the second secondary storage unit 500B-1 to receive the second second selection signal generator. The second second data selection signal sds-2 from 500B-2 Secondary switching is performed and output to the third tertiary storage unit 600-3 and the tertiary fourth storage unit 600-4, which constitute the third tertiary buffering means 600.

Meanwhile, the tertiary buffering means 600 receives data from the secondary buffering means 500 and plays a buffer role, and then outputs one data, that is, the first functional unit 700-1 to be used. The first data is received from the tertiary first storage unit 600-1 and buffered, and the first data to be used in the second functional unit 700-2 at the rear end is stored in the tertiary second storage unit 600-2. Receives and buffers the second data to be used in the third functional unit (700-3) of the rear stage is received and buffered in the third tertiary storage unit (600-3), the fourth functional unit (700-4) of the rear stage The second data to be used in the third buffer unit 600-4 is received and buffered.

Finally, the plurality of functional units 700 receives respective buffered data from the tertiary buffering means 600 and performs each independent function.

The embodiments described above are merely illustrative in all respects and should not be construed as limiting, and all modifications that fall within the true spirit and scope of the present invention shall fall within the claims of the present invention.

As described above, according to the present invention, data is transmitted hierarchically to a plurality of functional units provided in parallel using switching information included in an input data stream, thereby increasing the number of virtual functional units to improve parallelism. The data processing power of the pipeline can be greatly improved, and dynamic virtual functions can be easily implemented depending on the application.

Claims (16)

Primary buffering means (400) for primarily switching and outputting data according to first switching information (SI1) included in the input data stream; Secondary buffering means (500) for secondly switching and outputting data according to second switching information (SI2) included in the data stream from the primary buffering means (400); Tertiary buffering means (600) for receiving data from the secondary buffering means (500) and acting as a buffer; And Pipeline system having a hierarchical buffer structure consisting of a plurality of functional units (700) for receiving data from the tertiary buffering means (600) to perform each function. 2. The apparatus of claim 1, wherein the primary buffering means comprises: a primary storage unit 400-1 that receives a data stream and temporarily stores the data stream; A primary selection signal generator 400-2 receiving two first switching information SI1 from the primary storage 400-1 and outputting a primary data selection signal fds; And receiving two data from the primary storage unit 400-1 and primarily switching the two data according to the primary data selection signal fds from the primary selection signal generator 400-2. Pipeline system having a hierarchical buffer structure, characterized in that consisting of the primary switching unit 400-3 to output. The method of claim 2, wherein the primary storage unit 400-1. A pipeline system with a hierarchical buffer structure, characterized in that it is adapted to process data in a first-in first-out manner. The pipeline system according to claim 2 or 3, wherein the primary storage unit 400-1 is implemented with one input port and two output ports. The method of claim 1, wherein the secondary buffering means 500 outputs the secondary data by secondary switching in accordance with the second switching information (SI2) included in the data stream from the primary buffering means (400) Secondary first buffering means 500A; And And a second secondary buffering means 500B for secondaryly switching and outputting second data according to the second switching information SI2 included in the data stream from the primary buffering means 400. Pipeline system with hierarchical buffer structure. The secondary primary storage unit 500A-1 of claim 5, wherein the secondary primary buffering means 500A receives the temporary data stream from the primary buffering means 400 and temporarily stores the data stream. Wow; A secondary first selection signal generator for receiving two second switching information SI2 from the secondary first storage unit 500A-1 and outputting a secondary first data selection signal sds-1. 500A-2); And Receives two first data from the secondary first storage unit 500A-1 and receives a secondary first data selection signal sds-1 from the secondary first selection signal generator 500A-2. According to the pipeline system having a hierarchical buffer structure, characterized in that consisting of a secondary first switching unit (500A-3) for switching and outputting two first data. The method of claim 6, wherein the secondary primary storage unit (500A-1). A pipeline system with a hierarchical buffer structure, characterized in that it is adapted to process data in a first-in first-out manner. The pipeline system according to claim 6 or 7, wherein the secondary primary storage unit (500A-1) is implemented with one input port and two output ports. The secondary secondary storage unit 500B-1 of claim 5, wherein the secondary secondary buffering unit 500B receives and temporarily stores a data stream from the primary buffering unit 400 and outputs the temporary stream. Wow; A secondary second selection signal generator for receiving two second switching information SI2 from the secondary second storage unit 500B-1 and outputting a secondary second data selection signal sds-2; 500B-2); And The second second data selection signal sds-2 received from the second second storage signal generator 500B-2 by receiving two second data from the second storage unit 500B-1. According to the pipeline system having a hierarchical buffer structure, characterized in that consisting of a secondary second switching unit (500B-3) for switching and outputting two second data. The method of claim 9, wherein the secondary secondary storage unit (500B-1). A pipeline system with a hierarchical buffer structure, characterized in that it is adapted to process data in a first-in first-out manner. 11. The pipeline system according to claim 9 or 10, wherein the secondary secondary storage unit (500B-1) is implemented with one input port and two output ports. The pipeline system having a hierarchical buffer structure according to claim 1, wherein the tertiary buffering means 600 includes a plurality of tertiary storage units 600-1 to 600-4 having a parallel structure. . 13. The pipeline system according to claim 12, wherein the plurality of tertiary storage units (600-1 to 600-4) are configured to process data in a first-in first-out manner. The pipeline having a hierarchical buffer structure according to claim 12 or 13, wherein the plurality of tertiary storage units 600-1 to 600-4 are implemented with one input port and one output port. system. The pipeline system according to claim 1, wherein a plurality of functional units (700-1 to 700-4) are in parallel structure for performing respective functions. 2. The pipeline system according to claim 1, wherein the order of the buffering means also increases as the number of functional units increases.