KR100221315B1 - A pipelined adder - Google Patents

Abstract

The present invention relates to a plurality of operand adder circuits, and more particularly, to a pipeline adder having a pipelined structure in which a merge adder that finally adds two outputs at the last stage of a Wallace tree has a reduced operation cycle period. The first sum group S [0: k-1] and the first carry C [k] by adding the first bit groups A [0: k-1] and B [0: k-1] to the period. A first adder 60 for outputting; In the second clock period, the first carry C [k] and the second bit group A [k: 2k-1] and B [k: 2k-1] are added to add a second sum S [k: 2k-1]) and a second adder 61 for outputting the second carry C [2k]; In the third clock period, the second carry C [2k] and the third bit group A [2k: 3k-1] and B [2k: 3k-1] are added to add a third sum S [2k: 3k-1]) and a third adder 62 for outputting a third carry C [3k]; And a fourth sum S [3k] by adding the third carry C [3k] and the fourth bit group A [3k: n-1], B [3k: n-1] to a fourth clock period. : n-1]) and a fourth adder 63 for outputting the fourth carry C [n]. The merge adder itself has a relatively large delay time compared to the delay time of the upper stage. By internalizing the internal circuit of the pipeline, the delay times of all stages are almost the same, so that the operating frequency of the entire pipeline is increased.

Description

Pipeline adder

The present invention relates to a multi-addition adder circuit, and more particularly, to a pipeline adder having a pipelined structure by constructing a merge adder that finally adds two outputs at the last stage of the Wallace tree.

In general, Wallace Tree is most widely used as a multioperand addition circuit that adds a plurality of operands which are used in computing devices, signal processing systems, and various special purpose chips of high-performance computers.

Here, Wallace Tree is C.S. See Wallace's article "A Suggestion for a Fast Multiplier" published in IEEE in 1964

1A illustrates the structure of a Wallace tree

As shown in FIG. 1A, the three adders in the first stage are three-input two-output full adders, the input line of the adder receives a partial row product of nine rows, and outputs a sum and a carry in the next adder. Output line (CARRY, SUM).

1B illustrates a modified Wallace tree

As shown in FIG. 1B, since the delay times of the carry output C and the sum output S of the full adder are different from each other, outputs having the same delay time are collected and processed. In this way, the modified Wallace tree has less gate latency than the existing Wallace tree. As the number of input bits in the tree increases, the gator delay time further decreases.

In this way, the Wallace tree forms a tree using a half adder, a full adder, or a counter, so that two or more operands can be calculated in the shortest time.

If there is a lot of data to be processed according to various application fields, the wallless tree shown above may be pipelined to perform parallel processing.

On the other hand, pipeline processing is one of the methods of speeding up data processing. In order to increase the efficiency of the system, two or more processors process different parts in parallel so that the result calculated by the previous processor can be used as the input of the next processor. do. In other words, the data that is continuously inputted at the end of the pipeline is processed sequentially in each stage of the pipeline, and the continuous output is obtained at the other end, and the data processing is physically divided by assigning them to each stage. Parallel processing is executed by the number of stages in one pipeline.

2 illustrates general pipeline processing

Therefore, the pipeline clock period is determined by the stage having the longest delay time in each stage as shown in the following equation.

[Equation 1]

In the above equation Each stage Is the delay time of Is the delay time for each interface latch, the longest stage delay Delay Time for Interface and Interface Latch Time Determined by the clock cycle of this pipeline, each interface latch is clocked To be motivated.

If you need to add massive data explained above

As an example, there is an adder structure proposed by the present inventor, which performs fast addition through a pipeline to which a Wallace tree is applied in the addition process required to obtain an absolute error value in motion estimation.

As shown in FIG. 1, since the Wallless tree has two output lines, two output values must be obtained by using a general adder to obtain the final sum value. This is a problem in the pipeline to which the Wallless tree is applied.

Here, it is helpful to understand the characteristics of the wallless tree, and the operation of the wallless tree for outputting four data as two data will be described with reference to FIGS. 3 and 4.

3 illustrates the characteristics of the Wallace tree that adds four data and outputs the data as two data.

As shown in FIG. 3, in the Wallace tree, four data are input and the bits of the same position are added and added together to generate a sum and carry, and the bits and carry corresponding to the sum generated. Two bits are output by considering the bits corresponding to (CARRY) as one data. Therefore, carry provision is prevented from occurring.

That is, four data A, B, C, and D are composed of 8 bits, and the same bit positions are added to each other. Groups of three bits of A, B, and C are added together. As a result, the sum SUM of each group becomes the weight corresponding to the same bit position, and the carry is the upper 1 bit position, and the bits of the same weight as each of the remaining D bits are added in groups of three again. As a result, the sum of each group SUM is the same bit position and the carry is the weight corresponding to the upper 1 bit position, so that two data X and Y form an output pair of the Willis tree.

At this time, up to 9 bits of the output two data X and Y are generated. However, when the two added data values are not very large according to the application, the most significant bit (carry) may not be considered.

Referring to FIG. 4, bits having the same weight of three data A, B, and C among the four input data shown in FIG. 3 are added through the eight first adders 41. Bits having the same weight in the sum and carry and the remaining input data output from the first full adder 41 are added through the seven second adders 42 to output two data X and Y.

The pipeline adder structure to which the wallless tree is applied is shown in FIG.

However, the merge adder of the last stage has the largest delay because it involves carry delay in adding the two outputs, so that the operating frequency of the whole system is determined by the delay time of the merge adder.

In the pipeline adder using the wallless tree, the final value is obtained by adding two pieces of data output from the wallless tree of the upper stage in the final stage.

At this time, the carry propagation time does not occur in the upper stage, that is, the wallless tree. However, because carry propagation occurs in the last stage, it has a considerably larger delay time than the delay time of the upper stage, so that the entire pipeline clock frequency is determined as the delay time of the last stage.

Therefore, in the upper stages, there is a problem that extra processing time corresponding to the difference between the current stage delay time and the last stage delay time remains.

Accordingly, the present invention has been devised to solve the above-mentioned problems. The delay adder of a merge adder having a round-up delay in the last stage of the pipeline is divided into less than or equal to the delay time of the remaining stages. Its purpose is to provide a pipeline adder with improved performance by increasing the overall operating frequency by performing pipeline processing with its own stages.

In order to achieve the above object, the pipeline adder of the present invention outputs one data by finally summing two binary data output from the last Wallace tree through pipeline processing configured as a Wallace tree according to a clock frequency f. In the merge adder for

The first bit group A [0: k-1], B [0: k-1], which is composed of a plurality of bits including the least significant bit of the input data (n bit data), is added to the first clock period. A first adder for outputting a sum S [0: k-1] and a first rounded number C [k]; The second sum period S [k] is added by adding the first round number C [k] and the second bit group A [k: 2k-1] and B [k: 2k-1] to a second clock period. : 2k-1]) and a second adder for outputting the second rounded number C [2k]; The third sum (S [2k) is added by adding the second rounded number C [2k] and the third bit group A [2k: 3k-1] and B [2k: 3k-1] to a third clock period. 3k-1] and a third adder for outputting a third rounded number C [3k]; And adding a third rounded number C [3k] and a fourth bit group A [3k: 4k-1], B [3k: 4k-1] to a fourth clock period to add a fourth sum S [S]. 3k: 4k-1] and a fourth adder for outputting the fourth rounded number C [4k].

The pipelined structure of the internal circuit of the merge adder itself, which had a relatively large delay time compared to the delay time of the upper stage, makes the delay time of all stages almost similar, thereby increasing the operating frequency of the entire pipeline compared to the past. Of course, the more load you have to process in parallel, the better performance you can expect.

1 illustrates the concept of a typical Wallace tree

1A is a basic Wallace tree structure diagram;

1B is a modified Wallace tree structure diagram;

Figure 2 illustrates general pipeline processing

Fig. 3 illustrates the Wallace tree operation of outputting four data as two data.

4 is a block diagram of a four input two output wallless adder implementing the wallless tree of FIG.

5 is a block diagram showing adders that can be used as a merge adder in a pipeline final stage.

5A is a block diagram for an 8-bit ripple adder;

5B is a block diagram for an 8-bit carry select adder;

5C is a block diagram for an 8-bit carry lookahead adder;

6 is a block diagram of a merge adder having a pipeline structure by subdividing the operation of the merge adder according to the present invention.

* Explanation of symbols for main parts of the drawings

60: first adder 61: second adder

62: third adder 63: fourth adder

L1 to L5: Latch

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, a general adder for adding two data output from the Wallace tree in the final stage of the pipeline will be described with reference to FIG. 5.

5 is a block diagram showing adders that can be used as a merge adder in a pipeline final stage, FIG. 5A is a block diagram for an 8-bit ripple adder, FIG. 5B is a block diagram for an 8-bit carry select adder, and FIG. 5C is 8 A block diagram for a bit carry predictor adder.

Referring to Figure 5a, 8-bit ripple adder adds the 8 binary parallel around the top (FA ₀ ~FA ₇₎ using the input signal X ₀ ~X ₇ and all the bits of Y ₀ ~Y ₇ at the same time. The output carry COUT = C ₁ from the first full adder FA ₀ becomes the input carry CIN = C ₁ of the next higher full adder FA ₂ , with each carry and sum being Can be obtained by

[Equation 2]

The ripple adder has a disadvantage in that it takes a very long time (carrie propagation delay) to propagate the generated carry to the next higher full adder (the next higher bit).

That is, while the input signals X ₇ and Y ₇ are ready to perform the addition process simultaneously with the input, the carry C ₇ cannot be set until carry C ₆ is propagated and for this reason C ₆ waits for C ₅ and C ₅ is therefore waiting for the _{C 4, C 1, C 2} , from the C ₀ ... The ripple carry adder outputs the normal and error-free sums S _0-7 and carry C _{8 only} when C ₇ is obtained through C ₆ , C ₆ .

Referring to FIG. 5B, the 8-bit carry select adder first adder 10 and the second adder 12, the third adder 14, the multiplexer 16, and the final carry output selector 18. It is composed of

First, assume that the 8-bit carry select adder receives and adds 8-bit input signals X _{0 to} X ₇ , Y ₀ to Y _7, and an initial external input signal C ₀ .

The first adding unit 10 receives and adds the lower 4 bit input signals X _{0 to} X ₃ and Y ₀ to Y ₃ , and the first external input signal C ₀ , and then adds the sums S _{0 to} S ₃ and the radio wave carry C. Outputs _4. Here, the propagation carry C ₄ is input to a selection signal (SEL) of the multiplexer 16.

The second adding unit 12 outputs the sum S _{4 to} S ₇ and the radio wave carry C _{8 0} when the radio wave carry C ₄ is "0". That is, the second adder 14 receives and adds the upper 4-bit input signals X _{4 to} X ₇ and Y ₄ to Y _7, and the radio wave carry "0", and then adds the sum S _{4 to} S ₇ and the radio wave carry C. Print ₈ Here, the sums S _{4 to} S ₇ are output as the input signal of the multiplexer 16 and the propagation carry C _{8 0} is output to the final carry selector 18.

The third adder 14 outputs the sum S _{4 to} S ₇ and the propagation carry C _{8 1} when the propagation carry C ₄ is "1". That is, the third adder 14 receives and adds the upper 4-bit input signals X _{4 to} X ₇ and Y ₄ to Y _7, and the radio wave carry "1", and then adds the sum S _{4 to} S ₇ and the radio wave carry C. Print ₈ Here, the sums S _{4 to} S ₇ are output as the input signal of the multiplexer 16 and the propagation carry C _{8 1} is output to the final carry selector 18.

The multiplexer 16 selecting and outputting the sum S ₄ ~S ₇ from the third addition unit 14 and the sum S ₄ ~S ₇ from the second addition unit 12 according to the selection signal C ₄ Let's do it. The final carry output selecting section 18 outputs to receiving the radio waves carry C ₄ and (C _{8) 0} and (C _{8) 1} selects the radio waves carry (C _{8) 0} and (C _{8) 1.}

That is, when the final carry C ₈ is developed as a logical equation, it is expressed as Equation 3 below.

[Equation 3]

The carry select adder has the disadvantage of having a signal adder due to a redundant adder used for carry selection, a multiplexer and a final carry selector.

Referring to FIG. 5C, the 8-bit carry prediction adder includes a carry generate signal G _i generator 20, a carry propagate P _i generator 22, and a carry generator 24. ) And an adder 26.

The carry generation signal generator 20 is configured by an AND gate, and when the input signals X _i and Y _i are both “1”, the carry output C _{i + 1 is set} to “1” regardless of the carry input C _i . "

The carry propagation signal generator 22 includes an exclusive logic gate, and when only one of the input signals X _i and Y _i is “1”, the carry output C _{i + 1 is set} to “1” regardless of the carry input C _i . Make it.

The carry generator 24 receives the carry generation signal G _i , the carry propagation signal P _i, and the first external carry C ₀ to generate a predicted carry C _{i + 1} and output the generated carry C _{i + 1} to the adder 26.

The addition section 8 outputs the sum S _i in addition to the carry propagate signal P _i and the predicted carry-C _i.

The sum S _i defined by the carry propagation signal and the predicted carry is logically developed as follows.

[Equation 4]

The carry generation signal G _i and the carry propagation signal P _i are logically developed as shown in Equation 5 below.

[Equation 5]

Then, when the prediction carry C _{i + 1} defined by the carry generation signal and the carry propagation signal is developed in a logical formula, the following equation (6) is obtained.

[Equation 6]

According to the predictive carry logic, the predicted carry C _{1 to} C ₄ are obtained as shown in the following equations (7) to (10).

[Equation 7]

[Equation 8]

[Equation 9]

[Equation 10]

As described in the above equation, the predictive carry output C _{i + 1} may be generated in advance by the input signals X _i and Y _i and the first external carry C ₀ irrespective of the carry input C _i , so the carry predict adder carries a carry propagation delay. To increase the addition speed. However, the predictive carry C _{1 to} C ₄ are expressed as 2 level NAND gates, but the weight of the predicted carry (C ₀ = 2 ⁰ , C ₁ = 2 ¹ , C ₂ = 2 ² ,…, C _2n = 2 ⁿ If) continues to increase, the prediction carry can no longer be represented by a two-level NAND gate.

In other words, although the carry propagation delay is most effectively eliminated, as the weight of the predicted carry increases, the complexity of the predicted carry generation logic also increases, thus increasing the configuration hardware, thus increasing the critical path required to obtain the final result.

On the other hand, the critical path of the wall tree is a path passing through the first full adder and the second full adder, as shown in Figure 4, the critical path of the conventional general adder described above, as shown in Figure 5, the carry generation unit or Since the carry propagation part is added or the carry prediction part is added, it has a significantly larger critical path compared to the critical path of the Wallace tree, and thus a long delay time.

Therefore, the present invention is to subdivide the final stage with the longest delay time to balance the delay time of each stage and to increase the operating frequency.

6 is a block diagram illustrating an adder having a pipeline structure by subdividing the operation of the merge adder according to the present invention.

As shown in Fig. 6, the input of the pipeline adder is two data X [0: 7], Y [0: 7] composed of 8 bits, and the input data are divided by two bits to provide data bits A [0: 1], B [0: 1] is the first group of bits, data bits A [2: 3], B [2: 3] are the second group of bits, data bits A [4: 5], and B [4: 5] are Assume that the 3 bit group, data bits A [6: 7], B [6: 7] are the fourth bit group.

The pipeline adder is composed of first to fourth adders 60 to 63 and first to fifth latch portions L1 to L5.

The first latch unit L1 latches all the bit groups A [0: 7] and B [0: 7] of the two data inputs, and the first adder 60 inputs the first data bit. The groups A [0: 1] and B [0: 1] are added to output the first sum S [0: 1] and the first carry C [2].

The second latch part L2 may include a first sum S [0: 1], a first carry C [2], and a second to fourth bit group output from the first adder 60. L [2: 7], B [2: 7]).

The second adder 71 adds the first carry C [2] and the second bit groups A [2: 3] and B [2: 3] to add a second sum S [2:]. 3]) and the second carry C [4].

The third latch portion L3 has a first sum S [0: 1] output from the first adder 60 and a second sum S [outputted from the second adder 71. 2: 3]), the second carry C [4] and the third to fourth bit groups A [4: 7], B [4: 7].

The third adder 62 adds the second carry C [4] and the third bit group A [4: 5], B [4: 5] to add a third sum S [4: 5]) and the third carry C [5].

The fourth latch portion L4 has a first sum S [0: 1] output from the first adder 60 and a second sum S [2] output from the second adder 61. 3) the third sum S [4: 5], the third carry C [6], and the fourth bit group A [6: 7], output from the third adder 62; B [6: 7]) is latched.

The fourth adder 63 adds the third carry C [6] and the fourth bit group A [6: 7], B [6: 7] to add a fourth sum S [6: 7]) and the fourth carry C [8].

The fifth latch L5 includes a first sum S [0: 1] output from the first adder 60 and a second sum S [2: output from the second adder 61. 3]), and the third sum S [4: 5] output from the third adder 62 and the fourth sum S [6: 7] output from the fourth adder 63. Latch.

Next, the operation and effects of the present embodiment will be described in detail.

The pipeline adder of the present invention adds binary input data A [0: 7], B [0: 7], during the first clock, through the first adder 60, the first sum S [0: 1. ] And the first carry C [2], and during the second clock, calculate the second sum S [2: 3] and the second carry C [4] via the second adder 61, and the third clock. In the meantime, the third sum S [4: 5] and the third carry C [6] are calculated through the third adder 62 and the fourth sum S [6: through the fourth adder 63 during the fourth clock. 7] and the fourth carry C [8]. That is, the final sum S [0: 7] of the two input data during the fifth clock is calculated.

In summary, when producing a pipeline structure by applying a Wallace tree to process a plurality of data in parallel, the final stage has to sum two output data and obtain one result value. In this case, since the merge stage inevitably uses the carry adder, the final stage has a relatively long delay time, and the long pipeline time determines the total pipeline clock frequency.

Therefore, by segmenting the long delay time of the merge adder, that is, by dividing the merge adder internal circuit into several stages and performing pipeline processing, the overall pipeline clock frequency has a relatively high frequency and the processing speed is improved. It is.

Of course, as the number of stages increases, the initial delay time until the output value for the first input data is increased, but the processing speed is improved due to the fast clock frequency, and higher efficiency can be expected when the amount of data is quite large.

The pipelined structure of the internal circuit of the merge adder itself, which had a relatively large delay time compared to the delay time of the upper stage, makes the delay time of all stages almost similar, thereby increasing the operating frequency of the entire pipeline compared to the past. Of course, the more load you have to process in parallel, the better performance you can expect.

Claims (3)

In the merge adder for outputting one data by finally summing the two binary data output from the last Wallace tree through the pipeline processing consisting of the Wallace tree according to the clock frequency f, The first bit group A [0: k-1], B [0: k-1], which is composed of a plurality of bits including the least significant bit of the input data (n bit data), is added to the first clock period. A first adder 60 outputting a sum S [0: k-1] and a first carry C [k]; In the second clock period, the first carry C [k] and the second bit group A [k: 2k-1] and B [k: 2k-1] are added to add a second sum S [k: 2k-1]) and a second adder 61 for outputting the second carry C [2k]; In the third clock period, the second carry C [2k] and the third bit group A [2k: 3k-1] and B [2k: 3k-1] are added to add a third sum S [2k: 3k-1]) and a third adder 62 for outputting a third carry C [3k]; And In the fourth clock period, the third carry (C [3k]) and the fourth bit group A [3k: n-1] and B [3k: n-1] are added to add a fourth sum S [3k: n-1]) and a fourth adder (63) for outputting a fourth carry (C [n]). 2. The first latch unit (L1) according to claim 1, further comprising: a first latch portion (L1) for latching all bit groups (A [0: n], B [0: n]) of two data inputted; The first sum S [0: k-1] and the first carry C [k] and the second to fourth bit groups A [k: n], output from the first adder 60, A second latch portion L2 for latching B [k: n]); A first sum S [0: k-1] output from the first adder 60 and a second sum S [k: 2k-1] output from the second adder 61. A third latch portion L3 for latching the second carry C [2k] and the third to fourth bit groups A [2k: 3k-1] and B [2k: 3k-1]; A first sum S [0: k-1] output from the first adder 60 and a second sum S [k: 2k-1] output from the second adder 61; The third sum S [2k: 3k-1], the third carry C [3k] and the fourth bit group A [3k: n-1], B output from the third adder 62 A fourth latch portion L4 for latching [3k: n-1]); A first sum S [0: k-1] output from the first adder 60 and a second sum S [k: 2k-1] output from the second adder 61; Latching a third sum S [2k: 3k-1] output from the third adder 62 and a fourth sum S [3k: n] output from the fourth adder 63. Pipeline adder, characterized in that the fifth latch portion (L5) is further added. The pipeline adder according to claim 1, wherein the first to fourth adders (60 to 63) comprise full adders for adding a plurality of bits to at least one bit.