KR100219068B1 - Row decoder of memory device - Google Patents

Abstract

The present invention supplies a full-high supply voltage (Vcc) level to a word line connected to a cell in order to select a cell, but the voltage level supplied to the word line when the selected cell performs an equalization or write recovery operation. Is supplied to a value that is separated from the full-high by a predetermined value, and a voltage level lower than the full-high voltage level is supplied to the gate of the access transistor of the SRAM cell during a station equalization or recovery operation so that data latched to the cell node is stored. This is to prevent distortion.

Description

Low Decoder of Semiconductor Memory Device

1 is a partial core circuit diagram of a typical SRAW.

2 is a conventional low decoder.

3 is a transition simulation waveform diagram of a conventional low decoder.

4 is a cell current simulation waveform diagram by a conventional low decoder.

5 is a low decoder according to an embodiment of the present invention.

6 is a waveform diagram of a supply power supply voltage (Vcc) versus a voltage of a word line when a low decoder according to an embodiment of the present invention is used.

7 is a transition simulation waveform diagram of a low decoder according to an embodiment of the present invention.

8 is a waveform diagram of a cell current simulation by a low decoder according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

51: section decoder 53: control logic

52: global decoder 54: word line voltage level converter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low decoder in a semiconductor memory device, and more particularly, to a low decoder for controlling a word line to select a cell in a cell array.

In general, a memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a read only memory (ROM), or the like, first selects a cell in which data is stored or to store data for read and write operations. To this end, each cell has a word line driven by a row decoder and a bit line driven by a column decoder.

FIG. 1 is a partial core circuit diagram of a conventional SRAM. As shown in the drawing, a word line W is connected to gates of the access transistors MN1 and MN2 of the SRAM cell 11, and the access transistors MN1 and MN2. The bit line pair (Bit, / Bit) is connected to the drain. The transistors include transistors MP1 and MP2 for precharging bit lines for stable read and write operations, and transistors MP3 for equalizing bit line pairs Bit and Bit. The transistors MP1, MP2, and MP3 are gated to the control signal EQ, respectively.

FIG. 2 is a conventional low decoder, which consists of simple logic of the CMOS inverter 23 type controlled by the output signals of the section decoder 21 and the global decoder 22.

That is, when the output signal of the global decoder 22 is enabled at the logic level 'Low', the word line whose output signal of the section decoder 21 is 'High' is selected. .

For reference, a low decoder having the configuration as shown in FIG. 2 is used in a memory device that blocks a whole number of memory cells by a predetermined number and blocks each block.

However, such a conventional low decoder is likely to cause a problem in memory cell operation at Vcc, which is a full-high voltage level. That is, since the selected word line has Vcc, which is a full high voltage level, and drives the access transistor of the SRAM cell at the full high voltage level, the bit line Bit // during the write recovery operation or equalization operation is performed. Bit) affects a cell node when the access transistor is turned on while being precharged and equalized, causing the latched cell data to be distorted.

3 is a transition simulation waveform diagram of the conventional low decoder, showing that the voltage of the cell node is 0.31V, and FIG. 4 is a cell current simulation waveform diagram of the conventional low decoder, and the cell current is 62 mA. There will be supplementary explanations for this in one embodiment of the invention which will be described later.

It is an object of the present invention to provide a low decoder of a semiconductor memory device which prevents distortion of data stored in a cell node during a write recovery operation and an equalization operation.

A low decoder of the present invention for achieving the above object is a low decoder of a semiconductor memory device which drives a word line under the control of an output signal of a section decoder and a global decoder, and is connected between a power supply terminal and a word line and is connected to the section decoder. A pull-up transistor receiving the output of the gate signal; A pull-down transistor connected between the word line and a ground power supply terminal and receiving an output of the section decoder as a gate signal; Control means for outputting a control signal that is activated when a cell connected to the word line is in a write recovery operation or when a bit line of the cell is equalized in response to a write recovery signal and a bit line equalization signal; And a plurality of transistors configured to form a current path between the word line and the output terminal of the global decoder in response to the output signal of the section decoder and the control signal, wherein the word line has a power supply by the pull-up transistor. Word line level converting means which is enabled when a cell connected to the word line is write recovered or when the bit line of the cell is equalized to bring the word line down by a threshold voltage of the plurality of transistors from a power supply; It is characterized by comprising.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

5 is a low decoder according to an embodiment of the present invention. Referring to FIG. 5, a cell is selected by a pull-up or pull-down driving of a word line W under the control of an output a of the section decoder 51. A cell having a pull-up transistor (MP5) and a pull-down transistor (MN6) for non-selection, and connected to the word line (W) in response to the write recovery signal (WR) and the bit line equalization signal (EQ), is a light recovery operation. Or a control logic unit 53 for outputting a control signal C that is activated when the bit line of the cell is equalized, and in response to the output signal of the section decoder 51 and the control signal C. A plurality of transistors constituting a current path between a word line (W) and an output terminal of the global decoder (52), the word line having a power supply by the pull-up transistor, and a cell connected to the word line is a light leaker A word line voltage level converting unit 53 is enabled when discarded or when the bit line of the cell is equalized, thereby lowering the word line by the threshold voltage of the plurality of transistors from a power supply.

Specifically, the pull-up transistor MP5 is configured as a PMOS transistor as a PMOS transistor connected between the power supply terminal and the word line W, and receiving the output a of the section decoder 51 as a gate signal. The MP6 is implemented by an NMOS transistor connected between the word line W and the ground power supply terminal and receiving the output a of the section decoder 51 as a gate signal.

The control logic unit 54 drives in response to the light recovery signal WR and the bit line equalization signal EQ, which are signals for controlling the light recovery operation and the bit line equalization operation. It consists of a logic circuit that makes the signal active when it is recovered or when the bit line of the cell is equalized. The embodiment may be variously implemented by those skilled in the art.

In the word line voltage level converter 54, a plurality of NMOS transistors MN7, MN8, and MN9 are connected in series so that a current path is formed between the word line W and the output terminal of the global decoder 52. The NMOS transistors MN7 and MN8 receive the inverted output signal of the section decoder 51 by the inverter I2 to the gate, respectively, and operate the switching. The NMOS transistor MN9 gates the output signal c of the control logic unit 53. It is applied to switch and operates.

A low decoder according to an embodiment of the present invention having the above configuration supplies a full-high supply voltage (Vcc) level to a word line connected to a cell in order to select a cell, but the bit line of the selected cell When the equalization operation or the selected cell performs the write recovery operation, the voltage level supplied to the word line is supplied at a value lower than the full-high supply voltage by the threshold voltages of the NMOS transistors MN7, MN8, and MN9. . As a result, during an equalization or write recovery operation, a voltage level lower than the full-high supply voltage level is supplied to the gate of the access transistor of the SRAM cell, thereby preventing the latched data of the cell node from being distorted.

A detailed operation of the low decoder having the above configuration will be described with reference to FIGS. 5 and 6 to 8.

FIG. 6 is a waveform diagram of a voltage of a power supply voltage Vcc vs. a word line when a low decoder according to an embodiment of the present invention is used.

As shown in the figure, when the supply power supply voltage Vcc of the chip is used as 3 V, the output a of the section decoder 51 and the output b of the global decoder 52 and the control logic unit ( In the case where the outputs c of the 53 are all low (0 V), 3 V is applied to the word line, but the output a of the section decoder 51 is the low (0 V), and the control logic portion 53 If the output (c) of the circuit is high (5V), all the transistors MN7, MN8, and MN9 formed between the word line (W) and the output terminal (b) of the global decoder 52 are turned on to provide a current path. By forming, the word line voltage is applied at about 2.1V apart.

That is, when the output (a) of the section decoder 51 is 'low (0V)' and the output (c) of the control logic unit 53 is 'high (5V)', the cell is selected and the word line is opened. When equalization or write recovery is performed, it can be seen that 2.1V, which is lower than the full-high voltage level (Vcc = 3V), is applied to the word line.

7 is a transition simulation waveform diagram of a low decoder according to an embodiment of the present invention. When the write recovery and equalization are enabled when the word line is actually turned on (high), the word line W is 2.2. Shows falling to V The cell node voltage is also stable at 0.17V. It will be easily compared to FIG. 3, which is a conventional waveform diagram.

FIG. 8 is a waveform diagram of a cell current simulation by a low decoder according to an embodiment of the present invention, and it can be seen that 37 μs flows due to 25 μs lower than that of FIG. 4.

According to the present invention, it is possible to perform stable operation even if the operating range of the supply power supply voltage (Vcc) is wide, so that a low decoder requiring a high-speed operation or a high-definition supply voltage is required. Is suitable as. In particular, it can be employed in a memory device operating a high-speed switch, such as fast SRAM.

The technical idea of the present invention has been described in detail according to the above preferred embodiment. It should be noted that the above embodiment is for the purpose of illustration and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (3)

A low decoder of a semiconductor memory device which drives a word line under the control of an output signal of a section decoder and a global decoder, comprising: a pull-up transistor connected between a power supply terminal and a word mine and receiving the output of the section decoder as a gate signal; A pull-down transistor connected between the word line and a ground power supply terminal and receiving an output of the section decoder as a gate signal; Control means for outputting a control signal that is activated when a cell connected to the word line is in a write recovery operation or when a bit line of the cell is equalized in response to a write recovery signal and a bit line equalization signal; And a plurality of transistors configured to form a current path between the word line and the output terminal of the global decoder in response to the output signal of the section decoder and the control signal, wherein the word line has a power supply by the pull-up transistor. Word line voltage level converting means which is enabled when a cell connected to the word line is write recovered or when the bit line of the cell is equalized to bring the word line down by a threshold voltage of the plurality of transistors at a power supply; Low decoder of a semiconductor memory device comprising a. The word line voltage level converting means comprises: first, second and third transistors connected in series between the word line and the output terminal of the global decoder and an inverter for inverting the output of the section decoder. And the first and third transistors are supplied with the output of the inverter as a gate, and the second transistor is applied with the control signal as a gate. 3. The low decoder of claim 2, wherein the first, second, and third transistors and the pull-down transistor are en-mo transistors, respectively, and the pull-up transistors are PIM transistors. 4.