KR100212151B1 - Structure of a non-volatile semiconductor memory device and a manufacturing method for the same - Google Patents

Abstract

The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device including a memory device memory cell, a selection transistor for controlling input / output of a memory cell, and a peripheral circuit transistor, Depositing a first polysilicon film on the first polysilicon film, selectively removing the first polysilicon film to form a window on the field oxide film of the memory cell to be formed, forming an interlayer insulating film on the first polysilicon film Selectively removing the interlayer insulating film to form a window separated by at least one active region and a field oxide film on a field oxide film in a region where the selective transistor is to be formed; And depositing a film.

Description

Structure of Nonvolatile Memory Device and Manufacturing Method Thereof

The present invention relates to a nonvolatile memory device in which a memory cell for storing data and a selection transistor for selecting a memory cell are connected in a NAND type and a method of manufacturing the same. More particularly, the present invention relates to a nonvolatile memory device having two or more bits Lines connected to a single contact and a method of manufacturing the same.

A memory cell storing data has a structure in which a first polysilicon film insulated with an oxide film and a second polysilicon film insulated with an interlayer insulating film are stacked on a single crystal semiconductor substrate. The storage and erasing of data in such a memory cell structure consists of injecting or discharging electrons into the first polysilicon film by applying an appropriate voltage between the substrate and the second polysilicon film, And the second polysilicon film is referred to as a control gate.

On the other hand, the select transistor for selecting a memory cell has the same structure as a memory cell, but does not require a floating gate for data storage and electrically shows a single-layer polysilicon film structure, so that the first polysilicon film and the second poly A step of forming a single gate structure by contacting a silicon film is required.

Conventional techniques for contacting the first polysilicon film with the second polysilicon film include a method of forming a butting contact on a field oxide film added to a part of a cell array and a method of etching an interlayer insulating film on a selection transistor . The method of forming the butting contact has a problem that the area of the field oxide where the butting contact is formed is used in addition to the field oxide film which separates the active region, thereby increasing the cell array area and also increasing the resistance of the cell array as a whole.

On the other hand, one of the prior art methods of etching the interlayer insulating film on the select transistor is disclosed in U.S. Patent No. 4,789,431, which is a method of etching an ONO (interlayer insulating film formed of oxide-nitride-oxide) Since the first polysilicon film and the second polysilicon film are directly connected to each other, an additional area for the butting contact is not needed, which is advantageous in reducing the area. However, when the etched portion of the ONO film is etched without being completely masked in the process of successively etching the tungsten silicide film, the second polysilicon film, the ONO film, and the first polysilicon film, the tungsten silicide film, , The first polysilicon film, the gate oxide film, and the substrate proceed in that order, and pitting occurs in the active region. In order to solve this problem, the selection transistor must be formed larger than the portion where the ONO film is etched. This prevents the channel length of the selection transistor from being reduced, which is a great obstacle to high integration of the memory cell.

In order to solve the above problems, a method of etching an ONO film on a field oxide film has been used as a new attempt. In this method, there is a method of etching only the ONO film and a method of etching the second polysilicon film and the ONO film after the second polysilicon film is deposited.

First, referring to FIGS. 6A and 6B, a method of etching only the ONO film will be described. (Here, the left side of FIG. 6 shows a select transistor region and the right side shows a memory cell region).

A field oxide film 62 is formed on the silicon substrate 60 to define an active region and then a gate oxide film 64 is grown to form the structure of FIG. 6A. Then, as shown in FIG. 6B, The silicon film 66 is deposited and the first polysilicon film in the memory cell region is selectively etched to form a memory cell pattern. Next, a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially stacked on the entire surface of the substrate to form an ONO film 70 on the substrate surface as shown in FIG. 6C.

Then, a normal photolithography process is performed to form a photoresist 72 pattern in which a field region of the selection transistor region is opened as shown in FIG. 6D, and then an ONO film on the field region is selectively etched by a normal etching process Thereby forming the window 74. [0050] The photoresist 72 is removed and the second polysilicon film 76 and the tungsten silicide film 78 are successively deposited on the entire surface of the substrate as shown in FIG. The first polysilicon film 66 and the second polysilicon film 76 / the tungsten silicide film 78 are brought into contact with each other to form a single layer polysilicon film.

The method of etching the ONO film after depositing the second polysilicon film will be described with reference to FIGS. 7A to 7F. (Here, the left side of FIG. 7 shows the select transistor region and the right side shows the memory cell region. ).

First, as shown in FIG. 7A, a field oxide film 62 is formed on a semiconductor substrate 60 to define an active region, and then a gate oxide film 64 is grown on the entire surface of the substrate. 7B, a first polysilicon film 66 is deposited on the entire surface of the substrate, and the first polysilicon film deposited in the field region of the memory cell region is selectively removed by a conventional photolithography and etching process After the memory cell pattern is formed, the ONO film 70 is deposited on the entire surface of the substrate as shown in FIG. 7C.

7D, the second polysilicon film 80 is deposited on the entire surface of the substrate, followed by a normal photolithography and etching process. Then, as shown in FIG. 7E, The second polysilicon film and the ONO film are selectively removed to expose the first polysilicon film 66.

Then, as shown in FIG. 7F, a tungsten silicide film 86 is deposited on the entire surface of the substrate to contact the exposed first polysilicon film and the second polysilicon film / tungsten silicide film, Thereby forming a polycide film structure.

Since the etching of the ONO film is performed in the field oxide film area instead of the active area in which the select transistor is formed, the additional area for the butting contact is not required, so that the size of the cell array can be reduced and the tungsten silicide film, Even when the polysilicon film, the ONO film, and the portion where the ONO film is etched at the time of etching the first polysilicon film are not completely masked, the portion where the ONO film is etched is the tungsten silicide film, the second polysilicon film, A part of the field oxide film can be etched, but the occurrence of the fitting on the substrate can be prevented. Further, since the second polysilicon film and the first polysilicon film are directly in contact with each other over the numerous field oxide films in the cell array, when a voltage is applied to the gate of the selection transistor, a polycide structure composed mainly of a tungsten silicide film / And the resistance of the entire cell array is reduced.

However, unlike the single bit line structure, since there are two or more selection transistors in the shared bit line structure, as shown in FIG. 8, when the region 106 in which the ONO film is etched exists on the field oxide film, An additional new problem arises. First, as shown in FIG. 9, the central region of the field oxide film becomes convex due to the wafer loading effect during the photolithography process. In this case, even if the region 106 in which the ONO film is etched invades the active region or is not invaded, the tungsten silicide film for forming the gate is formed in the cell array, During the etching of the film, the ONO film and the first polysilicon film, as shown in Fig. 10, the loss of the field oxide film induces the fitting 114 in the substrate. Finally, considering the loading effect, there is a disadvantage that the margin of the photographic process is reduced. The disadvantage of this is that the area of the field becomes smaller as the memory cells are highly integrated, which is a further problematic process. When the ONO film is etched after the second polysilicon film is deposited, the ONO film between the first polysilicon film and the second polysilicon film is etched in the cleaning step before the tungsten silicide film is immersed, and after the tungsten silicide film is deposited A tungsten silicide film is present in the region where the ONO film is etched. In this case, a tungsten silicide film is left in the tungsten silicide film, the second polysilicon film, the ONO film, and the region 106 in which the ONO film is etched when the first polysilicon film is etched to form a gate in the cell array, There is a problem that the selected lines are electrically short-circuited.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-described problems of the prior art, and it is an object of the present invention to provide a semiconductor device and a manufacturing method thereof that can prevent fitting to the substrate during etching of an insulating film formed on the first polysilicon film, And a method of manufacturing the non-volatile memory device.

In order to achieve the above object, a nonvolatile memory device according to the present invention is a nonvolatile memory device having a memory cell in which two or more selection transistors are connected in series and stores data, The first conductor, the interlayer insulating film, and the second conductor are sequentially stacked on the insulating film, and at least one structure in which the first conductor and the second conductor are continuously stacked is formed on the upper portion of the element isolation film adjacent to the channel region of the selection transistor And the element isolation films adjacent to the source / drain regions between the active regions and the element isolation films and adjacent to each other between the active regions are thicker than the device isolation films between the memory cells.

A nonvolatile memory device manufacturing method according to the present invention is a nonvolatile memory device manufacturing method comprising a memory cell and a selection transistor and a peripheral circuit transistor for controlling input and output of a memory cell and comprising a field oxide film and a gate oxide film, Depositing a first polysilicon film on the first polysilicon film, selectively removing the first polysilicon film to form a window on the field oxide film of the memory cell to be formed, forming an interlayer insulating film on the first polysilicon film Selectively removing the interlayer insulating film to form a window separated by at least one active region and a field oxide film on a field oxide film in a region where the selective transistor is to be formed; And depositing a film.

And further depositing a tungsten silicide film on the second polysilicon film.

According to another aspect of the present invention, there is provided a method for fabricating a nonvolatile memory device, comprising: depositing a second polysilicon film on an upper surface of the interlayer insulating film after forming the interlayer insulating film; selectively removing the second polysilicon film and the interlayer insulating film Forming at least one active region and a window separated by a field oxide film on the field oxide film in the region where the selective transistor is to be formed, and forming a conductive film on the resultant film.

The conductive film is preferably formed of a tungsten silicide film.

1 is a cell layout diagram of a nonvolatile memory device according to an embodiment of the present invention;

2 is a cell layout diagram of a nonvolatile memory device according to another embodiment of the present invention.

3 is a cell layout diagram of a nonvolatile memory device according to an embodiment of the present invention.

4 is a view for explaining an embodiment of a nonvolatile memory element manufacturing method of the present invention.

5 is a view for explaining another embodiment of the nonvolatile memory element manufacturing method of the present invention.

6 is a view for explaining a conventional nonvolatile memory device manufacturing method.

7 is a view for explaining another nonvolatile memory element manufacturing method of the prior art;

8 is a layout diagram of a conventional nonvolatile memory device.

9 is a view showing a shape of an ONO film modified by a loading effect in the prior art.

10 is a view showing that a fitting is generated in a substrate in etching a gate pattern in the prior art.

DESCRIPTION OF REFERENCE NUMERALS

10, 100: memory cell regions 12, 102:

14, 104: polysilicon film etching region 16, 16a, 106, 108: ONO film etching region

20, 60: silicon substrate 22, 62: field oxide film

24, 64: gate oxide film 26: tunnel oxide film

28, 66: first polysilicon film 30, 36, 54, 68, 74, 84:

32, 70: ONO film 34, 52, 72, 82:

38, 50, 76, 80: second polysilicon film 40, 56, 78, 86: tungsten silicide film

110: Field oxide film before etch 112: Field oxide film after etching

114: Fitting

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings showing specific embodiments thereof.

A cell layout structure of a nonvolatile memory device according to an embodiment of the present invention is shown in FIG. In the shared bit line structure, two or more select lines are present. In the present invention, when the region 16 in which the ONO film of the one select line SSL1 is etched is formed on one field region, The ONO film etching area 16a is formed on the Y-axis direction of the one-field area, that is, not on the straight line in the bit line direction, but above the adjacent field area, so that the ONO etching areas as a whole are arranged in a zig- do. Therefore, the phenomenon that the region 16 in which the ONO film is etched between the selection line and the selection line is exposed to the upper portion of the active region due to the loading effect does not occur. In addition, in the zigzag shape, the region 16 in which the ONO film is etched is positioned so as to be spaced apart from the region where the contact is formed so that the ONO film is etched in the upper portion of the active region due to misalignment in the Y- 16 can be prevented from being exposed. In addition, since there is no pattern on the adjacent field oxide film, it is possible to easily perform the process in the photolithography process even in a highly integrated memory cell.

2 and 3 are views showing a cell layout structure of a nonvolatile memory device according to a modified embodiment of the present invention, in which the area 16 in which the ONO film is etched has a layout structure different from that in FIG.

4A to 4E are views showing one embodiment of a method for manufacturing a nonvolatile memory device according to the present invention, and show a method of etching an ONO film before depositing a second polysilicon film (here, Transistor region and the right side represents a memory cell region).

4A, a field oxide film 22 is formed on a p-type silicon substrate 20 by a LOCOS process to define an active region and a field region. In this case, At this time, in the manufacturing method of the present invention, it is not necessary to additionally form a field oxide film having a large area, unlike the conventional art in which the butting contact is formed. Next, a thermal oxidation process is performed to form a gate oxide film 24 having a thickness of about 200 ANGSTROM to be a gate insulating film of the selection transistor of the cell array and the peripheral circuit transistor. Next, a photolithography process is performed to form a photoresist pattern (not shown) in which a memory cell region of the cell array is opened. Then, the gate oxide film formed in the memory cell region is selectively removed by a wet etching process, A tunnel oxide film 26 is formed on the entire surface of the substrate to a thickness of about 90 Å in a dry thermal oxidation process in a diffusion furnace. A gate oxide film 24 of about 250 Å is formed in the select transistor region, A tunnel oxide film 26 of about 90 angstroms is formed.

Next, a first polysilicon film 28 to be used as a floating gate of a memory cell is deposited on the entire surface of the substrate to a thickness of about 1000 Å, and then a photo and etching process is performed to form the first poly By selectively removing the silicon film, a floating gate pattern is formed in the memory cell region, as shown on the right side of FIG. 4B.

Next, a silicon oxide film of about 50 Å is grown on the entire surface of the substrate by a thermal oxidation process, and a silicon nitride film of about 120 Å is deposited on the silicon oxide film by LPCVD on the silicon oxide film. By forming a silicon oxide film of about 50 Å on the silicon nitride film, an ONO film 32 as an interlayer insulating film between the floating gate and the control gate is formed as shown in FIG. 4C.

Referring to FIG. 4D, a photoresist 34 is formed on the field oxide film 24 for isolating the active region from the selective transistor region by photolithography. The photoresist 34 masks the remaining region except the zigzag window region 36, Pattern is formed and the ONO film of the window region 36 is selectively removed by a dry etching process (see FIG. 1).

Then, the photoresist 34 is removed, and a second polysilicon film 38 of about 1000 Å thick and a tungsten silicide film 40 of about 1000 Å thick are successively deposited do. At this time, although the first polysilicon film 28, the ONO film 32, the second polysilicon film 38, and the tungsten silicide film 40 are continuously stacked on the selective transistor, 36, the polysilicon film 28 and the second polysilicon film 38 / the tungsten silicide film 40 are brought into contact with one field region periodically to have one gate electrically, The effect of reducing the resistance of the array as a whole is obtained.

Thereafter, a photolithography process is performed to form a photoresist pattern for masking a region where a gate is to be formed in the cell array region, and then the tungsten silicide film, the second polysilicon film, the ONO film, and the first By sequentially removing the polysilicon film, gates of the select transistor and the memory cell are formed in the cell array. At this time, if the area where the ONO film is etched is exposed without being masked by misalignment, the tungsten silicide film, the second polysilicon film, the first polysilicon film, and the field oxide film are stacked in that part, But it is not a problem in device isolation. After the ion implantation for forming the source and the drain is performed after the above process, an HTO film of about 1000 ANGSTROM is deposited, a BPSG film of about 6000 ANGSTROM is deposited, and a reflow process is performed to planarize the substrate and form a contact hole for the wiring process. After the above process, a titanium film having a thickness of about 300 Å and a titanium nitride film having a thickness of about 400 Å are deposited as a barrier metal, an annealing process is performed in a diffusion furnace, an aluminum film having a thickness of about 6000 Å is deposited, and a titanium nitride film having a thickness of about 250 Å is deposited thereon Next, a photolithography process is performed to form a metal wiring.

5A to 4F show another embodiment of the method for manufacturing a nonvolatile memory device of the present invention, in which a method of etching an ONO film after depositing a second polysilicon film is shown (here, A selection transistor region and a right side represents a memory cell region).

5A to 5C, the process of forming the ONO film 32 proceeds in the same manner as the process shown in FIG.

After forming the structure shown in FIG. 5C, the second polysilicon film 50 is deposited on the entire surface of the substrate to a thickness of about 1000 Å, as shown in FIG. 5D, A photoresist pattern 52 defining a zigzag window 54 is formed on the field oxide film 22 as shown in FIG. 1, and the second polysilicon film of the window region 54 and the ONO The membrane is selectively removed.

Then, the photoresist 52 is removed, and a tungsten silicide film 56 of about 1000 Å in thickness is deposited on the entire surface of the substrate, as shown in FIG. 5F. At this time, the select transistor shows a structure in which the first polysilicon film 28, the ONO film 32, the second polysilicon film 50, and the tungsten silicide film 56 are sequentially stacked, but the ONO film is etched The first polysilicon film 28 and the second polysilicon film 50 / tungsten silicide film 56 are brought into contact with one field oxide film 22 periodically through the gate insulating film 54 to electrically connect one gate . ≪ / RTI >

Next, a photolithography process is performed to form a photoresist pattern for masking a region where a gate is to be formed in the cell array region. Then, the tungsten silicide film, the second polysilicon film, the ONO film, and the tungsten silicide film in the region exposed by the self- 1 polysilicon film is successively removed, gates of the select transistor and the memory cell are formed in the cell array. At this time, if the area where the ONO film is etched is exposed without being masked by misalignment, the tungsten silicide film, the second polysilicon film, the first polysilicon film, and the field oxide film are stacked in that part, But it is not a problem in device isolation. Further, even if the ONO film exposed at the side of the window region is etched by the tungsten silicide film before the deposition, and the residue is left by the tungsten silicide film penetrating into the cavity formed at the side of the window region, Area, the adjacent two selection lines can not be short-circuited.

Thereafter, the source / drain forming process, the interlayer insulating film forming process, and the metal wiring process are performed as in the above-described embodiment to complete the nonvolatile memory device.

Therefore, according to the present invention, when the ONO film is etched, a zigzag-like contact is formed on the upper part of the field region, thereby eliminating the loading effect in the photolithography process, thereby preventing the occurrence of the fitting on the substrate. Also, even when the tungsten silicide film is not completely etched, the short circuit between the select lines can be prevented, and the area added by the butting contact can be reduced.

Claims (10)

A nonvolatile memory device having two or more selection transistors connected in series and a memory cell for storing data, wherein a first conductor, an interlayer insulating film, and a second conductor are provided over the gate insulating film of the two or more selection transistors And a structure in which the first conductor and the second conductor are continuously stacked is formed on the upper part of the element isolation films adjacent to the channel region of the selection transistor so as to be spaced apart from each other by at least one interval between the active region and the element isolation film To the nonvolatile memory element. The nonvolatile memory device according to claim 1, wherein the first conductor is a polysilicon film. The nonvolatile memory device according to claim 1, wherein the second conductor is a polycide film. 4. The nonvolatile memory device according to claim 3, wherein the polycide film comprises a polysilicon film and a tungsten silicide film. The nonvolatile memory device according to claim 1, wherein the interlayer insulating film is an ONO film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. A nonvolatile memory device manufacturing method comprising: a step of depositing a first polysilicon film on a semiconductor substrate on which a field oxide film and a gate oxide film are formed; 1. A method of manufacturing a semiconductor device, the method comprising: selectively removing a polysilicon film to form a window on a field oxide film of a memory cell to be formed; forming an interlayer insulating film on the first polysilicon film; Forming at least one active region and windows separated by a field oxide film on top of the field oxide films in the transistor formation scheduled region, and depositing a second polysilicon film on the surface of the resultant structure. A method of fabricating a memory device. 7. The method of claim 6, further comprising forming a metal silicide film on the second polysilicon film. 8. The method of claim 7, wherein the metal silicide layer is a tungsten silicide layer. A nonvolatile memory device manufacturing method comprising: a step of depositing a first polysilicon film on a semiconductor substrate on which a field oxide film and a gate oxide film are formed; 1. A method of manufacturing a semiconductor device, the method comprising: selectively removing a polysilicon film to form a window on a field oxide film of a memory cell to be formed; forming an interlayer insulating film on the first polysilicon film; Selectively removing the second polysilicon film and the interlayer insulating film to form windows separated into at least one active region and a field oxide film on the field oxide films of the selective transistor formation scheduled region; , And forming a conductive film on the resultant product. Wherein the nonvolatile memory element is formed of a nonvolatile memory element. 10. The method of claim 9, wherein the conductive layer is a tungsten silicide layer.