KR100212135B1 - Test circuit of a dynamic memory device - Google Patents

Abstract

The present invention discloses a task circuit of a dynamic memory device. The circuit includes address scrambling means for scrambled input address signal, data scrambling means for scrambled input data, and memory cell for storing data from the data scrambling means at an address output from the address scrambling means. A dynamic memory device having an array; And address counting means for counting addresses sequentially, address descrambling means for generating the input address signal by descrambling an address from the address counting means, data generating means for generating data, and data generating means. Data descrambling means for descrambling data from and generating the input data, the data descrambling means being enabled by an external enable signal and operating in response to a clock signal, the address counting means, descrambling means, And a beast circuit having a beast control means for controlling the operation of the data generating means and the descrambling means. Thus, the dynamic memory device can be tested effectively.

Description

Test circuit of dynamic memory device

1 is a block diagram of a test circuit of a conventional dynamic memory device.

2 (a) and (b) show examples of a circuit of the address scrambler of the dynamic memory device shown in FIG.

3 shows a circuit of a data scrambler.

4 is a block diagram of a test circuit of the dynamic semiconductor memory device of the present invention.

5 is a block diagram of a test circuit of the dynamic semiconductor memory device of the present invention.

The present invention relates to a test circuit of a dynamic memory device, and more particularly, to a test circuit of a dynamic memory device in consideration of data and address scramble.

According to the development of design technology and manufacturing technology, a system consisting of several chips is composed of one chip, and a memory device is also embedded.

By using the embedded memory device as described above, the timing problem between the dynamic memory device and the circuit connected thereto can be improved and manufacturing cost can be reduced.

However, testing becomes more difficult because the pins of the memory device, which were directly accessible from the outside by using the embedded memory device, are embedded in the circuit. To solve this problem, there is a way to test all pins of the built-in memory device to the external to directly control, such as built-in self-test (BIST) that has a built-in test circuit You can also test using the method.

The Beast circuit is a method of designing an additional circuit that can test itself in a circuit and executing a test using an internally generated test vector without applying a test vector externally. In general, in order to implement a bee circuit, a data generating circuit for generating data to be written to the dynamic memory device or comparing the read data and an address generating circuit for generating an address for accessing the dynamic memory device are used. The data generator and the address generator generate data and addresses necessary for the test of the dynamic memory device under the control of the beast control circuit.

By the way, in the conventional bee circuit, the address and data generation circuit simply used an up / down counter. However, in general, a dynamic memory device is designed to write or read an internal cell by scrambling an externally applied address and data to increase the degree of integration. Therefore, generating the address and data using only the up / down counter does not consider the actual structure of the dynamic memory device, and thus it is impossible to generate an efficient test vector for testing the dynamic memory device. In order to construct an efficient Beast circuit, the dynamic memory device must be tested in consideration of the scrambling information.

Accordingly, an object of the present invention is to provide a test circuit of a dynamic memory device capable of testing the dynamic memory device in consideration of data and address scrambling information of the dynamic memory device.

The test circuit of the dynamic memory device of the present invention for achieving the above object includes an address scrambling means for scrambled input address signal, a data scrambling means for scrambled input data, and an address output from the address scrambling means. A dynamic memory device having a memory cell array for storing data from said data scrambling means; And address counting means for counting addresses sequentially, address descrambling means for generating the input address signal by descrambling an address from the address counting means, data generating means for generating data, and data generation Data descrambling means for descrambling data from the means to generate the input data, and enabled by a beast enable signal from outside and operating in response to a clock signal, the address counting means, And a beast circuit having descrambling means, data generating means, and a beast control means for controlling the operation of the descrambling means.

Before describing the test circuit of the dynamic memory device of the present invention with reference to the accompanying drawings, a test circuit of a conventional vertical memory device will be described.

FIG. 1 is a block diagram of a test circuit of a conventional dynamic memory device, which includes a stage counter 12, a refresh counter 14, a beast control circuit 16, an address generating circuit 18, a data generating circuit 20, Dynamic memory device composed of a beast 10 consisting of a beast error detection circuit 22, a comparison circuit 24, and a multiplexer 26, an address scrambler 32, a data scrambler 34, and a memory cell array 36. It consists of 20.

The stage counter 12 is for counting each step of the test algorithm. Since the general march test algorithm has 6 steps, the stage counter 12 counts from 0 to 5. The refresh counter 14 is a counter for refreshing a memory cell of the dynamic memory device 30 and counts an address during a refresh operation. The address generation circuit 18 is a counter for generating an address of the dynamic memory device 30. If the address of the dynamic memory device is 16 bits, the upper 7 bits are used as the row address and the lower 9 bits are used as the column address. In addition, a total of 9 bits are generated using the upper two bits as dummy bits and the lower 7 ratio as bits generated by the counter. The selection of the row address and column address is controlled by the beast control circuit 16. The data generation circuit 20 generates data to be written to the dynamic memory device or an expected output value to compare the read data. The multiplexer 26 is controlled by the beast control circuit 16 to selectively output the address from the address generating circuit 18 or the data from the data generating circuit 20. It is a circuit for detecting the error which exists in the beist circuit itself with the beeze error detection circuit 20. As shown in FIG. The comparison circuit 24 compares the data from the data generation circuit 20 with the data read from the dynamic memory device 30, or from the signal from the beast control circuit 16 and from the beast error detection circuit 22. Compare the normal signal. Beast control circuit 16 is enabled in response to the enable signal from the outside, operates in response to the clock signal and controls the operation of each block of the beet 10.

2 (a) and (b) show an example of a circuit of the address scrambler 32 of the dynamic memory device 30 shown in FIG. 1, and FIG. 2 (a) shows a 9-bit row address scrambler as an address. XNOR gate 40 for outputting the lowest row address bit signal RA0 by non-exclusively ORing the lower two bits Q0 and Q1 of the 9-bit counter output signal counted by the generation circuit 18, and the lower bit. And an XOR gate 42 for outputting the row address bit signal RQ1 by exclusively logicing the signals Q1 and Q2, and outputting the signals Q2, Q3, Q4, Q5, Q6, Q7 and Q8 of the towner. Are output as row address bit signals RA2, RA3, RA4, RA5, RA6, RA7, RA8. The column address scrambler shown in FIG. 2 (b) converts the output signals Q2, Q3, Q4, Q5, Q6, Q7 and Q8 of the counter into column address bit signals CA1, CA2, CA3, CA4, CA5, CA6, Output to CA7).

The externally visible address of the dynamic memory device is called an external or logical address, and the address used when accessing a real cell is called a physical or topological address. The process of converting a logical address into a topological address is called address scrambling. The output signals Q0 to Q8 counted by an external counter are row address signals, and the row address bit signals RA0 to RA8 are actually address signals of the dynamic memory device. That is, in the case of the row address, the address signal generated by the address generating circuit 18 and the address of the dynamic memory device do not coincide, and in the case of the column address, the coincidence.

FIG. 3 shows a circuit of the data scrambler 34. The data input signal for non-exclusive logic input of the least significant bit of the column address and each bit data EDin from the data generating circuit 20 to the dynamic memory device. It consists of a non-exclusive logic circuit 50 for generating (Din).

The table below shows the state and memory cell type of each data by data scrambling operation.

A bit permutation of data having the same address as seen from the outside of the dynamic memory device is called logical data, and a bit permutation of data having the same address substantially located inside the dynamic memory device is called topology data. This conversion between logical data and topological data is data scrambling. Data scrambling has certain rules according to addresses, and dynamic memory devices have data scrambling with respect to row addresses and data scrambling with column addresses and no scrambling with data paths. As shown in the table, when the value of the row address bit RA0 is 0, the operation to the true cell is performed. When the value of the address bit RA1 is 1, the operation to the completion cell is performed.

Thus, if the external data signal of 8 bits of data is 10101010 and the least significant bit signal RA0 of the row address signal is 0, the data written to the memory cell is 1010101, and if the signal RA0 is 1, it is written to the memory cell. The data is 10101010.

That is, when the data input by the data scrambler is 10101010 and the row address is all 0 by the above-described data and address scrambler operation, the data written to the memory cell will be described using the following table.

As can be seen from the above table, when the externally inputted row address signal is 0, 10101010 data is written to a cell having a cell address of 1, and when 10, data of 1010101 is written to a cell having a cell address of zero. If the address signal is 2,3, 1010101 data is written to the cell with the cell address 2, and if the address signal is 3, the data of 10101010 is written to the cell with the cell address 3.

That is, the test circuit of the conventional dynamic memory device as shown in FIG. 1 generates an efficient test vector because the address and data generating circuits 18 and 20 are composed of only a simple counter without considering the scrambling information of the dynamic memory device. I could not.

4 shows a block diagram of a test circuit of the vertical semiconductor memory device of the present invention, and is composed of an up / down counter 60 and an address descrambler 62. FIG. That is, unlike the conventional circuit composed of only a counter, the address descrambler 62 is further provided.

5 shows a block diagram of a test circuit of the dynamic semiconductor memory device of the present invention, and is composed of a data generating circuit 70 and a data descrambler 72. Unlike the conventional circuit, the data descrambler 72 is further provided.

That is, the test circuit of the dynamic semiconductor memory device of the present invention is configured by connecting a descrambler to the rear ends of the conventional address generator and data generator.

That is, in order to examine the operation of the present invention, when the output signal of the data generation circuit 70 is 10101010 and the row address is all 0, the data written to the memory cell will be described with the following table.

As can be seen from the table, it can be seen that the address input from the outside coincides with the cell address inside the dynamic memory device, and the data input from the outside and the data written in the dynamic memory device match.

Therefore, the test circuit of the dynamic memory device of the present invention of the present invention matches an externally input data and address with addresses and data inside the memory cell of the dynamic memory device to generate an efficient test vector and efficiently test the dynamic memory device. can do.

Claims (1)

Address scrambling means for scrambling the input address signal; Data scrambling means for scrambling input data; And a memory cell array for storing data from the data scrambling means at an address output from the address scrambling means. And address counting means for counting addresses sequentially; Address descrambling means for descrambling an address from the address counting means to generate the input address signal; Data generating means for generating data; Data descrambling means for descrambling data from the data generating means to generate the input data; And a beast control means for enabling operation by an externally enabled bee enable signal and operating in response to a clock signal, for controlling operations of the address counting means, descrambling means, data generating means, and the descrambling means. A test circuit for a longitudinal memory device, characterized in that it comprises a beast circuit.