KR100209831B1 - 처리 시스템 및 그의 동작 방법 - Google Patents

처리 시스템 및 그의 동작 방법 Download PDF

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Publication number
KR100209831B1
KR100209831B1 KR1019950006996A KR19950006996A KR100209831B1 KR 100209831 B1 KR100209831 B1 KR 100209831B1 KR 1019950006996 A KR1019950006996 A KR 1019950006996A KR 19950006996 A KR19950006996 A KR 19950006996A KR 100209831 B1 KR100209831 B1 KR 100209831B1
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KR
South Korea
Prior art keywords
instruction
execution
instructions
circuit
exception
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Expired - Fee Related
Application number
KR1019950006996A
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English (en)
Korean (ko)
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KR950027565A (ko
Inventor
피터 송 승윤
Original Assignee
포만 제프리 엘
인터내셔널 비지네스 머신즈 코포레이션
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Publication of KR950027565A publication Critical patent/KR950027565A/ko
Application granted granted Critical
Publication of KR100209831B1 publication Critical patent/KR100209831B1/ko
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Hardware Redundancy (AREA)
  • Communication Control (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
KR1019950006996A 1994-03-31 1995-03-30 처리 시스템 및 그의 동작 방법 Expired - Fee Related KR100209831B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US22132994A 1994-03-31 1994-03-31
US08/221,329 1994-03-31
US8/221,329 1994-03-31

Publications (2)

Publication Number Publication Date
KR950027565A KR950027565A (ko) 1995-10-18
KR100209831B1 true KR100209831B1 (ko) 1999-07-15

Family

ID=22827362

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950006996A Expired - Fee Related KR100209831B1 (ko) 1994-03-31 1995-03-30 처리 시스템 및 그의 동작 방법

Country Status (15)

Country Link
US (1) US5548738A (enExample)
EP (1) EP0753172B1 (enExample)
JP (1) JP2682812B2 (enExample)
KR (1) KR100209831B1 (enExample)
CN (1) CN1099632C (enExample)
AT (1) ATE181161T1 (enExample)
CA (1) CA2137053A1 (enExample)
CZ (1) CZ9602771A3 (enExample)
DE (1) DE69419036T2 (enExample)
HU (1) HUT75823A (enExample)
MY (1) MY131679A (enExample)
PL (1) PL177404B1 (enExample)
RU (1) RU2142157C1 (enExample)
TW (1) TW260765B (enExample)
WO (1) WO1995027245A1 (enExample)

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US5625835A (en) * 1995-05-10 1997-04-29 International Business Machines Corporation Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor
US5708837A (en) * 1995-06-30 1998-01-13 International Business Machines Corporation Method and apparatus for register renaming in a computer system using a separate arithmetic available queue
US5881306A (en) * 1996-12-17 1999-03-09 International Business Machines Corporation Instruction fetch bandwidth analysis
US5870582A (en) * 1997-03-31 1999-02-09 International Business Machines Corporation Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched
US6098167A (en) * 1997-03-31 2000-08-01 International Business Machines Corporation Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution
US5913048A (en) * 1997-03-31 1999-06-15 International Business Machines Corporation Dispatching instructions in a processor supporting out-of-order execution
US5887161A (en) * 1997-03-31 1999-03-23 International Business Machines Corporation Issuing instructions in a processor supporting out-of-order execution
US5805849A (en) * 1997-03-31 1998-09-08 International Business Machines Corporation Data processing system and method for using an unique identifier to maintain an age relationship between executing instructions
US5875326A (en) * 1997-04-25 1999-02-23 International Business Machines Corporation Data processing system and method for completing out-of-order instructions
US7089404B1 (en) 1999-06-14 2006-08-08 Transmeta Corporation Method and apparatus for enhancing scheduling in an advanced microprocessor
JP3808013B2 (ja) * 2002-07-05 2006-08-09 富士通株式会社 命令実行装置
EP2169538A4 (en) * 2007-06-20 2010-12-01 Fujitsu Ltd INSTRUCTIONS PROCESSOR
EP2169539A4 (en) * 2007-06-20 2010-12-29 Fujitsu Ltd INSTRUCTION MANAGEMENT DEVICE AND METHOD
RU2406127C2 (ru) * 2007-09-18 2010-12-10 Виктор Анатольевич Кущенко Цифровой процессор кущенко в.а.
TWI383364B (zh) * 2008-01-31 2013-01-21 Chimei Innolux Corp 液晶顯示裝置及其驅動模組
GB2514618B (en) * 2013-05-31 2020-11-11 Advanced Risc Mach Ltd Data processing systems
US9710272B2 (en) 2014-04-25 2017-07-18 Avago Technologies General Ip (Singapore) Pte. Ltd. Computer processor with generation renaming
US10209992B2 (en) 2014-04-25 2019-02-19 Avago Technologies International Sales Pte. Limited System and method for branch prediction using two branch history tables and presetting a global branch history register
JP7043985B2 (ja) * 2018-06-13 2022-03-30 富士通株式会社 演算処理装置および演算処理装置の制御方法
CN112506570B (zh) * 2020-12-03 2023-09-08 长沙树根互联技术有限公司 设备指令下发方法、系统和服务器
JP2024025407A (ja) * 2022-08-12 2024-02-26 富士通株式会社 演算処理装置および演算処理方法

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US5051940A (en) * 1990-04-04 1991-09-24 International Business Machines Corporation Data dependency collapsing hardware apparatus
US5341482A (en) * 1987-03-20 1994-08-23 Digital Equipment Corporation Method for synchronization of arithmetic exceptions in central processing units having pipelined execution units simultaneously executing instructions
US4879676A (en) * 1988-02-29 1989-11-07 Mips Computer Systems, Inc. Method and apparatus for precise floating point exceptions
JP2858140B2 (ja) * 1988-10-19 1999-02-17 アポロ・コンピューター・インコーポレーテッド パイプラインプロセッサ装置および方法
US5136697A (en) * 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
US5129067A (en) * 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements
US5077692A (en) * 1990-03-05 1991-12-31 Advanced Micro Devices, Inc. Information storage device with batch select capability
US5261066A (en) * 1990-03-27 1993-11-09 Digital Equipment Corporation Data processing system and method with small fully-associative cache and prefetch buffers
IL94115A (en) * 1990-04-18 1996-06-18 Ibm Israel Dynamic process for creating pseudo-random test templates for pompous hardware design violence
US5197135A (en) * 1990-06-26 1993-03-23 International Business Machines Corporation Memory management for scalable compound instruction set machines with in-memory compounding
US5214763A (en) * 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
US5193167A (en) * 1990-06-29 1993-03-09 Digital Equipment Corporation Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system
JPH04172533A (ja) * 1990-11-07 1992-06-19 Toshiba Corp 電子計算機
US5222244A (en) * 1990-12-20 1993-06-22 Intel Corporation Method of modifying a microinstruction with operands specified by an instruction held in an alias register
RU2002298C1 (ru) * 1990-12-28 1993-10-30 Институт точной механики и вычислительной техники им.С.А.Лебедева РАН Устройство дл выполнени подпрограмм
EP0529303A3 (en) * 1991-08-29 1993-09-22 International Business Machines Corporation Checkpoint synchronization with instruction overlap enabled
US5274818A (en) * 1992-02-03 1993-12-28 Thinking Machines Corporation System and method for compiling a fine-grained array based source program onto a course-grained hardware
US5257216A (en) * 1992-06-10 1993-10-26 Intel Corporation Floating point safe instruction recognition apparatus
US5257214A (en) * 1992-06-16 1993-10-26 Hewlett-Packard Company Qualification of register file write enables using self-timed floating point exception flags
US5268855A (en) * 1992-09-14 1993-12-07 Hewlett-Packard Company Common format for encoding both single and double precision floating point numbers
US5450560A (en) * 1992-12-21 1995-09-12 Motorola, Inc. Pointer for use with a buffer and method of operation

Also Published As

Publication number Publication date
CN1114763A (zh) 1996-01-10
HU9602594D0 (en) 1996-11-28
HUT75823A (en) 1997-05-28
DE69419036D1 (de) 1999-07-15
CZ9602771A3 (cs) 2002-06-12
WO1995027245A1 (en) 1995-10-12
PL316532A1 (en) 1997-01-20
KR950027565A (ko) 1995-10-18
JP2682812B2 (ja) 1997-11-26
MY131679A (en) 2007-08-30
EP0753172B1 (en) 1999-06-09
CA2137053A1 (en) 1995-10-01
DE69419036T2 (de) 2000-01-27
ATE181161T1 (de) 1999-06-15
EP0753172A1 (en) 1997-01-15
RU2142157C1 (ru) 1999-11-27
JPH07271584A (ja) 1995-10-20
US5548738A (en) 1996-08-20
TW260765B (enExample) 1995-10-21
CN1099632C (zh) 2003-01-22
PL177404B1 (pl) 1999-11-30

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