KR100208935B1 - Cmpleteness inspection apparatus and method of data when communicating with aal protocol - Google Patents

Abstract

The present invention is to reduce the implementation area in the implementation of the device for the integrity check of data transmitted and received during asynchronous transmission mode adaptation layer (AAL) protocol communication. The apparatus for checking the integrity of data for asynchronous transmission mode adaptation layer (AAL) protocol communication according to the present invention, the transmission buffer and the receiving buffer for the temporary storage of the packet data transmitted and received during the AAL protocol communication, and A CRC calculator for inputting packet data input under control by byte unit and calculating and outputting a CRC according to a pre-programmed expression, and controlling the CRC calculator to control the received packet data and the packet data for transmission. And a central processing unit for reading the CRC calculation value calculated by the logic device after providing the CRC calculator in byte units.

Description

Apparatus and method for data integrity check in asynchronous transmission mode adaptive layer protocol communication

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous transmission mode (ATM) communication system. More particularly, the present invention relates to a CRC calculating device and a method for calculating the integrity of packet data transmitted and received during asynchronous transmission mode adaptation layer (AAL) protocol communication.

In the Broadband Integrated Services Digital Network of Asynchronous Transfer Mode (hereinafter referred to as ATM), data communication is ATM Adaptation Layer (hereinafter referred to as AAL) type 3/4, AAL. A protocol such as Type 5 is used as a layer of subtransmission to provide services such as TCP / IP (Transmission Control Protocol / Internet Protocol), SNMP (SNMP), frame relay, and the like. Here, AAL3 / 4 and AAL5 are protocol data units delivered using CRC (Cyclic Redundancy Check) 10 and CRC32 for integrity checking of higher service data units (hereinafter referred to as SDUs). Unit: (hereinafter referred to as PDU) is checked for errors. The SDU is converted into a PDU, transmitted, and the PDU is restored to the SDU. Examples of commercially available chips that provide such functions include TXC-05501 (SARA-S) and TXC-05601 (SARA-R), which are manufactured and sold by the United States TransSwitch Corporation.

When a circuit is implemented to provide the services using such chips, a memory for controlling the operation state of the chip, a memory for storing the serviced data, and the like are required, and the contents of these memories are processed. An Arbitrator for controlling the memory access between the Central Processing Unit (CPU) and the SARA chips is required. The basic operation of these configurations is that the SDU to be serviced first is given from the CPU to the memory for storing service data (hereinafter referred to as packet memory), and when information about this is written by the CPU to the operation control memory, the data of the packet memory is SARA-S. In operation, the memory for operation is converted into an ATM cell and transmitted. On the contrary, the SARA-R processes an ATM cell including data communication information, restores the original SDU, and stores the same in the packet memory. At this time, information about this is recorded in the control memory, and the contents thereof are notified to the CPU so that the service to the upper layer is performed.

As described above, when implementing the AAL5 function using a commercial chip, a packet memory (Static RAM) and a control memory (Static RAM) are required in addition to the commercial chip, and the control logic and commercial chip for sharing the memory between the commercial chip and the CPU Control logic is needed to control itself. Although this configuration can increase the processing capacity of the actual data, the amount of hardware required for this includes a significant amount of space and cost in hardware since it includes a commercial chip itself, memories, and peripheral logic. Therefore, when a high throughput capacity is not required, there is a waste in terms of cost and area occupied by the circuit.

For example, assuming that there is an upper board for controlling each subscriber module in a system capable of performing ATM cell exchange, and there is a subscriber board controlled by this, a control communication message comes up and down between the upper and lower sides. Since the user ATM cells for the service can be exchanged using the same path as the exchange path, the AAL5 protocol can be used as a method of data communication for these control messages. In this case, each subscriber board has to handle the control messages much slower than the amount of user cell by AAL5 protocol. As a result, despite the small number of ATM cells that require AAL5 protocol processing, the memory, logic, and chipset described above must be used for each subscriber, resulting in high manufacturing cost and component mounting density in the subscriber board.

Accordingly, an object of the present invention is to provide an apparatus and method for easily performing a protocol using only one PLD with a CPU during a low speed AAL5 protocol communication in a communication system using an ATM method.

Another object of the present invention is to provide an apparatus and method for calculating CRC32 check using simple logic in software in a communication system using ATM.

The present invention for achieving these objectives is that when the inter-processor communication (IPC) is made using the AAL5 protocol through the switch (CSA) between the subscriber-side boards such as NIA, D1MA, D3MA, etc. and the NMA controlling them, Instead of implementing the AAL5 protocol using a commercial chipset, most of the protocol processing is done by software, but only CRC32 calculation, which is a part that requires very much operation at CPU operation speed, is implemented using a logic device. It is characterized by the help of the treatment.

An apparatus for checking the integrity of data for AAL protocol communication according to the present invention, the transmission buffer and the receiving buffer for the temporary storage of the packet data transmitted and received during the AAL protocol communication, and the packet data input under a predetermined control byte A CRC calculator for inputting a unit and calculating and outputting a CRC according to a pre-programmed expression, and controlling the CRC calculator and providing packet data received through the reception buffer and packet data for transmission to the CRC calculator in units of bytes. And at least a central processing unit for reading the CRC calculation value calculated by the logic device.

1 is a view showing the configuration of an apparatus for checking the integrity of data in asynchronous transmission mode adaptive layer protocol communication according to the present invention.

2 is a view showing in detail the configuration of the CRC32 calculator shown in FIG.

3 is a view showing a processing flow according to the calculation operation of the CRC32 calculator according to the present invention.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the invention will now be described with reference to the accompanying drawings. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are used for the same components as much as possible even though they are shown in different drawings. In addition, in the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to the intention or custom of the user or chip designer, and the definitions should be made based on the contents throughout the present specification.

Referring to Fig. 1, an apparatus to which the present invention is applied, that is, a communication apparatus for an AAL protocol, reads a transmission buffer 300 for transmitting a low-speed IPC ATM cell, a reception buffer 400 for receiving cells, and reads the cells. A CPU and peripheral circuit 100 for processing or generating an IPC (Inter Processor Communication) cell and writing it into a buffer, and a CRC32 calculator 200 implemented by a conventional programmable logic device (PLD). Here, the reception buffer 400 is an area in which an ATM cell is received and stored as a normal first in first out (FIFO) or memory. The transmission buffer 300 is an area stored before the ATM cell is generated by the CPU and transmitted to the switch. The CPU and its peripheral circuit 100 can typically use anything that can write 32 bits in the data bus size. The non-described CRC32 calculator 200 is made as shown in FIG. 2 to be described later as a characteristic element according to the present invention.

Referring to FIG. 2, the CRC32 calculator 200 according to the present invention includes 32 D flip-flops 220, a plurality of exclusive OR gates 210, input / output buffers 230 and 240 required for connection to a CPU data bus, and a D flip. It is composed of a control logic 250 that controls the operation of the output buffer 230 by supplying the operation clock CLOCK and the preset PRESET signal of the flop 220 and providing the output enable signal Output Enable.

The control logic unit 250 provides a signal for distinguishing between a read signal CRCRD and a write signal CRCWR indicating whether to read or write data from the 100 to the CPU and its peripheral circuits shown in FIG. It generates and outputs the CLOCK, PRESET and Output Enable signals. The generation of this signal uses a method using one of the address addresses provided from the CPU 100. The method of generating these signals is the same as the method in which the CPU accesses the peripheral memory in a conventional CPU circuit such as MC68030 manufactured and sold by Motorola Corporation of the United States. That is, the control logic unit 250 gates the CRCWR signal and the address and outputs the result as CLOCK. And, the control logic unit 250 gates the CRCWR signal and the inverted address and outputs the result as PRESET, and outputs the CRCRD signal as the Output Enable signal. Output

In FIG. 2, the detailed structure of the block 210 that performs the exclusive logic function may be represented by the formula of Table 1 as follows. These equations are preferably implemented through a programmable logic device (PLD), and may be implemented using an exclusive logic gate having multiple inputs.

Output of exclusive logic gate Output of exclusive logic gate D00 C2 ^ D2 ^ D8 D016 C0 ^ C2 ^ C3 ^ D0 ^ D2 ^ D3 ^ C4 ^ D4 ^ D24 D01 C0 ^ C3 ^ D0 ^ D3 ^ D9 D017 C4 ^ C5 ^ D4 ^ D5 ^ C0 ^ C1 ^ C3 ^ D0 ^ D1 ^ D3 ^ D25 D02 C0 ^ C1 ^ D0 ^ D1 ^ C4 ^ D4 ^ D10 D018 C0 ^ C1 ^ C2 ^ D0 ^ D1 ^ D2 ^ C4 ^ C5 ^ C6 ^ D4 ^ D5 ^ D6 ^ D26 D03 C1 ^ C2 ^ D1 ^ D2 ^ C5 ^ D5 ^ D11 D019 C1 ^ C2 ^ C3 ^ D1 ^ D2 ^ D3 ^ C5 ^ C6 ^ C7 ^ D5 ^ D6 ^ D7 ^ D27 D04 C0 ^ C2 ^ C3 ^ D0 ^ D2 ^ D3 ^ C6 ^ D6 ^ D12 D020 C3 ^ D3 ^ C4 ^ C6 ^ C7 ^ D4 ^ D6 ^ D7 ^ D28 D05 C1 ^ C3 ^ D1 ^ D3 ^ C4 ^ C7 ^ D4 ^ D7 ^ D13 D021 C2 ^ D2 ^ C4 ^ C5 ^ C7 ^ D4 ^ D5 ^ D7 ^ D29 D06 C4 ^ C5 ^ D4 ^ D5 ^ D14 D022 C2 ^ C3 ^ D2 ^ D3 ^ C5 ^ C6 ^ D5 ^ D6 ^ D30 D07 C0 ^ D0 ^ C5 ^ C6 ^ D5 ^ D6 ^ D15 D023 C3 ^ D3 ^ C4 ^ C6 ^ C7 ^ D4 ^ D6 ^ D7 ^ D31 D08 C1 ^ D1 ^ C6 ^ C7 ^ D6 ^ D7 ^ D16 D024 C0 ^ C2 ^ D0 ^ D2 ^ C4 ^ C5 ^ C7 ^ D4 ^ D5 ^ D7 D09 C7 ^ D7 ^ D17 D025 C0 ^ C1 ^ C2 ^ C3 ^ D0 ^ D1 ^ D2 ^ D3 ^ C5 ^ C6 ^ D5 ^ D6 D010 C2 ^ D2 ^ D18 D026 C0 ^ C1 ^ C2 ^ C3 ^ D0 ^ D1 ^ D2 ^ D3 ^ C4 ^ C6 ^ C7 ^ D4 ^ D6 ^ D7 D011 C3 ^ D3 ^ D19 D027 C1 ^ C3 ^ D1 ^ D3 ^ C4 ^ C5 ^ C7 ^ D4 ^ D5 ^ D7 D012 C0 ^ D0 ^ C4 ^ D4 ^ D20 D028 C0 ^ D0 ^ C4 ^ C5 ^ C6 ^ D4 ^ D5 ^ D6 D013 C0 ^ C1 ^ DO ^ D1 ^ C5 ^ D5 ^ D21 D029 C0 ^ C1 ^ D0 ^ D1 ^ C5 ^ C6 ^ C7 ^ D5 ^ D6 ^ D7 D014 C1 ^ C2 ^ D1 ^ D2 ^ C6 ^ D6 ^ D22 D030 C0 ^ C1 ^ D0 ^ D1 ^ C6 ^ C7 ^ D6 ^ D7 D015 C2 ^ C3 ^ D2 ^ D3 ^ C7 ^ D7 ^ D23 D031 C1 ^ D1 ^ C7 ^ D7

In Table 1, ^ denotes an exclusive logic gate, for example, a value of D031 means that all of the input signals C1, C7, and feedback signals D1 and D7 are output by performing exclusive logic sum operation.

Referring again to FIG. 2, the input / output relationship for each of the input buffer 240 and the output buffer 230 is given by the equation, and the input / output relationship of the deflip-flop 220 is given by the equation. That is, CO = CD31, C1 = CD30, ....., C7 = CD24 between input and output of input buffer 240, and CD0 = D31, CD1 = D30, .., CD30 = D1, between input and output of output buffer 230. CD31 has a relationship of D0, and has a relationship of D0 = D00, D1 = D01, ....., and D31 = D031 between the inputs and outputs of the flip-flop 220. Here, the input buffer 240 is characterized by consisting of only one byte. In the above description, D00 to D031 are the inputs of the deflip-flop 220, and D0 to D31 are the outputs of the deflip-flop 220 and the input of the output buffer 230. CD0 to CD31 are the outputs of the output buffer 230 and the inputs of the input buffer 240, and C0 to C7 are the outputs of the input buffer 240. The outputs D0 to D31 of the flip-flop 220 and the outputs C0 to C7 of the input buffer 240 are applied to the input of the exclusive logic gate 210.

3 is a flowchart illustrating a process of performing a CRC32 calculation on one packet by the CRC32 calculator 200 according to the present invention.

First, an operation at the time of reception according to the AAL protocol will be described with reference to FIGS. 1 to 3. This receiving operation is performed in the order of steps 301, 302, 303, 305, and 304 in FIG. 3.

In FIG. 1, the cell received in the reception reception buffer 400 is removed by the CPU 100, and the payloads of the cells having the same header are collected and assembled into one packet. At this time, it is necessary to check whether there is a bit error in the assembled packet. For this, the CRC32 calculator 200 is used in the present invention. As in step 301 of FIG. 3, the CRC32 calculator 200 is preset (step 301). At this time, the state of the deflip-flop 220 after presetting has a value of '1'. In order to generate the preset signal, the CPU and the peripheral circuit 100 supply the write signal CRCWR and the available address address. After the preset, the packet data is actually written to the CRC32 calculator 200 by byte (step 302). The operation clock of the flip-flop 220 is also generated in the same manner as the generation of the preset signal. When all received packet data including the received CRC32 value is written to the CRC32 calculator 200, the 32-bit deflip-flop 220 has the CRC32 calculation result. At this time, the CPU 100 can simultaneously read these 32 bits by giving the read signal CRCRD (step 304).

Next, with reference to Figs. 1 and 3, the operation at the time of transmission according to the AAL protocol will be described. This transmission operation is performed in the order of steps 301, 302, 303, and 304 in FIG. 3.

At the time of transmission, padding is performed in accordance with International Telcommunication Union (ITU) Recommendation I.363 to make a given packet a multiple of 48, and the processing is similar to the above procedure. First, the CRC32 calculator 200 is preset (step 301), and the packet data is written to the CRC32 calculator 200 (step 302). At this time, the area in which the CRC32 is to be written should not be written to the CRC32 calculator 200, so that the packet writing is performed by 4 bytes less than the reception time. That is, after performing step 303, step 305 is performed instead of step 305. After writing the packet data, if 4 bytes of the flip-flop 220 are read simultaneously, this value is the CRC32 value to be sent to the last transmitting cell of each packet.

As described above, the present invention can create an environment in which a single PLD can be simply communicated without a separate commercial chip or additional memory for low speed AAL5 protocol communication. Thus, using very little hardware to implement the AAL5 protocol frees up more space for other functions on the board. Therefore, there is an advantage in reducing the cost of implementation than when using a commercial chipset and memory.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.

Claims (3)

An apparatus for checking integrity of data for asynchronous transmission mode adaptation layer (AAL) protocol communication, A transmission buffer and a reception buffer for temporarily storing packet data transmitted and received during the AAL protocol communication; A CRC calculator for inputting packet data input under predetermined control in units of bytes to calculate and output a CRC according to a pre-programmed expression; A central processing unit which controls the CRC calculator and provides packet data received through the reception buffer and packet data for transmission to the CRC calculator in byte units and then reads the CRC calculation value calculated by the logic device; At least comprising a device. The method of claim 1, wherein the CRC calculator, First means for outputting a CRC calculation value by taking a pre-programmed exclusive logical sum operation on the packet data controlled by the central processing unit and inputted in bytes; And a second means for outputting a 32-bit calculated value of the CRC calculated value outputted from the first means. In the method for the integrity check of data for asynchronous transmission mode adaptation layer (AAL) protocol communication, A logic device for calculating a CRC according to a pre-programmed expression is provided. The packet data transmitted and received during the AAL protocol communication is input to the logic device in byte units to calculate a CRC, and then the CRC calculation is performed to read the calculation result. Checking integrity.