KR100208668B1 - Apparatus for minimizing an electric power consuming by using a phased-locked loop in a radio frequency stage of a television set - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-saving television receiver circuit, in particular, a bias current is variable in response to a current control signal, an amplifier 110 for amplifying and outputting a high frequency input signal RF, and a bias current in response to a current control signal. A variable, prescaler 120 for prescaling and outputting the signal provided from the amplifier 110, a programmable divider 130 for dividing the signal provided from the prescaler 120 in response to the division control data; And a register 22 for storing the provided divided control data and providing the stored divided control data to the programmable divider 130 and the upper bits of the divided control data to determine whether the received channel frequency is a high frequency or a low frequency. The discriminating means 23 for discriminating and the image in response to the output signal of the logical sum means 23. It comprises current control means (24) for generating a current control signal.

Therefore, in the present invention, since the bias current of the amplifier and the prescaler can be varied according to the received channel frequency, it is possible to reduce the current consumption when receiving a television broadcast with a low channel frequency.

Description

Power-saving TV receiver circuit

The present invention relates to a power-saving television receiver circuit, and more particularly, to an apparatus for reducing power consumption by using a phase lock loop in a radio terminal.

1 is a circuit block diagram showing a circuit configuration of a television receiver circuit using a conventional phase lock loop. As shown in FIG. 1, the amplifier 11 amplifies the high frequency input signal RF and outputs the amplified input signal. The prescaler 12 outputs a prescaled signal by subtracting the voltage level of the amplified input signal from the amplifier 11 to be suitable for the device connected to the rear end thereof. The programmable divider 13 divides the prescaled signal from the prescaler 12 in response to the divided control signal provided and outputs the divided signal. The crystal oscillator 14 generates and outputs a first clock signal. The reference divider 15 divides the first clock signal from the crystal oscillator 14 as a reference signal and outputs a reference clock signal. In FIG. 1, the phase comparator 16 compares the phase of the first divided signal from the programmable divider 13 with the phase of the reference clock signal from the reference divider 15 and outputs the phase-compared signal. The charge pump 17 amplifies the phase compared signal from the phase comparator 16 to output the current amplified signal. The integrator 18 integrates the current amplified signal from the charge pump 17 to output the integrated signal. The voltage controlled oscillator 19 inputs the integrated signal from the integrator and feeds it back to control the gain of the amplifier 11. In FIG. 1, Vt represents a tuning signal.

The channel frequency in the receiving circuit of a television usually uses a frequency range of 90 to 860 MHz. Thus, the phase lock loop operates in the band of 90 to 860 MHz. Therefore, the amplification unit, the prescaler, and the like, which are implemented in an analog integrated circuit composed of an ECL (Emitter Coupled Logic) device, are fixed to enable high-speed operation at 860 MHz.

Therefore, there is a problem in that unnecessary power is consumed because the bias current value is fixed at the highest frequency even at a low channel frequency.

An object of the present invention is to reduce the power consumption by operating at the appropriate operating speed corresponding to each frequency by varying the bias current of the amplifier and the pre-scaler in response to the reception channel frequency in order to solve the above-mentioned conventional problems There is provided a power saving television receiver circuit.

1 is a circuit block diagram showing a circuit configuration of a television receiver circuit using a conventional phase lock loop.

2 is a circuit block diagram showing a circuit configuration of a power saving television receiver circuit according to an embodiment of the present invention.

FIG. 3 is a circuit diagram showing the configuration of the variable bias current generator of the amplifier and prescaler of FIG.

* Explanation of symbols for main parts of the drawings

11, 110: amplifier 12, 120: prescaler

13, 130: reference divider 14: crystal oscillator

15 reference divider 16 phase comparator

17: charge pump 18: integrator

19: voltage controlled oscillator 21: bus receiver

22: register 23: judgment means

24: current control means Q1 and Q2: first and second transistors

In order to achieve the above object, the circuit of the present invention relates to a power-saving television receiver circuit, and in particular, a bias current is variable in response to a current control signal, and an amplifier 110 for amplifying and outputting a high frequency input signal RF. And a bias current is varied in response to the current control signal, and is provided from the prescaler 120 for prescaling and outputting the signal provided from the amplifier 110 and the prescaler 120 in response to the division control data. A programmable divider 130 for dividing the signal, a register 22 for storing the provided divided control data, and providing the stored divided control data to the programmable divider 130 and receiving a combination of the upper bits of the divided control data. Discriminating means 23 for discriminating whether the channel frequency is a high frequency or a low frequency , In response to the output signal of the OR gate means (23) characterized by comprising a current control means 24 for generating the current control signal.

Therefore, in the present invention, since the bias currents of the amplifier and the prescaler can be varied according to the received channel frequency, it is possible to reduce the current consumption in the television broadcasting reception circuit having a low channel frequency.

Hereinafter, a configuration and an operation of an apparatus for reducing power consumption of a television radio stage using a phase lock loop according to an embodiment of the present invention will be described with reference to the drawings.

2 is a circuit block diagram showing a circuit configuration of a power saving television receiving circuit according to an embodiment of the present invention. In the circuit of FIG. 2, some parts identical to those of FIG. 1 are omitted, and only the components added or changed and components necessary for description are shown. FIG. 3 is a circuit diagram showing the configuration of the variable bias current generator of the amplifier and prescaler of FIG.

The circuit of FIG. 2 includes an amplifier 110, a prescaler 120, a programmable divider 130, a bus receiver 21, a register 22, a determination means 23, and a current control means 24.

The amplifier 110 varies the bias current in response to the current control signal and amplifies and outputs the high frequency input signal RF. The prescaler 120 varies the bias current in response to the current control signal, and prescales and outputs the signal provided from the amplifier 110. The programmable divider 130 divides the signal provided from the prescaler 120 in response to the division control data.

The bus receiver 21 is connected to a system bus to receive the divided control data provided from a system controller (not shown). The register 22 stores the dispensing control data received through the bus receiver and provides the stored dispensing control data to the programmable divider 130. Dispense control data corresponds to the selected channel. That is, since the frequency used is different according to the low frequency channel and the high frequency channel, the control data is used to divide the received signal with the corresponding division ratio.

The judging means 23 is configured by the OR gate and performs OR on the upper bits of the divided control data provided from the register 22 to determine whether the reception channel frequency is a high frequency or a low frequency.

The current control means provides a current control signal to the amplifier 110 and the prescaler 120 in response to the output signal of the determination means 23.

The amplifier 110 and the prescaler 120 of FIG. 2 employ the variable bias current generation circuit of FIG. The variable bias current generation circuit includes bipolar transistors Q1 and Q2 and resistors R1, R2, R3 and R4. The collector of the bipolar transistor Q1 is connected to the operating voltage VCC and a current control signal is input to the base. The resistors R1 and R3 are connected in series between the operating voltage VCC and the ground, and the emitter of the transistor Q1 is connected through the resistor R2 at a common contact of the two resistors R1 and R3. The collector of transistor Q2 is connected to the operating voltage VCC and to the common contact of resistors R1 and R3 and the emitter is grounded through resistor R4.

Therefore, when the current control signal is in the low state, the transistor Q1 is maintained in the turn off state. Therefore, the base voltage of the transistor Q2 is determined as the voltage divided by the resistor R3 by the operating voltage distribution of the resistors R1 and R3.

When the current control signal is in a high state, the transistor Q1 is maintained in the turned on state. Therefore, the base voltage of the transistor Q2 is determined as the voltage distributed to the resistor R3 by the parallel resistance of the resistors R1 and R2 and the operating voltage distribution of the resistor R3.

In other words, when the transistor Q1 is turned off, the voltage level of the transistor Q2 is applied higher when the transistor Q1 is turned on than the base voltage level of the transistor Q2. Thus, the emitter current value of the transistor Q2 is increased. It becomes bigger.

Therefore, at the high frequency, the current control signal is turned high to turn on the transistor Q1, so that the base current of the transistor Q2 is increased and the emitter current is increased. Thus, the amplifier 110 and the prescaler 120 are increased. Bias current is increased. In other words, at high frequencies, the bias current is increased to increase the operating speed.

On the contrary, at the low frequency, since the current control signal is turned low to turn off the transistor Q1, the base current of the transistor Q2 is reduced and the emitter current is also reduced, thereby the amplifier 110 and the prescaler ( The bias current of 120 is reduced. That is, at a low frequency, the bias current may be reduced to reduce power consumed by the amplifier 110 and the prescaler 120.

As described above, in the present invention, since the bias currents of the existing amplifier and the prescaler are fixed to the operating speed of the highest frequency of the channel frequency, the bias current is set to be larger than necessary at the low frequency and thus the power consumption is high. By setting the bias current variably in response to the frequency generated, the power saving effect can be obtained by reducing unnecessary power consumption.

As mentioned above, although this invention was demonstrated concretely by the above-mentioned preferable embodiment, this invention is not limited to this, A deformation | transformation and improvement are possible within the range of the common knowledge of a person skilled in the art.

Claims (1)

An amplifier 110 for varying a bias current in response to the current control signal and for amplifying and outputting a high frequency input signal RF; A prescaler (120) for varying a bias current in response to the current control signal and prescaling and outputting a signal provided from the amplifier (110); A programmable divider 130 for dividing the signal provided from the prescaler 120 in response to the division control data; A register 22 for storing the provided dispensing control data and providing the stored dispensing control data to the programmable divider 130; Logic sum means 23 for determining whether a received channel frequency is a high frequency or a low frequency by combining the upper bits of the division control data; a current for generating the current control signal in response to an output signal of the logic sum means 23. A power saving television receiver circuit comprising a control means (24).