KR100206188B1 - Negative high voltage generating circuit of nonvolatile semiconductor memory device - Google Patents

Abstract

The present invention relates to a negative high voltage generating circuit of a nonvolatile semiconductor memory device for controlling a negative high voltage required for erasing of a memory cell to be constant, comprising: an oscillator for outputting a driving signal in response to a predetermined control signal; A charge pump unit for outputting a high voltage in response to the drive signal output from the oscillation unit; And a high voltage level control unit for comparing the high voltage outputted from the charge pump unit with a reference voltage and outputting the control signal inputted to the oscillation unit, wherein the high voltage level control unit includes a first input terminal to which the high voltage is applied, The first and second resistors connected in series between the second input terminal to which the reference voltage is applied and the other terminal is connected to the third input terminal to which one end is connected to the connection point between the resistors and to which the first reference voltage is input And a comparator.

Description

The negative high voltage generating circuit of the nonvolatile semiconductor memory device

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a negative high voltage generating circuit of a nonvolatile semiconductor memory device for controlling a constant high negative voltage required for erasing a memory cell.

1 is a cross-sectional view showing a method of erasing a nonvolatile semiconductor memory device.

Referring to FIG. 1, in a nonvolatile semiconductor memory device having a memory cell array composed of a plurality of memory cells, each memory cell has a drain 2 and a source 3 connected to a channel 1 A gate oxide film 7, a floating gate 8, an ONO film 9, and a control gate 10 are sequentially formed on the channel upper part 1. The drain 2, the source 3, and the control gate 10 are connected to power terminals 4, 5, and 6 to which a predetermined voltage is applied from the outside, respectively. The erase mode of operation for discharging the electrons accumulated in the floating gate 7 of the programmed memory cell to the source 3 is as follows. First, a high voltage (Vpp) of about 12 volts, a floating state (high impedance state), and a ground voltage GND are applied to the drain 2, the source 3, and the control gate 10 of the memory cell, respectively And the electrons accumulated in the floating gate 8 are discharged to the source 3 through FN tunneling to perform an erase operation. Second, a source voltage Vs of about 5 volts, a floating state (high impedance state), and a high voltage of about -10 volts are applied to the drain 2, the source 3, and the control gate 10 of the memory cell, (Vpp) is applied to electrons accumulated in the floating gate 8 to be emitted to the source 3 through the FN tunneling, thereby performing an erase operation. In the latter method of the erasing methods, a negative high voltage generating circuit is used to obtain the negative high voltage (Vpp) of -10 volts applied to the control gate 10 have.

2 is a block diagram showing the configuration of a negative high voltage generating circuit of a conventional nonvolatile semiconductor memory device.

The negative high voltage generating circuit shown in FIG. 2 is composed of a high voltage level control unit 20, an oscillation unit 30, and a charge pump unit 40. The oscillation unit 20 drives the charge pump unit 40 by outputting drive signals OPP and nOPP whose phases are inverted from each other in response to a predetermined control signal S_negcomp. The charge pump unit 40 outputs a negative high voltage Vneg applied to the control gate 10 of the memory cell in response to the drive signals OPP and nOPP. The high voltage level control unit 20 for controlling the negative high voltage Vneg to maintain a constant level compares the negative high voltage Vneg with the reference voltage Vref, By outputting the control signal S_negcomp, the negative high voltage Vneg output from the charge pump unit 40 can be kept constant. In this way, the negative high voltage Vneg is kept constant by controlling the oscillation unit 30 by the control signal S_negcomp output from the high voltage level control unit 20, while the control signal S_negcomp ) To the gate of the PMOS transistor MP1, as shown in Fig. Thus, a method of keeping the negative high voltage Vneg output from the charge pump unit 40 constant by the power supply voltage Vcc is also used.

The output voltage Vneg of the charge pump unit 40 shown in FIG. 2 continues to be lowered according to the drive signals OPP and nOPP output from the oscillation unit 30, A high voltage Vneg can be obtained. It is necessary to control so that the negative high voltage Vneg to be applied to the control gate 10 of the memory cell is kept constant during the erase operation. If the negative high voltage Vneg does not reach the desired voltage level, the voltage difference between the control gate 10 and the source 3 of the memory cell becomes insufficient to perform the erase operation. On the other hand, if the negative high voltage Vneg is above a desired voltage level, the memory cell may be damaged due to the negative high voltage Vneg applied to the control gate 10 of the memory cell. Therefore, accurate control of the negative high voltage Vneg applied to the control gate 10 is required. To this end, a high voltage level control unit 20 is required for a negative high voltage generation circuit, and the high voltage level control unit 20 includes capacitors C1 and C2 and a comparator 14.

The high voltage level control unit 20 compares the negative high voltage Vneg output from the charge pump unit 40 with the reference voltage Vref so that a constant negative high voltage Vneg is output from the charge pump unit 40 And outputs a high-level or low-level control signal S_negcomp. Since the reference voltage Vref of the comparator 14 normally has a positive voltage value, a positive voltage is applied to the other terminal of the comparator 14, A changing comparison voltage Ndiv is required, and the coupling of the capacitors C1 and C2 is used as the voltage dividing means. When the negative high voltage Vneg is changed by the high voltage pumping operation of the charge pump unit 40, the comparison voltage Ndiv is calculated from the previously set voltage value (for example, 2 volts) It starts to decrease gradually.

[Equation 1]

In Equation (1), Ndiv0 is an initial value of the comparison voltage (Ndiv), and the C2 capacitor has a very large value as compared with the C1 capacitor.

A comparative voltage Ndiv is generated by the capacitors C1 and C2 connected between the negative high voltage Vneg and the ground voltage Vss output from the charge pump unit 40, The comparison voltage Ndiv is compared with the reference voltage Vref. When the comparison voltage Ndiv of the two input signals Ndiv and Vref input to the comparator 14 is higher than the reference voltage Vref, the comparator 14 outputs a high level control signal S_negcomp To drive the oscillation unit 30 of Fig. The oscillation unit 30 driven by the control signal S_negcomp outputs driving signals OPP and nOPP to cause the charge pump unit 40 to continuously perform the high voltage pumping operation. As a result, the negative high voltage Vneg output from the charge pump unit 40 gradually decreases to a desired voltage level. If the reference voltage Vref is higher than the comparison voltage Ndiv among the two input signals Ndiv and Vref input to the comparator 14, the control signal S_negcomp at the low level is set to Output. Accordingly, since the oscillation unit 30 is disabled and the high-voltage pumping operation of the charge pump unit 40 is interrupted, the voltage level is not lowered any more, and a constant high voltage Vneg is maintained.

However, according to the negative high voltage generating circuit of the conventional nonvolatile semiconductor memory device, the capacitors C1 and C2 and the comparator 14 (not shown) are controlled to control the negative high voltage Vneg from the charge pump unit 40 to be kept constant, The high voltage level control unit 20 is composed of a high voltage level control unit 20, The value of the C2 capacitor among the capacitors C1 and C2 needs to be about 30 pF so that the comparison voltage Ndiv for the negative high voltage Vneg change is not greatly coupled. When the capacitor is formed on the actual layout, the area occupied by the capacitor C2 can be obtained by the following equation (2).

&Quot; (2) "

According to Equation (2), since the area occupied by the capacitors C1 and C2 of the high voltage level control unit 20 on the layout is large, there arises a problem that it is difficult to highly integrate the nonvolatile semiconductor memory device.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a nonvolatile semiconductor memory device capable of minimizing a chip area on a layout occupied by a high voltage level control section for controlling a negative high voltage to be kept constant, And a negative high voltage generating circuit.

1 is a sectional view showing a method of erasing a nonvolatile semiconductor memory device;

2 is a block diagram showing the configuration of a negative high voltage generating circuit of a conventional nonvolatile semiconductor memory device;

FIG. 3 is a circuit diagram showing another method of controlling the charge pump unit of FIG. 2;

4 is a block diagram showing the configuration of a negative high voltage generating circuit of a nonvolatile semiconductor memory device according to the present invention;

5 is an operation timing diagram according to the present invention,

Description of the Related Art [0002]

20: high voltage level control unit 30:

40: Charge pump section

According to an aspect of the present invention, there is provided an apparatus including: an oscillation unit for outputting a driving signal in response to a predetermined control signal; A charge pump unit for outputting a high voltage in response to the drive signal output from the oscillation unit; And a high voltage level control unit for comparing the high voltage outputted from the charge pump unit with a reference voltage and outputting the control signal inputted to the oscillation unit, wherein the high voltage level control unit includes a first input terminal to which the high voltage is applied, The first and second resistors connected in series between the second input terminal to which the reference voltage is applied and the other terminal is connected to the third input terminal to which one end is connected to the connection point between the resistors and to which the first reference voltage is input And a comparator.

In a preferred embodiment of this circuit, the driving signals consist of signals whose phases are inverted from each other.

In a preferred embodiment of this circuit, the first resistor and the second resistor are provided such that the second resistor has a larger value than the first resistor so that the comparison voltage is changed in a positive voltage range.

With such a circuit, the high integration level of the nonvolatile semiconductor memory device can be realized by minimizing the chip area occupied by the high voltage level control unit that controls the negative high voltage to be kept constant.

Reference will now be made in detail to the preferred embodiments of the present invention with reference to FIGS. 4 through 5. FIG.

4, the negative high voltage generating circuit of the novel nonvolatile semiconductor memory device of the present invention is realized by minimizing the area occupied by the high voltage level control section 20 so as to realize high integration of the nonvolatile semiconductor memory device Circuit. The comparison voltage Ndiv necessary for the high voltage level control unit 20 for controlling the negative high voltage Vneg output from the charge pump unit 40 to be constant is used by using the capacitors C1 and C2 Respectively. As a result, the chip area occupied by the capacitors C1 and C2 becomes larger, making it difficult to achieve high integration. However, in the case of the present invention, by replacing the capacitors C1 and C2 used as voltage dividing means of the high voltage level controller 20 with the resistors R1 and R2, High integration of the nonvolatile semiconductor memory device can be realized by minimizing the area.

In Figs. 4 to 5, the same reference numerals are used for components having the same functions as those shown in Figs. 1 to 3.

4 is a block diagram showing the configuration of a negative high voltage generating circuit of a nonvolatile semiconductor memory device according to a preferred embodiment of the present invention.

The negative high-voltage generating circuit shown in FIG. 4 includes a high-voltage level control unit 20, an oscillation unit 30, and a charge pump unit 40. The oscillation unit 30 outputs a drive signal S_driv in response to a predetermined control signal S_negcomp and the charge pump unit 40 generates a drive signal S_driv in response to the drive signal S_driv output from the oscillation unit 20, (Vneg). The high voltage level control unit 20 compares the high voltage Vneg output from the charge pump unit 40 with the reference voltage Vref and outputs the control signal S_negcomp input to the oscillation unit 30 do. Here, the drive signal S_driv is composed of signals OPP and nOPP whose phases are inverted from each other so that the charge pump unit 40 operates efficiently. In this way, while the negative high voltage Vneg for the method of controlling the oscillation unit 30 is kept constant by the control signal S_negcomp output from the high voltage level control unit 20, the control signal S_negcomp is maintained, To the gate of the PMOS transistor MP1, as shown in Fig. Thus, a method of keeping the negative high voltage Vneg output from the charge pump unit 40 constant by the power supply voltage Vcc is also used.

The high voltage level control unit 20 includes resistors R1 and R2 and a comparator 14. The resistors R1 and R2 are connected to a first input terminal 12 to which the high voltage Vneg is applied And a second input terminal 16 to which a second reference voltage Vref2 is applied. When the negative high voltage Vneg and the second reference voltage Vref2 are inputted, the comparison voltage Ndiv divided by the resistors R1 and R2 is output through the connection point N1. The comparator 14 has one terminal connected to the connection point N1 between the resistors R1 and R2 and the other terminal connected to the third input terminal 13 to which the first reference voltage Vref1 is input have. That is, when the comparison voltage Ndiv is at a higher level than the first reference voltage Vref1, the comparator 14 outputs a high level control signal S_negcomp. On the other hand, when the comparison voltage Ndiv is lower than the first reference voltage Vref1, the comparator 14 outputs a low level control signal S_negcomp.

The operation will be described based on the operation timing diagram of Fig. 5 according to the preferred embodiment of the present invention.

5, when the comparison voltage Ndiv of the high voltage level controller 20 is higher than the first reference voltage Vref1, a high level control signal S_negcomp is output from the high voltage level controller 20, Is output. Accordingly, the oscillation unit 30 is driven to output the drive signals OPP and nOPP whose phases are inverted from each other to operate the charge pump unit 40. The charge pump unit 20 performs a high voltage pumping operation in response to the drive signals OPP and nOPP so that the negative high voltage Vneg level is continuously lowered. When the comparison voltage Ndiv is lower than the first reference voltage Vref1, the control signal S_negcomp at a low level is output from the high voltage level controller 20. Thus, the oscillation unit 30 is disabled and the negative high voltage Vneg level output from the charge pump unit 40 is prevented from being lowered further. Therefore, the negative high voltage Vneg output from the charge pump unit 40 is constantly maintained by the control signal S_negcomp of the high voltage level control unit 20.

In the present invention, in order to obtain a desired comparison voltage Ndiv internally within the high voltage level controller 20, the resistors R1 and R2 are used instead of the voltage division by the capacitors C1 and C2 used in the conventional high voltage level controller 20. [ , R2) were used. In this case, when the second reference voltage Vref2 input to one end of the resistor is kept constant at about 1.6 volts at the time of voltage distribution, the comparison voltage Ndiv corresponding to the negative high voltage Vneg is expressed by Equation (3) .

&Quot; (3) "

For example, when the second reference voltage Vref2 is about 1.6 volts and the resistor R1 = 15K |, the resistor R2 = 215K | and the negative high voltage Vneg output from the charge pump unit 40 is -10 The voltage Ndiv that is voltage-divided by the resistors R1 and R2 when the voltage is a volt is 0.8 volts by Equation (3). When the negative high voltage Vneg is less than -10 volts, the comparison voltage Ndiv becomes lower than the first reference voltage Vref1 of about 0.8 volts, and the control signal S_negcomp, which is the output of the comparator 14, Level so as to stop the pumping operation of the charge pump unit 40. [0050] In this case, if the resistance used for voltage distribution of the high-voltage level control unit 20 is formed of polysilicon of about 300 단위 per unit area, the chip area occupied by the resistor is expressed by Equation (4).

&Quot; (4) "

The occupied area calculated by the above-mentioned equation (4) ) Is the area of a conventional capacitor ( ), Which is about 300 times smaller than that of the By using the resistors R1 and R2 as the voltage distributing means of the high voltage level control unit 20, it is possible to reduce the chip area occupied by the negative high voltage generating circuit, which keeps the negative high voltage Vneg constant, High integration of the semiconductor memory device can be realized.

As described above, by replacing the capacitor used as the voltage distributing means of the high voltage level control unit for controlling the negative high voltage output from the charge pump unit to be constant, the chip area occupied by the voltage distributing means is minimized High integration of the nonvolatile semiconductor memory device can be realized.

Claims (3)

An oscillation unit 30 for outputting a drive signal S_driv in response to a predetermined control signal S_negcomp; A charge pump unit 40 for outputting a high voltage Vneg in response to the drive signal S_driv output from the oscillation unit 20; And a high voltage level control unit 20 for comparing the high voltage Vneg output from the charge pump unit 40 with a reference voltage Vref and outputting the control signal S_negcomp input to the oscillation unit 30 The high voltage level control unit 20 includes first and second input terminals 12 and 13 connected in series between a first input terminal 12 to which the high voltage Vneg is applied and a second input terminal 16 to which a second reference voltage Vref2 is applied, One terminal is connected to the connection point N1 between the second resistors R1 and R2 and the resistors R1 and R2 and the other terminal is connected to the third input terminal 13 to which the first reference voltage Vref1 is input A negative high voltage generating circuit of the nonvolatile semiconductor memory device constituted by the connected comparator (14). The method according to claim 1, Wherein the drive signal (S_driv) comprises signals (OPP, nOPP) whose phases are inverted from each other. The method according to claim 1, The first resistor Rl and the second resistor R2 may be arranged such that the second resistor R2 is larger than the first resistor R1 so that the comparison voltage Ndiv changes in a positive voltage range, Voltage negative voltage generating circuit of the nonvolatile semiconductor memory device.