KR100205789B1 - Nonvolatile semiconductor memory device - Google Patents

Abstract

The present invention relates to a nonvolatile semiconductor memory device capable of improving read performance by removing a limitation of a column address input during a continuous data read operation. The present invention relates to a plurality of word lines and a plurality of word lines, respectively. A nonvolatile semiconductor memory device for reading data stored in a plurality of memory cells at a time through a plurality of bit lines connected to the memory cells, the nonvolatile semiconductor memory device comprising: a first predetermined number of bit lines of the plurality of bit lines; First and second group page buffers respectively connected to the second and second group of bit lines and for storing read data on the first and second group of bit lines; A column address counter which receives a read enable signal and predetermined column address signals applied from outside during a data read period, and counts the column address signals in response thereto; A column address sensing circuit for sensing the counted column address signals from the column address counter and outputting a column address sensing signal and a column ending signal for activating next page reading; A column decoder which receives column address signals counted from the column address counter and outputs predetermined signals for transmitting data stored in the first and second group page buffers to a data input / output buffer in response thereto; A sequence of receiving a column address detection signal and a column end signal output from the column address detection circuit and a start address signal applied from the outside and outputting a read enable signal for activating the column start signal and the page read in response thereto A read control circuit; A read clock control signal for receiving a read enable signal output from the sequential read control circuit, a predetermined read end signal, and an address latch enable signal for activating page read, and in response to outputting upper and lower buffer control signals and read operation signals; A generating circuit; For receiving the upper and lower buffer control signal and the read operation control signal output from the read clock control signal generation circuit, and in response to the precharge operation of the bit line, the data storage operation and the data transmission operation to the input and output burr A read clock circuit for outputting control signals and the read end signal; A read operation control signal and a column end signal output from the column address sensing circuit and the read clock control circuit are respectively input, and in response thereto, when the start column address exists between '00h-FFh', a state output signal of a second level is output. R / If the start column address exists between '100h-1FFh', data of the page corresponding to the start column address and the next address of the start column address are continuously transferred from the memory cell array to the corresponding page buffer. Status output signal R / of the first level to prevent the page data of the start column address from being output to the outside It consists of a state output control signal generating circuit for outputting the.

Description

A non volatile semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device capable of improving read performance by removing a limitation of a column address input during a continuous data read operation.

EEPROMs tend to be densely integrated, while at the same time their performance and operating speeds are improving. In general, EEPROM uses a floating gate transistor having a floating gate, a control gate, a source, and a drain as a memory cell. The memory cells are arranged in a matrix of rows and columns, control gates of memory cells arranged in the same rows are connected to a plurality of word lines, and drains of cells arranged in the same columns are connected to a plurality of bit lines. have. The memory cells, the plurality of word lines and the plurality of bit lines constitute a memory cell array. In such an EEPROM, data stored in memory cells connected to one selected word line of a plurality of word lines is read out temporarily through the plurality of bit lines in order to improve an operation speed. This read operation is called a page read operation. Read data on the plurality of bit lines is temporarily stored in data latches called page buffers.

In the EEPROM, memory cells having a NAND structure (hereinafter referred to as "strings") have been developed to increase memory capacity. It has a plurality of memory cells connected in series between a string select transistor for selecting such a string and a ground select transistor for selecting a ground. In a read operation in a memory cell array having a plurality of the above strings, since a page read time for reading data of a memory cell selected by an input address after inputting an address takes several μs, the raw data of one of the memory cell arrays (hereinafter, The " page " is simultaneously read (hereinafter referred to as " page read ") and stored in the latch portion by storage means existing in the semiconductor memory device. Thereafter, it should be sequentially read by an external read enable signal which is an external continuous output signal.

On the other hand, when the direct access operation for one page is completed, the data is latched automatically by the page read operation for the next page even if there is no address input of the next page, and then again applied to the external continuous read enable signal. By outputting continuous data (hereinafter, referred to as "sequential read"), the address input operation of each page can be eliminated. However, as described above, during the sequential reading, a page reading time for the next page is required between the direct reading operation for one page and the direct reading for the next page. During this page read time, the external output signal should be kept in the standby state. As a result, the overall data output time improvement effect is limited, and the overall system performance is degraded. An operation timing diagram of a conventional nonvolatile semiconductor memory device for improving this is shown in FIG. 1. As shown in FIG. 1, an input address always receives an address between '00h-FFh' to sequentially and sequentially output data. The description of the operation thereof is described in detail in "Method and Apparatus for Reading in Semiconductor Memory Device, Application No. P95-32483", and thus will be omitted here.

However, the column address that can be input during continuous data output of the conventional nonvolatile semiconductor memory device is limited to between '00h and FFh'. For this reason, when the column address to be read is close to the MSB column address among the selected pages, an unnecessary read operation on the least significant column address (MLB column address) must be preceded by the above limitation factor. As a result, there is a deterioration factor of substantial read performance improvement, and a problem arises in that the nonvolatile semiconductor memory device must be controlled by a command setting different from the normal read performance.

Accordingly, it is an object of the present invention to provide a nonvolatile semiconductor memory device which is proposed to solve the above-mentioned problems and removes the limitation of a column address input during a continuous read operation.

1 is an external timing diagram in a sequential read mode of a nonvolatile semiconductor memory device according to the prior art;

2 is a schematic block diagram of a peripheral circuit for performing a sequential read operation according to the present invention;

3 is a detailed circuit diagram illustrating a memory cell array, a page buffer, a column selection circuit, and a data input / output buffer used in FIG. 2;

4 is a detailed circuit diagram showing a tristate inverter used in FIG.

5 is a schematic circuit diagram of a read clock control circuit for generating various control signals used in FIG.

FIG. 6 is a schematic circuit diagram of a read clock circuit for generating various control signals used in FIG. 2; FIG.

7 is a schematic circuit diagram of a sequential read control circuit for generating various control signals used in FIG.

8 is an external signal timing diagram of a nonvolatile semiconductor memory device according to the present invention;

9 is an operation timing diagram of a nonvolatile semiconductor memory device according to a preferred embodiment of the present invention;

* Explanation of symbols on the main parts of the drawings

1: memory cell array 2: read clock control circuit

3: read clock circuit 4: sequential read control circuit

5: row address counter 6: row predecoder

7: row decoder 8: column address counter

9: column decoder 10: data input / output buffer

11: column address sensing circuit 12: page buffer

13 column selection circuit 14 current supply circuit

15: I / O path section 16: read operation control signal generation circuit

17: read end signal generator circuit 18: buffer control signal generator circuit

40: control signal generation circuit 41: detection and latch control signal generation circuit

42: read control signal generation circuit 99: count over and page read signal generation circuit

100: column address reset signal generating circuit

According to one aspect of the present invention for achieving the above object, a plurality of bits connected to the memory cells and the data stored in a plurality of word lines and a plurality of memory cells connected to the plurality of word lines, respectively A nonvolatile semiconductor memory device for reading out temporarily through lines, the nonvolatile semiconductor memory device comprising: a first predetermined number of bit lines of the plurality of bit lines and a second group of bit lines, respectively; First and second group page buffers for storing read data on the first and second group of bit lines; A column address counter which receives a read enable signal and predetermined column address signals applied from outside during a data read period, and counts the column address signals in response thereto; A column address sensing circuit for sensing the counted column address signals from the column address counter and outputting a column address sensing signal and a column ending signal for activating next page reading; A column decoder which receives column address signals counted from the column address counter and outputs predetermined signals for transmitting data stored in the first and second group page buffers to a data input / output buffer in response thereto; A sequence of receiving a column address detection signal and a column end signal output from the column address detection circuit and a start address signal applied from the outside and outputting a read enable signal for activating the column start signal and the page read in response thereto A read control circuit; A read clock control signal for receiving a read enable signal output from the sequential read control circuit, a predetermined read end signal, and an address latch enable signal for activating page read, and in response to outputting upper and lower buffer control signals and read operation signals; A generating circuit; For receiving the upper and lower buffer control signal and the read operation control signal output from the read clock control signal generation circuit, and in response to the precharge operation of the bit line, the data storage operation and the data transmission operation to the input and output burr A read clock circuit for outputting control signals and the read end signal; A read operation control signal and a column end signal output from the column address sensing circuit and the read clock control circuit are respectively input, and in response thereto, when the start column address exists between '00h-FFh', a state output signal of a second level is output. R / If the start column address exists between '100h-1FFh', data of the page corresponding to the start column address and the next address of the start column address are continuously transferred from the memory cell array to the corresponding page buffer. Status output signal R / of the first level to prevent the page data of the start column address from being output to the outside It includes a state output control signal generation circuit for outputting.

Such an apparatus can read out data of a column address to be read without performing a read operation on an unnecessary column address by removing a restriction on a column address input during a continuous read operation.

Reference to the present invention will be described in detail with reference to FIGS. 2 to 9.

2 is a block diagram showing a configuration of a semiconductor memory device according to a preferred embodiment of the present invention.

In the novel nonvolatile semiconductor memory device of the present invention, referring to FIG. 2, the row address counter circuit 5 is a row address signal from an address buffer, although not shown in the drawing, in a sequential read operation. And the address signal is counted in response to the count stop signal XCNTup from the clock generation circuit. The row predecoder 6 generates a signal for controlling the row decoder 7 in response to the output of the row address counter circuit 5. The column address counter 8 and the sequential read control circuit 4 have an external read enable signal. Output sequential data by The read clock circuit 3 and the read clock control signal generation circuit 2 perform a page read operation, and the data input / output buffer 10 outputs data. The column address detecting circuit 11 detects an output signal of the column address counter 6 and generates a signal for activating page reading. The memory cell array 1 is arranged in a matrix of rows and columns, and controls the row decoder 7 and the page buffer 12 and the memory cell array 1, and the column selection circuit 13 for column selection. Output the signal. The state output control signal generation circuit 20 receives the read operation signal Rop output from the read clock control signal generation circuit 20 and the column end signal Fsay output from the column address detection circuit 11. In response, the status output signal R / indicating that the semiconductor memory device is operating. Outputs

Here, the state output control signal generation circuit 20 receives the read operation control signal Rop and the column end signal Fsay output from the column address detection circuit 11 and the read clock control circuit 2, respectively. When the start column addresses input in response to the two input signals Rop and Fsay exist between '00h and FFh', continuous read operation and data output are performed. On the other hand, if the input start column address exists between '100h-1FFh', data corresponding to the start column address and the next address of the start column address are successively transferred to the corresponding page buffer 12. That is, during the continuous data transfer period regardless of whether the time required to output the data of the start column address is sufficient or insufficient compared to the time required to transfer the data of the next start column address to the page buffer 12. The state output signal R / of the first level for limiting data output to the outside through the state output control signal generation circuit 20 shown in FIG. Outputs

3 is a schematic circuit diagram for performing a data read operation according to the present invention. In the drawing, the memory cell array 1 is composed of two upper and lower sub main cell arrays 1A and 1B. In the present invention, 512 bytes are configured as one page. However, it would be apparent to one skilled in the art that 1024 bytes could be composed of one page. The upper and lower page buffers 12A and 12B are connected to the bit lines BL0 to BL511 in the memory cell array 1, respectively, and have a sense amplifier function for reading data and a function for temporarily storing the read data. In addition, the current supply circuit 14 is connected to one side of the page buffer 12 composed of the upper and lower page buffers 12A and 12B to read the data of the memory cell and to supply the bit lines BL0 to BL511. It is equipped with a current mirror that controls the amount. Upper and lower input / output path units 15A and 15B are connected to output terminals of the page buffer 12 to control external control signals SPB, 1oReadL, , 1oReadH, To determine the data path. The column select circuit 13 is composed of column select transistors T9 connected to the output terminals of the input / output pass sections 15A and 15B to select the bit lines BL0 to BL511. The data input / output buffer 10 is connected to the column pass transistors T9, respectively, and converts and latches external data input through the data input / output terminals I / O into data having a CMOS level. Thereafter, the latched data is provided to the data bus and the data input / output terminals I / O in response to the latch enable signal or the data output enable signal.

The lower sub memory cell array 1A includes 256 NAND cell units. Each NAND cell unit is comprised of 16 memory cells M0-M15 with channels connected in series between the source of the first select transistor ST1 and the drain of the second select transistor ST2. The drain of the first select transistor ST1 of each NAND cell unit is connected to the corresponding bit line BL through a resistance connection. The source of the second select transistor ST2 of each NAND cell unit is connected to a common source line CSL. The control gates of the first selection transistors ST1 arranged in the same row, the control gates of the memory cells M0-M15 and the control gates of the second selection transistors ST2 are the first selection line SSL, the word lines WL0-WL15 and It is connected with the 2nd selection line GSL, respectively. First select lines SSL, second select lines GSL, and word lines WL0 to WL15 are respectively connected to the row decoder 7 illustrated in FIG. 2 in the lower sub memory cell array 1A. In the page buffer 12 connected to the bit lines BL0 to BL511, a bit line control signal BLct1 is applied to the gate of the D-type transistor T1 for preventing high voltage transmission on the bit line BL in the figure. The source of the transistor T1 is connected to the drain of the N-type transistor T2 for setting the precharge level on the bit line BL during a read operation, and a power supply voltage Vcc is applied to the gate of the transistor T2.

The N-type transistor T2 has a source-drain channel connected between one terminal of the transistor T1 and a node N1, and the P-type transistor T3 has a source-drain channel connected between a power supply voltage and a data sensing line S0, and a current supply circuit. A gate is connected to the output terminal of (14). The N-type transistors T4 and T5 have a gate connected to an initialization control signal 1oDCB and a lower isolation control signal 1oSBLL, respectively, and a source-drain channel is connected between the node N1 and the ground power supply Vss and the node N1 and the node N2, respectively. have. Inverters G1, G2, and G3 configured as latches are configured between the node N2 and the node N3. In addition, a source-drain channel is connected in series between the node N3 and the ground voltage Vss of the N-type transistors T6 and T7 having gates respectively connected to the data sensing line S0 and the lower buffer latch signal 1oLatchL. The gate of the N-type transistor T5 functions to separate the nodes N1 and N3 in response to the lower isolation control signal 1oSBLL. The N-type transistors T4 and T5 function to initialize the node N3 to a high level in response to the control signals 1oDCB and 1oSBLL.

The current mirror type current supply circuit 14 is connected to the P-type transistor T3 and precharges the precharge currents of the bit line BL and the data sensing line S0 and data stored in the memory transistors connected to the bit lines. It serves to provide a sense current to sense. The current supply circuit 14 includes the source drain paths of the P-type transistors T11 and T12 connected in parallel with the source drain path of the P-type transistor T10 between the power supply voltage Vcc and the ground voltage Vss, and the N-type transistors T13 and T14. Drain source passages are connected in series. Gates of the P-type transistors T3 and T12 are connected through a line Z0, and a drain source passage of the N-type transistor T15 is connected between the line Z0 and the ground power supply Vss. Gates of the N-type transistor T15 and the P-type transistor T10 are connected to the precharge control signal 1oPRE. The gate and the drain of the P-type transistor T12 are commonly connected, and the reference voltage Vref is connected to the gate of the N-type transistor T13. The sense amplifier activation signal 1oSAE is applied to the gate of the N-type transistor T14. The transistor T14 pulls down the line Z0 to the ground voltage Vss in response to the precharge control signal 1oPRE, whereby the bit line BL is quickly precharged because the P-type transistor T3 is in the on state.

The line Z0 is then at a predetermined voltage level in response to the sense amplifier activation signal 1oSAE, whereby the P-type transistor T3 is turned on small and supplies a small current Isense on the data sense line S0. Data stored in the data latch circuit G3 composed of inverters G1 and G2 is applied to the drain of the column select transistor T9 in the column select circuit 13 through the tristate inverter G4 in response to the read control signal 1oReadL. A drain source passage of the N-type transistor is connected in series between the input / output terminals of the tristate inverter G4, and a gate thereof is connected to the control signal SPB. In the description of the drawings, the page buffer 12, the input / output path unit 15, and the column selection circuit 13 connected to the one bit line BL0 have been described, but the remaining bit lines BL1 to BL511 are constituted by the same circuit. . The upper page buffer 12B and the upper input / output path unit 15B include an N-type transistor T5 in response to the upper isolation control signal 1oSBLH, an N-type transistor T7 in response to the upper buffer latch signal 1oLatchH, and upper read control. And a tristate inverter G4 responsive to the signal 1oReadH.

FIG. 4 is a detailed circuit diagram of the tristate inverter shown in FIG. 3. The tri-state inverter G4 is composed of P-type transistors T16 and 17 and N-type transistors T18 and T19, and complementary read control signals through the gate of the P-type transistor T17 and the gate of the N-type transistor T18. And read control signal 1oRead are connected respectively. Detailed circuit diagrams of the read clock control signal generation circuit 2, the read clock circuit 3, and the sequential read control circuit 4 according to the present invention are as shown in Figs. The read clock control signal generation circuit 2 includes a read operation control signal generation circuit 16 indicating that the page is in operation, a read end signal generation circuit 17 indicating the end of page reading, and the connected page buffer 12. Is composed of a buffer control signal generation circuit 18 for generating signals for controlling < RTI ID = 0.0 > The read clock circuit 3 includes a control signal generation circuit 40, a sensing and latch control signal generation circuit 41, and a read control signal generation circuit 42. The sequential read control circuit 4 is composed of a count-down and page read signal generation circuit 99 and a column address reset signal generation circuit 100. 8 is an external signal timing diagram of the nonvolatile semiconductor memory device according to the present invention, and FIG. 9 is an operation timing diagram of the nonvolatile semiconductor memory device according to the preferred embodiment of the present invention.

Hereinafter, operations will be described with reference to FIGS. 2 to 9 according to the present invention.

As shown in FIG. 8, when a start column address is input from '00h-FFh', it operates in the same manner as in the prior art, but when the start column address is input from '100h-1FFh' as follows: It will work. Regardless of the time taken to output the arbitrarily selected start column address, the state output signal R / of the first level is transmitted through the state output control signal generation circuit 20 shown in FIG. Outputs That is, the time required for outputting the data of the start column address to the outside is independent of the time required for reading the data corresponding to the next address of the start column address to the corresponding page buffer 12. Status output signal R / of first level when present between '100h-1FFh' To limit the data output to the outside. The data corresponding to the start column address and the next address of the start column address are successively transferred to the corresponding page buffer 12. At this time, the state output signal R / of the first level while continuously transferring data corresponding to the two addresses. As a result, data of the start column address is not output to the outside.

An embodiment according to the present invention will be described in detail with reference to the operation timing diagram shown in FIG.

First, the time period between M0 and M1 is a period for inputting a command for a read operation, and the flag signal SGSR indicating the read operation mode from a command register existing in the semiconductor memory device transitions from low level to high level. do. Then, the period between the times M1 and M2 is a section for inputting the column address and the row address. When the last address is input, the address latch enable signal, which is an activation signal of the page read operation for the memory cell. Is toggled for a short period from the high level to the low level, whereby the read operation signal Rop indicating that the page read operation is in progress transitions from the low level to the high level. At this time, if the input column address is 100h-1FFh, the signal Srdh indicating this transitions from the low level to the high level. When the signal Rop, which indicates the page read operation, transitions from the low level to the high level, the status output signal R / indicating that the semiconductor memory device is operating. Transitions from the high level to the low level.

Therefore, the bit line control signal BLctl for keeping the bit lines BL0-BL511 shown in FIG. 3 below the blocking voltage level of the D-type transistor T1 is transitioned from the high level to the low level. The clock signals 1oSBLL, 1oSBLH, and 1oDCB for discharging the bit lines BL0 to BL511 and setting the page buffer 12 shown in FIG. 3 are activated from a low level to a high level for a period of time. Accordingly, all of the bit lines BL0 to BL511 are discharged to the ground level through the N-type transistors T4 and T5 of FIG. 3, and the page buffer 12 connected to each of the bit lines BL0 to BL511 is set. At this time, the lower page buffer 12A connected to the bit lines BL0 to BL255 selected by the address for selecting the lower memory cell array 12A from among the page buffers 12 constituting one page during the page read operation. Upper buffer control signal for controlling activation of upper page buffer 12B connected to bit lines BL256 to BL511 selected by an address for selecting the upper memory cell array 1B. And lower buffer control signal All remain high level. When the discharge of the bit lines and the setting of one of the upper and lower page buffers 12A and 12B are finished, the precharge control signal 1oPRE and the sense amplifier activation signal 1oSAE transition from the low level to the high level.

As a result, the voltage applied to the gate of the P-type transistor T3 connected to the bit lines BL0 to BL511 becomes low, and a large amount of current is applied to the bit lines BL0 to BL511, respectively. Accordingly, the bit lines BL0 to BL511 are precharged to the blocking voltage level of the D-type transistor T1, and the data sensing lines S0 to S511 are at the power supply voltage level. As described above, after sufficient precharging of the bit lines BL0 to BL511 is performed, as illustrated in FIG. 9, the bit line precharge signal 1oPRE transitions from a high level to a low level and becomes inactive. As a result, the gate voltage of the P-type transistor T3 connected to all of the bit lines BL0 to BL511 increases from a low level to a constant voltage level, thereby supplying only the microcurrent isense to the bit lines BL0 to BL511. At this time, the reference voltage Vref applied to the gate of the N-type transistor T13 in the current supply circuit 14 shown in FIG. 3 is always maintained at a constant level. Thus, the bit lines BL0 to BL511 precharged to the blocking voltage level are respectively connected to the bit lines BL0 to BL511 and are selected according to the data of the memory cell selected by the row decoder 7 shown in FIG. 2. If the current drawn to the ground level by the cell is greater than the microcurrent isense introduced into the bit lines BL0-BL511, it is at ground level, and if it is small, it is at the cutoff voltage level and each data sensing line Si (i = 0-511). ) Becomes the power supply voltage or ground level according to the data of the selected memory cell.

When the voltage level of each data sensing line Si is determined according to the data of the selected memory cell, the lower and upper buffer latch signals 1oLatchL and 1oLatchH for storing the read data into the page buffer 12 are activated from low level to high level. do. Then, the page buffer 12 in which the data sensing line SOi is at the power supply voltage level (when the off-cell readout) is turned on by the data of the selected memory cell, since the N-type transistors T6 and T7 are all turned on. The state of the page buffer 12 is reversed. On the other hand, the page buffers 12 having the data sensing line SOi at the ground level (on the cell) have the page buffer 12 because the N-type transistor T7 is turned on, but the NMOS transistor T6 is turned off. The state of the buffer 12 is maintained as it is. When data of the memory cell read in this manner is stored in the page buffer 12, the lower and upper buffer latch signals 1oLatchL, 1oLatchH and sense amplifier activation signals 1oSAE for storing the read data into the page buffer 12. Transitions from the high level to the low level and becomes inactive.

Upper and lower read control signals 1oReadL for activating the tristate inverter G4 as the sense amplifier activation signal 1oSAE transitions from a high level to a low level; , 1oReadH, The driving signal 1oRcyen that activates the signal is activated from the low level to the high level for a certain period. As a result, the upper and lower read control signals 1oReadL, , 1oReadH, Is activated, data output of the page buffer 12 is enabled by an external output signal, and the count signal Gsrst, which indicates that the page read operation to the memory cell has been performed one or more times, transitions from the low level to the high level. Upper buffer control signal that controls the activation of the page buffer 12 connected to the bit line selected by the upper column address signal when the page is read. Transitions from the high level to the low level. Then, the read end signal 1oSfin indicating the end of the page read operation is activated for a short period from the low level to the high level. When the end signal 1oSfin of the page read operation is toggled, the read operation signal Rop indicating the page read operation is transitioned from the high level to the low level, and the signal BLctl for maintaining the bit line level below the blocking voltage level of the depletion transistor T1. This transition from the low level to the high level.

Status output signal R / indicating that the semiconductor memory device is operating Transitions from the low level to the high level, indicating that data output by an external output signal is enabled. In addition, when the read operation signal Rop indicating the page read operation is transitioned from the high level to the low level, the short pulse signal Ropdis is generated. As a result, the signal Srdh indicating that the start column address is 100h-1FFh is transitioned from the high level to the low level. On the other hand, the signal XCNTup, which increases the row address, is toggled once from the low level to the high level for a certain period of time to increase the row address so that the next page n + 1 (where n is a positive integer) is selected. Thereafter, another activation signal 1oRen of the page read is toggled from the low level to the high level so that the signal Rop transitions from the low level to the high level again, and performs the page read operation for the (n + 1) th page. Perform. Signal for controlling the activation of the page buffer 1/2 connected to the bit line selected by the upper column address when performing a page read operation for the (n + 1) th page. Since is low level, the page buffer (1/2 page) connected to the bit line selected by the upper column address is not affected at all by the page read operation for the (n + 1) th page. The read data of the (n + 1) th page is stored only in the page buffer (the other half page) connected to the bit line selected by the lower column address. The operation of storing the data read by the upper and lower column addresses is the same as the description of the operation described in 'Method and Apparatus for Reading Semiconductor Memory, Application No. P95-32483', and thus will be omitted here.

At this time, the status output signal R / indicating that the semiconductor memory device is operating. Is maintained at a high level. On the other hand, while the page read operation is performed on the (n + 1) th page, the status output signal R / indicating that the semiconductor memory device is operating. Is maintained at a high level, indicating that data output by an external data output signal is enabled. Accordingly, the external data output signal The column address is incremented by one to enable continuous and sequential data output. However, when a randomly selected start column address exists between '100h-1FFh', the following operation is performed. Regardless of the time required to output the arbitrarily selected start column address, the time required to output the data of the start column address to the outside is the data corresponding to the next address of the start column address to the page buffer 12 corresponding thereto. Regardless of the time required for reading, the state output signal R / of the first level is provided through the state output control signal generation circuit 20 shown in FIG. To limit the data output to the outside. The data corresponding to the start column address and the next address of the start column address are successively transferred to the corresponding page buffer 12. At this time, the state output signal R / of the first level while transferring data corresponding to two addresses consecutively. As a result, data of the start column address is not output to the outside. Therefore, the restriction of the start column address input by the above operation can be removed and the performance of the read operation can be improved.

As described above, the column address generated during the continuous data read operation by controlling the status output signal according to the input start column address through the state output control signal generation circuit during the page read operation for the next page in the continuous data read operation mode. You can remove the input restriction of. That is, when the input start column address exists between '100h-1FFh', data corresponding to the start column address and the next page of the start column address are successively transferred to a page buffer, and the state output control signal generation circuit during this period. To prevent data output to the outside. As a result, data output for unnecessary column addresses due to the limiting factor of the input address can be prevented, so that the read performance can be improved during the continuous data read operation. Further, the continuous data read operation can be performed by the read command setting rather than by the special command setting, thereby reducing the overhead of the system controlling the semiconductor memory device, thereby improving the performance of the overall memory device.

Claims (1)

Data stored in the plurality of word lines BL0 to BL511 and the plurality of memory lines M0 to M16 respectively connected to the plurality of word lines BL0 to BL511 may be connected to the memory cells M0 to M16. A nonvolatile semiconductor memory device for reading out at one time through a plurality of bit lines BL0 to BL511, A first predetermined number of bit lines BL0-BL255 of the plurality of bit lines BL0-BL511 and the remaining second group of bit lines BL256-BL511, respectively. First and second group page buffers 12A and 12B for storing read data on the second group of bit lines BL0 to BL255 and BL256 to BL511; The read enable signal applied from the outside during the data read period ( A column address counter 8 which receives predetermined column address signals 1oFsay and counts the column address signals 1oFsay in response thereto; A column address sensing circuit which senses the counted column address signals 1oFsay from the column address counter 8 and outputs a column address detection signal Hsay and a column end signal Fsay for activating next page reading. (11); In response to the column address signals 1oFsay counted down from the column address counter 11, the data stored in the first and second group page buffers 12A and 12B are transferred to the data input / output buffer 10. A column decoder 9 for outputting predetermined signals for transmission; The column address detection signal Hsay and the column end signal Fsay output from the column address detection circuit 11 and the start address signal Srdh applied from the outside are received and, in response, the column start signal 1oFsay. And a sequential read control circuit 4 for outputting a read enable signal 1oRen for activating page reads; The read enable signal 1oRen and the predetermined read end signal 1oSfin outputted from the sequential read control circuit 4 and the address latch enable signal for activating page read ( ), And in response to the upper and lower buffer control signal ( , And a read clock control signal generation circuit 2 for outputting a read operation signal Rop; Upper and lower buffer control signals output from the read clock control signal generation circuit 2 ( , And control signals for controlling a precharge operation of the bit line, a data storage operation, and a data transfer operation to the input / output buffer 10 in response to the read operation control signal Rop. A read clock circuit 3 for outputting a signal 1oSfin; The read operation control signal Rop and the column end signal Fsay respectively output from the column address sensing circuit 11 and the read clock control circuit 2 are received, and in response thereto, the start column address is '00h-FFh'. 'Present in the second level status output signal R / If the start column address exists between '100h-1FFh', the page buffer corresponding to the start column address and the page data corresponding to the next address of the start column address are sequentially stored in the memory cell array 1. Status output signal R / of the first level for preventing the page data of the start column address from being output to the outside during the transfer to (12). And a state output control signal generating circuit (20) for outputting the same.