KR100205375B1 - Moving image encoding apparatus - Google Patents

Abstract

The video code and the device are provided for subblock processing.

The video processing encoding apparatus of the prior art always encodes irregular pictures into constant subblocks, thereby causing a problem in that the boundary of an object is not easily reproduced due to large data loss.

The video encoding apparatus includes a DCT unit for DCT input frames, a quantum and transform unit for quantizing and converting DCT data, an inverse quantization transform unit for inverse quantizing and converting quantized data, an IDCT unit for IDCT inversely quantized data, and an IDCT A video encoding apparatus comprising a motion compensator for motion-compensating and feeding back data, comprising: a motion and segmentation information output unit for extracting a motion vector and region segmentation information into an input frame and a frame of a previous image and outputting the motion vector and region segmentation information to the motion compensator; When the subframe is processed by the information of the partition information output unit, the block extension unit expands the subblock size to the DCT processing size and outputs the DCT unit to the DCT unit, and the data decoded by the IDCT unit is expanded to the original image size. Add a block expansion unit that reduces the block output and outputs a block containing high frequency components. Therefore, it is possible to expand accordingly, so the area is subdivided precisely, so that the boundary of the object on the screen can be reproduced accurately.

Description

Video encoding device

The present invention relates to a digital video encoding system, and more particularly, to a video encoding apparatus for subblock processing.

In general, a single image is divided into square areas of a constant size, usually 8x8 pixels, and transformed for each area to obtain image components of various frequencies, ranging from the average value in the area to the image component of the highest frequency of the highest frequency. Decompose

This decomposition process is called DCT (Discrete Cosine Transform). Before transformation, pixel values spread irregularly on the screen tend to be concentrated toward the low frequency term after transformation. can do.

Hereinafter, a video processing encoding apparatus according to the prior art will be described with reference to the accompanying drawings.

1 is a block diagram showing a configuration of a video processing encoding apparatus according to the prior art, in which a DCT 11 for converting input image information in frame units into frequency components and a finite number of output signals of the DCT 11 are shown. A quantization converter 12 approximating a value, a multiplexer 13 for multiplexing and outputting the output signal of the quantization converter 12, and a buffer for buffering and transmitting the output signal of the MUX 13 ( 14) a QSC (Qantization Stepsize Control) unit 15 for controlling the quantization step of the quantization converter 12 according to the state of the buffer 14, and the image data quantized and converted by the quantization converter 12 An inverse quantization transform unit 16 for quantizing and outputting, an inverse discrete cosine transform (IDCT) 17 for inverse DCT of inverse quantized data, and previous block data and an IDCT (17) in case of an inter block; An adder 18 that adds and outputs the signal decoded by MCP which calculates the motion vector and outputs the motion compensation signal based on the frame memory 19 storing the output data of the controller 18, the data output from the frame memory 19 and the current image block data. (Motion Compensation Predictor) 20, the first switch 21 which is turned on in case of an inter-screen block and outputs the output data of the MCP 20 to the adder 18, and the current input image block data in case of an inter-screen block. And the subtractor 22 which outputs the error of the motion compensation signal of the MCP 20 and the intra block or the inter-block according to the error size of the subtractor 22, and outputs it to the DCT 11. It is composed of a second switch (2).

Referring to the operation of the video processing encoding apparatus according to the prior art configured as described above, the MCP 20 compares the block data of each block data of the current image with the block data of the past image output from the frame memory 19, and calculates a motion vector. Perform block motion compensation.

The subtractor 22 calculates an error between the block data of the current image and the motion compensation signal of the MCP 20, and the given block is switched to an inter-screen block or an intra-picture block by switching of the second switch 23 according to the magnitude of this mistake. Is defined.

If the error signal is small, the given block is defined as an inter-screen block, and the DCT 11 is performed with the difference signal from the block most similar to the previous image as the error signal of the given block.

If the error signal is large, the given block is defined as an in-screen block, and the DCT 11 is performed using the signal of the given block.

The quantization conversion unit 12 quantizes the discrete cosine transformed data, and the signal is transmitted through the MUX 13 and the buffer 14 through a transmission channel (TC) and then decoded.

The quantization step size is then determined to prevent overflow or underflow of the buffer 14.

The data quantized by the quantization converter 12 is dequantized by the inverse quantization converter 16 at the same time as it is transmitted. The dequantized data is inverse DCT and decoded by the IDCT 17. The decoded data is stored in the frame memory 19 when the first switch 21 is turned on in the inter-block block and added to the existing block data in the adder 18, and the first switch 21 in the intra-block block. ) Is off and immediately stored in the frame memory 19.

The signal stored in the frame memory 19 is used for the error signal calculation of the subtractor 22 in the next frame encoding after motion compensation in the MCP 20, and used for decoding the next frame block.

The conventional video processing encoding apparatus encodes an irregular picture, that is, a block containing a high frequency component, into a constant 8x8 block, so that data loss is large and a boundary of an object is not easily reproduced.

The present invention has been made to solve the above-mentioned problems of the prior art, and the block size can be encoded in subblock units such as 4x4, 4x8, and 8x4 while using an 8x8 DCT processor. It is an object of the present invention to provide a video encoding apparatus for precisely subdividing.

1 is a block diagram showing a configuration of a video processing encoding apparatus according to the prior art.

2 is a block diagram showing a configuration of a video processing encoding apparatus according to the present invention.

* Explanation of symbols for main parts of the drawings

210, 320: frame memory 220: MAS unit

230: DCT 240: quantization converter

250: MUX 260: Buffer

270: QSC unit 280: inverse quantization conversion unit

290: IDCT 300: block reduction unit

310, 350, 370, 390: switch 320: adder

340: motion compensation unit 360: subtractor

380 block extension

The video encoding apparatus according to the present invention obtains the motion vector and the region division information from the current input image and the previous image, and encodes the subblock by the block extension and the block reduction using an 8 × 8 DCT processor with a pixel size. Has a feature.

Hereinafter, a video encoding apparatus according to the present invention will be described with reference to the accompanying drawings.

2 is a block diagram showing a configuration of a video processing encoding apparatus according to the present invention. The first frame memory 210 stores an original previous image of image information currently input, and the image information and first frame currently input. A motion and segmentation unit 220 for outputting a motion vector M and region segmentation information S to a previous image output from the memory 210, and converting input image information in frame units into frequency components. The DCT 230, a quantization converter 240 for approximating the output signal of the DCT 230 to a finite number of values, and a motion vector and region division information of the MAS unit 220 are inputted to the quantization converter ( MUX (Multiplexer) 250 for multiplexing the output signal of 240, a buffer 260 for buffering and transmitting the output signal of the MUX 250, the state of the buffer 260 and the region division of the MAS unit 220 QSC (Qantiza) for controlling the quantization step of the quantization converter 240 according to the information S a tion stepsize control unit 270, an inverse quantization converter 280 that inversely quantizes and outputs the image data quantized and converted by the quantization converter 240, and an inverse discrete cosine for inverse DCT of the inverse quantized data. A block reduction unit 300 for reducing a block of dequantized data output from the IDCT 290, and an output of the block reduction unit 300 according to the area division information of the MAS unit 220. Alternatively, the first switch 310 for selectively outputting the output of the IDCT 290 and the adder 320 for adding and outputting the previous block data and the selection output signal of the first switch 310 in the case of an inter block. ), A second frame memory 330 storing the output data of the adder 320, a motion vector output from the second frame memory 330, and a motion vector and region division information output from the MAS unit 220. A motion compensator 340 for performing compensation, and a motion compensator in case of an inter-block A second switch 350 for outputting the output data of 340 to the adder 320, and a subtractor for outputting a difference between the current input image block data and the motion compensation signal of the motion compensator 340 in the case of an inter-block. 360 and a third switch 370 for selectively outputting an intra block or an inter-screen block according to the error size of the subtractor 360, and blocks data selected and output by the third switch 370. A fourth block for selectively outputting the output data of the third switch 370 or the output data of the block extension unit 380 according to the block extension unit 380 for expanding and outputting the area division information output from the MAS unit 220; It consists of a switch 390.

The input frame Fn of the video encoding apparatus according to the present invention configured as described above is divided into macroblock (16 × 16) units having brightness information of 16 × 16 pixels.

The first frame memory 210 stores the original previous image, and the MAS unit 220 compares each block data of the current image with block data of the past image output from the first frame memory 210 to determine a motion vector ( M) and the region division signal S are output to the MUX 250 and the motion compensator 340.

Here, the presence or absence of the area division signal for performing block division is determined based on the amount of increase of bits and the amount of decrease of error that occur during division of each block.

In this case, C = Δd-λΔb is used as an evaluation scale, where Δd represents an error amount that decreases when the region is divided, Δb represents an amount of bit that increases during the region division, and λ is a lagrange multiplier (not shown). The multiplication constant of).

In other words, if C is greater than or equal to zero, the given block is partitioned, otherwise the given block is no longer partitioned.

If the blocks have sizes of 4x4 and 4x8, in order to use 8x8 DCT, block expansion is required in the encoding process, and block reduction is required in the decoding process.

Meanwhile, the motion compensator 340 outputs the motion compensation signal to the subtractor 360 using the motion vector and the region division signal of the MAS unit 220.

The subtractor 360 calculates an error between the block data of the current image and the motion compensation signal, and determines an inter-screen / in-frame frame mode for each block according to the magnitude of the error.

That is, when the error signal of the subtractor 360 is small, the third switch 370 defines a given block as an inter-screen block and outputs an error signal of the previous image and the given block.

If the error signal is large, a given block is defined as an in-screen block and a signal of the given block is output.

In this way, the signal output from the third switch 370 is again output from the fourth switch 390 to the DCT 230 according to the area division information of the MAS unit 220 or from the block extension unit 380. It is selected whether to output the block data to the DCT 230.

The block data selected and output according to the region division information by the fourth switch 390 is quantized by the quantization converter 240 after being two-dimensional 8x8 DCT by the DCT 230, and the signal is again quantized by the MUX 250. It is transmitted to the transmission channel (TC) through the buffer 260.

In more detail, when the size of the block output from the third switch 370 is 16 × 16, 8 × 8 DCTs are performed four times, and in the case of a block smaller than 8 × 8, the block expansion unit 380 blocks the block in advance. The expansion is made into 8x8 blocks, and the DCT 230 is performed on the expanded block.

At this time, the quantization step size of the QSC unit 270 is determined to prevent overflow or underflow of the buffer 260 according to the region division information output from the MAS unit 220.

The data quantized by the quantization converter 240 is inversely quantized by the inverse quantization converter 280 as it is transmitted. The inverse quantized data is inversely DCT-decoded by the IDCT 290.

When a block smaller than 8x8 is expanded in the previous block expansion unit 380, the block reduction unit 300 requires a block reduction process for the decoded data of the IDCT 290.

According to the region division information of the MAS unit 220, the first switch 310 selectively outputs the reduced data output from the block reduction unit 300 or the data output from the IDCT 290.

The decoded data selected and output by the first switch 310 is added to the existing block data input by the switching of the second switch 340 in the case of the inter-block block in the adder 320 and thus the second frame memory 330. Is stored in the second frame memory 330.

The signal stored in the second frame memory 330 is used to calculate an error signal of the subtractor 360 during the next frame encoding after the motion compensation unit 340.

In the video encoding apparatus of the present invention, an irregular screen, that is, a block including a high frequency component, is divided into sub-blocks and processed using a DCT processor having a predetermined block size, so that an object boundary of the screen is accurately reproduced.

Claims (2)

A DCT unit for DCT input frames, a quantization transform unit for quantizing and converting DCT data, an inverse quantization transform unit for inverse quantization of quantized data, an IDCT unit for IDCT inverse quantized data, and motion compensation for IDCT data A video encoding apparatus comprising a motion compensator for feeding back a motion and segmentation information output unit for extracting a motion vector and region segmentation information into an input frame and a frame of a previous image and outputting the motion vector and region segmentation information to the motion compensator, and the motion and segmentation information output unit. A block expansion unit for extending the subblock to a DCT processing size and outputting the DCT to the DCT unit when subblock processing the input frame, and outputting the data decoded by the IDCT unit to the original image size when the subblock is an extended subblock And a block reduction unit. The method of claim 1, wherein the region division information of the motion and division information output unit is output based on a difference between an error amount that is reduced during the region division and a bit weight that is weighted during the region division multiplied by an arbitrary multiplication constant. Video encoding device.