KR100204337B1 - Error correction circuit for a/d converter - Google Patents

Abstract

According to the present invention, the error correction circuit of the analog / digital converter can not only correct an offset error generated in a comparison circuit for determining an input voltage level in the analog / digital conversion block but also corrects an amplification gain error in the digital / analog conversion block. This further improves the reliability of the final converted digital data.

Description

Error correction circuit for analog / digital converter

TECHNICAL FIELD The present invention relates to an analog / digital converter, and more particularly, to an analog / digital converter having an error correction circuit.

1 is a block diagram of a conventional analog / digital converter. FIG. 2 is a detailed circuit diagram of the conventional data correction circuit block 50 shown in FIG.

Hereinafter, an operation of an error correction circuit of a conventional analog / digital converter will be described with reference to FIGS. 1 and 2.

In a sample and hold circuit (10) for inputting an analog signal (AIN +, AIN-) provided from the outside, the input is periodically sampled and held to obtain an analog voltage signal having a predetermined level. Output The analog voltage signal is converted into 16 logic signals by the analog / digital converter 30.

Although not specifically illustrated in the drawings, the analog / digital converter 30 is divided by 16 resistors and a series of resistors connected in series to divide the level between the first reference voltage and the second reference voltage at regular intervals. It is composed of 15 comparators that receive and compare the voltage and the voltage input from the sample-hold circuit 10. Accordingly, the analog / digital converter 30 generates 15 bit data that determine the level of the voltage signal input from the sample-hold circuit 10. In addition, according to these 15 bit data, 4-bit digital data of a signal component is generated.

However, these comparators are in the initial state before the voltage signal is applied from the sample-hold circuit 10, and the | 1/2 LSB | It must have a smaller level of input offset voltage. If this input offset voltage is | 1/2 LSB | If larger, digital data containing errors by ± 1 LSB is generated, distorting the original signal.

In order to prevent this, the digital / analog converter 20 receives the 15 bit data from the analog / digital converter 30 and converts the 15 bit data back into an analog signal, thereby sampling the original input signal that was sampled by the sample-hold circuit 10. Compared with, the difference voltage corresponding to the difference between two voltages is obtained and amplified at a predetermined ratio.

The analog / digital converter 40 generates a 5-bit digital signal including a 3-bit correction component and a 2-bit signal component according to the level of the amplified difference voltage.

The error correction circuit 60 increases or decreases 4-bit digital data of the signal component applied from the analog / digital converter 30 by 1 LSB according to the digital data of the correction component applied from the analog / digital converter 40. Correct it.

The 4-bit digital data thus corrected is combined with 2-bit digital data of the signal component applied from the analog / digital converter 40 and output to the outside through the output driver 70 as the final 6-bit digital signal.

However, according to the above-described prior art, since the gain error is not considered when the digital / analog converter 20 amplifies the difference voltage, an incorrect digital signal may be generated from the analog / digital converter 40. In this case, even though digital data of a proper signal component is generated in the analog / digital converter 30, the digital component of the correction component and the signal component generated from the analog / digital converter 40 may contain an error. Final digital data may be generated.

Accordingly, an object of the present invention is to provide an error correction circuit of an analog / digital converter that can increase the reliability of digital data converted from an analog / digital converter by introducing a circuit for correcting a gain error caused by amplification of a differential voltage.

1 is a block diagram of an analog / digital converter according to an embodiment of the prior art;

2 is a detailed circuit diagram of the data correction circuit block shown in FIG. 1;

3 is a block diagram of an analog / digital converter according to an embodiment of the present invention;

4 is a detailed circuit diagram of the data correction circuit block shown in FIG. 3;

5 is a diagram showing output data of each of the first and second flash analog / digital conversion circuits of FIG. 3;

6 is a diagram showing output data of the multiplexer of FIG. 4;

* Explanation of symbols on the main parts of the drawing

120: digital / analog conversion circuit

130: first flash analog / digital conversion circuit

140: second flash analog / digital conversion circuit

160: data correction circuit

170: offset error correction circuit

180: amplification gain error correction circuit

(Configuration)

According to an aspect of the present invention for achieving the above object, in the correction circuit for correcting the offset error of the comparator in the analog / digital conversion block in the two or more flash analog / digital converter, periodical analog signal from the outside A sample-hold circuit for sampling and outputting and storing a voltage signal in a constant level region; First flash analog / digital converting means for generating a first digital signal that determines the level of the voltage signal applied from said sample-hold circuit and a second digital signal of signal components corresponding to said first data signal; Digital / analog conversion means for amplifying a voltage difference between a voltage signal obtained by converting the first digital signal applied from the first flash analog / digital conversion means back into an analog signal and an original voltage signal stored in the sample-hold circuit. and; Second flash analog / digital conversion means for generating a predetermined digital signal having a signal component and a correction component corresponding to the level of the amplified difference voltage from the digital / analog conversion means; Comparison means for comparing a predetermined reference voltage with the amplified difference voltage signal from the digital / analog conversion means to generate bit data of a correction component; Data correction means for generating predetermined digital signals by receiving predetermined digital data from the comparing means and the first and second flash analog / digital conversion means, respectively, increasing and decreasing the data of the signal component according to the data of the correction component. and; And output driving means for outputting the digital signal from the data correction means to the outside.

In this embodiment, the data correction means corrects offset errors for increasing or decreasing the second digital signal from the first flash analog / digital conversion means in accordance with a correction component of the digital data from the second flash analog / digital conversion means. Circuits; And an amplification gain error correction circuit for increasing or decreasing the second digital data corrected from the offset error correction circuit in accordance with the bit data from the comparison means, thereby converting the digital data from the amplification gain error correction circuit to the second flash analog. And a signal component of the digital data from the digital conversion means.

In this embodiment, the comparing means includes buffer means for buffering the amplified difference voltage from the digital / analog conversion means; And a comparator for generating the bit data of the correction component by comparing the difference voltage from the buffer means with the reference voltage.

According to such a circuit, not only the offset error generated in the comparator in the analog / digital conversion block can be corrected, but also the gain error generated in the amplifier in the digital / analog conversion block can be corrected.

(Example)

3 is a block diagram of an analog / digital converter according to an embodiment of the present invention. FIG. 4 is a detailed circuit diagram of the data correction block shown in FIG. 3.

Hereinafter, an operation of an error correction circuit in an analog / digital converter according to an embodiment of the present invention will be described with reference to FIGS. 3 to 4.

The sample-hold circuit 110 outputs a voltage signal of a predetermined level by sampling a predetermined analog signal input from the outside according to a predetermined sampling frequency and stores the voltage signal outputted. The voltage signal from the sample-hold circuit 110 is designed not to exceed the voltage level corresponding to the difference between the predetermined first reference voltage and the second reference voltage.

The flash analog / digital conversion circuit 130 divides the voltage level between the first reference voltage and the second reference voltage into 15 sections to determine which section the level of the voltage signal applied from the sample-hold circuit 110 corresponds to. Generates 15 logical signals that have been determined. These 15 logic signals are converted into 4-bit digital data of the signal component and applied to the data correction circuit 130 again.

On the other hand, the 15 logic signals from the flash analog / digital conversion circuit 130 are applied to the digital / analog conversion circuit 120 to be converted back into analog voltage signals and stored with the original analog signal stored in the sample-hold circuit 110. Are compared. The difference voltages of the two analog voltage signals compared are amplified by eight times and applied to the flash analog / digital conversion circuit 140.

The flash analog / digital conversion circuit 140 receives the differential voltage signal amplified by eight times and generates five bits of digital data composed of two bits of signal components and three bits of correction components corresponding to the level. Here, the amplified difference voltage is designed not to exceed the voltage difference between the first reference voltage and the second reference voltage.

The amplified difference voltage is applied to the comparator 152 through the buffer 151. The comparator 152 compares the predetermined reference voltage with the amplified difference voltage from the buffer 151 to determine whether the level of the amplified difference voltage is higher or lower than the reference voltage to generate one bit data of the correction component.

The offset error correction circuit 170 in the data correction circuit 160 is configured to convert the 4-bit digital data of the signal component applied from the flash analog / digital conversion circuit 130 to the three-bit data applied from the flash analog / digital conversion circuit 140. Increment / decrease by 1LSB according to the correction component digital data. As a result, the offset error generated in the flash analog / digital conversion circuit 130 is corrected.

The amplification gain correction circuit 180 receives the corrected 4-bit digital data of the signal component from the offset error correction circuit 170 and reduces the digital gain from the digital / analog conversion circuit 120 by 1LSB according to the bit data applied from the comparator 152. Correct the gain error generated during the amplification process.

The 4-bit digital data of the signal component thus corrected is combined with the 2-bit signal component digital data applied from the flash analog / digital conversion circuit 140 and applied to the output driver 190. The output driver 190 outputs 6-bit digital data of the signal component whose correction has been completed to the output terminal.

Next, as an example, the operation of the error correction circuit in the analog / digital converter according to the present embodiment will be described. 5 illustrates digital data converted corresponding to the level of the voltage signal input into the analog / digital conversion circuit 130. 6 is a diagram illustrating output data of the multiplexer of FIG. 4. For example, if the level of the input voltage signal is above L2 and below L3, digital data '0010' is generated. FIG. 5 illustrates digital data converted in correspondence to the eight times amplified difference voltage level input into the analog / digital conversion circuit 140.

If the A-level voltage signal from the sample-hold circuit 110 is applied to the flash analog / digital conversion circuit 130, the normal 15-bit logic value corresponding to the L8 level and the 4-bit digital data ' 1000 'is generated. The 15-bit logic value is applied to the digital / analog conversion circuit 120 and converted into an analog voltage signal, which is converted into an analog voltage signal of L8 level. The difference voltage between the voltage at the L8 level and the voltage at the A level corresponds to DAC_1 shown in FIG. 5. This differential voltage DAC_1 is amplified by eight times.

The amplified difference voltage is input to the analog / digital conversion circuit 140 and the buffer 151. When the level of the difference voltage amplified by eight times is normal, the analog / digital conversion circuit 140 generates one of the digital data of the section b shown in FIG. 5. In this case, as shown in FIG. 5, the voltage value obtained by subtracting the reference voltage L8 of the voltage section including the A level from the A level voltage, which is the original input signal, is equal to or greater than 0 and less than 1LSB. Thus, if the level of the amplified difference voltage corresponds to B point, digital data '10101' is generated. Here, the upper 3 bits '101' are correction components indicating normal cases and the lower 2 bits are digital data of the signal component.

Accordingly, the digital data '1000' is output directly from the offset correction circuit 170 and combined with the digital data '01' of the remaining signal components from the analog / digital conversion circuit 140. Thus, the final digital data '100001' is output to the outside through the output driver 190.

However, it is assumed that an input offset voltage higher than 1 / 2LSB is applied to the comparator in the flash analog / digital conversion circuit 130. Then, the voltage signal of the A level input from the sample-hold circuit 110 is determined to be one step higher to the L9 level, and digital data '1001' may be output. At this time, a difference voltage of DAC_2 shown in FIG. 5 is generated and amplified by eight times. In this case, one of the digital data of the section c shown in FIG. 5 is generated when the voltage value obtained by subtracting the level L9 of the analog signal reduced from the A level, which is the original input signal, corresponds to −1 LSB to 0.

If the level of the amplified difference voltage corresponds to C point, the digital data 11001 is generated. Here, the upper three bits '110' are correction components for lowering the digital data '1001' generated by the flash analog / digital conversion circuit 130 by 1LSB, and the lower two bits are digital data of the signal component. Accordingly, the corrected digital data '1000' is output from the offset correction circuit 170 and combined with the 2-bit digital data of the remaining signal components to output the final digital data '100001' to the outside through the output driver 190.

Similarly, suppose that the comparator in flash analog / digital conversion circuit 130 has an input offset voltage lower than -1 / 2LSB. Then, the voltage signal of the A level input from the sample-hold circuit 110 is determined to be one step lower to the L7 level, and digital data '0111' may be output. At this time, a difference voltage of DAC_3 shown in FIG. 5 is generated and amplified by eight times. In this case, one of the digital data of section a shown in FIG. 5 is generated when the voltage value obtained by subtracting the level L7 of the analog signal reduced from the A level, which is the original input signal, corresponds to 1LSB to 2LSB. Here, the upper three bits '011' are correction components for increasing the digital data '0111' generated by the flash analog / digital conversion circuit 130 by 1LSB, and the lower two bits are digital data of the signal component. Accordingly, the corrected digital data '1000' is generated from the offset correction circuit 170 and combined with the remaining two bits of signal components and output to the outside through the output driver 190.

The amplification gain error is caused by being over-amplified in the differential voltage amplification process in the digital / analog converter 120 when proper digital data is generated from the analog / digital conversion circuit 130. This error indicates that the level of the voltage signal from the sample-hold circuit 110 is the reference voltage level of the next higher interval than the reference voltage of the corresponding voltage section set in the analog / digital converter 130 as shown by A-point in FIG. It is generated when the difference voltage is large because it is closer to.

When the difference voltage is large, even if the digital data '1000' is properly generated in the flash analog / digital conversion circuit 130, when the amplification gain ratio in the digital / analog conversion circuit 120 is greater than 8 times, the level of the amplified difference voltage is increased. This may be larger than the D point shown in FIG. D point is the maximum voltage level when the level of the amplified difference voltage is normal. When the amplified differential voltage becomes abnormally large, the analog / digital conversion circuit 140 determines that the differential voltage has increased due to an offset error of less than -1 / 2LSB to an internal comparator, and thus, among the digital data of section a shown in FIG. Raise one. In this case, the digital data '011' of the correction component is generated from the flash analog / digital conversion circuit 140 so that the offset correction circuit 170 converts the signal component digital data '1000' from the flash analog / digital conversion circuit 130 to 1LSB. Increase by. However, if an error is included in the signal component digital data from the flash analog / digital data conversion circuit 160 as described above, an error may enter the upper 4 bits of the 6-bit digital data that is finally output and cause a large error.

Therefore, to correct this again, the comparator 152 generates bit data '1' of the correction component when the amplified difference voltage is larger than the reference voltage of the D point level.

Accordingly, the amplification gain error correction circuit 180 receives high-level bit data from the comparator 152 and downgrades the 4-bit digital data '1001' that is incorrectly corrected by the offset error correction circuit 170 by 1 LSB again. Error due to wrong amplification gain can be compensated for.

According to the present invention, since the offset error generated in the comparator of the first flash analog / digital conversion circuit as well as the amplification gain error in the digital / analog conversion circuit can be corrected, the reliability of the digital data converted from the analog / digital converter can be improved. It can increase.

Claims (3)

A correction circuit for correcting an offset error of a comparator in an analog / digital conversion block in two or more stages of a flash analog / digital converter, A sample-hold circuit 110 for periodically sampling an analog signal from the outside to output and store a voltage signal in a predetermined level region; A first flash analog / digital converting means for generating a first digital signal, the level of the voltage signal applied from the sample-hold circuit 110, and a second digital signal of signal components corresponding to the first data signal; 130); Amplifying a voltage difference between a voltage signal obtained by converting the first digital signal applied from the first flash analog / digital converting means 130 into an analog signal and the original voltage signal stored in the sample-hold circuit 110. Digital / analog conversion means (120); Second flash analog / digital conversion means (140) for generating a predetermined digital signal having a signal component and a correction component corresponding to the level of the amplified difference voltage from the digital / analog conversion means (120); Comparison means (150) for generating bit data of a correction component by comparing a predetermined reference voltage with an amplified difference voltage signal from the digital / analog conversion means (120); Predetermined digital data is received from the comparing means 140 and the first and second flash analog / digital converting means 130 and 140, respectively, to increase or decrease the data of the signal component according to the data of the correction component. Data correction means (160) for generating a signal; Output driving means (190) for outputting the digital signal from said data correction means (160) to the outside. The method of claim 1, The data correction means 160 increases or decreases the second digital signal from the first flash analog / digital conversion means 130 according to the correction component of the digital data from the second flash analog / digital conversion means 140. An offset error correction circuit 170; An amplification gain error correction circuit 180 including an amplification gain error correction circuit 180 for increasing or decreasing the second digital data corrected from the offset error correction circuit 170 in accordance with the bit data from the comparison means 150. Combining the digital data from 170 with a signal component of the digital data from the second flash analog / digital conversion means (140). The method of claim 1, The comparison means (150) comprises buffer means (151) for buffering the amplified difference voltage from the digital / analog conversion means (120); And a comparator (10) for comparing the difference voltage from said buffer means (151) with said reference voltage to generate said bit data of a correction component.

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