KR100200771B1 - Low pass filter - Google Patents

Abstract

A low pass filter using frequency band characteristics of an operational amplifier is disclosed. The low pass filter includes a first power supply terminal, a second power supply terminal, a differential amplifier, a buffer circuit, a first current source, and a capacitor. The differential amplifier has an output terminal and is located between the first power supply terminal and the second power supply terminal. The buffer circuit is located between the first power supply terminal and the second power supply terminal, and an input terminal is connected to the first output terminal of the differential amplifier, and amplifies a signal input to the input terminal and outputs it to the output terminal. The capacitor has a capacitance of several picofarads or less and is connected between the input terminal and the output terminal of the buffer circuit. The first current source is for supplying a constant bias current to the differential amplifier. According to the present invention, it is effective to provide a low pass filter having a desired cutoff frequency, particularly a cutoff frequency suitable for a phase locked loop circuit, while using a capacitor having a capacitance of several picofarads or less capable of on-chip manufacturing.

Description

Low pass filter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low pass filter, and more particularly, to a low pass filter using the structure and frequency band characteristics of an operational amplifier.

Low-pass filters are typically constructed using resistive and capacitance elements. In addition, filters having a high Q point structure are formed by using an operational amplifier.

1 is a circuit diagram of a low pass filter using an operational amplifier in a conventional low pass filter.

Referring to FIG. 1, a low pass filter using a conventional operational amplifier includes resistance elements 10 and 20, capacitors 40 and 50, and a non-inverting amplifier 80.

In the low pass filter of Fig. 1, a non-inverting amplifier 80 is simply used as an amplifier, and the cutoff frequency, which is characteristic of the low pass filter, is represented by the following equations. 20), and capacitors 40, 60,

[Equation 1]

Here, R1, R2, C1, and C2 represent the values of the resistor element 10, the resistor element 20, the capacitor 40, and the capacitor 60, respectively. If the resistance element 10 and the resistance element 2 have the same resistance value, R, and the capacitor 40 and the capacitor 60 have the same capacitance, C, the cutoff frequency is expressed by the following equation. Lose.

[Equation 2]

As such, the cutoff frequency of the conventional low pass filter is determined by the values of the resistance elements and the capacitance elements constituting the low pass filter. For example, in order for the cutoff frequency to have a low value of several hundred hertz (Hz), the values of the resistive elements and the capacitance elements must be quite large.

When a conventional low pass filter is used in a semiconductor device, an area of a layout occupied by a resistor in an on chip process is increased in order to configure resistors to have a high resistance value. In addition, in order to configure a capacitance device having a high capacitance, since a capacitance device value that can be manufactured in an on-chip process is limited, it is inevitably required to mount the capacitance device outside the chip by using an external terminal.

In particular, in a phase locked loop (PLL), in order to input a pulse current obtained from a phase comparator to an input terminal of a voltage controlled oscillator (VCO), an on-chip is used. The low pass filter produced is essential.

Accordingly, an object of the present invention is to construct a low pass filter having a low cutoff frequency, by using the structure and frequency band characteristics of the operational amplifier, the capacitance having a value that can be manufactured on the on-chip, that is below the picofarad There is provided a low pass filter having a low cutoff frequency characteristic even with an element.

1 is a circuit diagram of a conventional low pass filter.

2 is a block diagram of a low pass filter according to a first embodiment of the present invention.

3 is a circuit diagram of a low pass filter according to a first embodiment of the present invention.

4A is an equivalent circuit diagram of FIG. 3.

FIG. 4B is a circuit diagram more briefly illustrating FIG. 4A.

Description of the main symbols in the drawings

VDD, VSS: power terminals, Vin1, Vin2: input terminals,

Vo1, Vout: output terminals, Rs: output impedance of the differential amplifier,

Cgd: gate-drain capacitance, Cgs: gate-source capacitance,

gm: transconductance, Cdb: drain-to-board capacitance,

gd: drain conductance, ro: equivalent impedance.

In order to achieve the above object, the low pass filter according to the present invention is characterized by including a first power supply terminal, a second power supply terminal, a differential amplifier, a buffer circuit, and a capacitor.

The differential amplifier has an output terminal and is located between the first power supply terminal and the second power supply terminal.

The buffer circuit is located between the first power supply terminal and the second power supply terminal, and an input terminal is connected to the first output terminal of the differential amplifier, and amplifies a signal input to the input terminal and outputs it to the output terminal.

The capacitor is connected between the input terminal and the output terminal of the buffer circuit.

Next, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a low pass filter according to an embodiment of the present invention, and FIG. 3 is a detailed circuit diagram thereof.

2 and 3, a low pass filter according to an embodiment of the present invention includes current supply circuits 100 and 200, a differential amplifier 300, a buffer circuit 400, and a capacitor 500.

The current supply circuit 100 is a circuit for supplying a constant current to the differential amplifier 300.

Current supply circuit 100 is configured as PMOS transistors 110, 120, 130 and NMOS transistor 140.

The PMOS transistor 110 has a source connected to the power supply terminal VDD, and a drain and a gate connected to the source of the PMOS transistor 120.

The PMOS transistor 120 has its source connected to the drain and gate of the PMOS transistor 110, and the drain and gate are connected to the drain of the NMOS transistor 130.

The PMOS transistor 130 has a source connected to a power supply terminal VDD, a gate connected to a gate of the PMOS transistor 110, and a drain thereof to supply a constant bias current to the differential amplifier 300. It is connected to (101).

The NMOS transistor 130 has a drain connected to the drain and the gate of the PMOS transistor 120, a source connected to the power supply terminal VSS, and a gate connected to the power supply terminal VDD.

PMOS transistors 110 and 120 and NMOS transistor 140 both operate in the saturation region and have the same drain current. Therefore, the voltage level of each drain of the PMOS transistors 110 and 120 and the NMOS transistor 140 is determined according to the characteristics of each device, that is, the width and length of the devices. Therefore, the drain current of the PMOS transistor 130 gated through the drains of the PMOS transistors 110 is determined according to the width and length of each of the PMOS transistors 110 and 120 and the NMOS transistor 140. . Here, the drain current of the PMOS transistor 130 supplies a constant bias current to the differential amplifier 300.

The differential amplifier 300 includes a first input terminal Vin1, a second input terminal Vin2, a first output terminal Vo1, and a second output terminal Vo2 and have two identical structures. It is configured as amplifiers 320 and 340.

The differential amplifier 320 is configured as PMOS transistors 322 and 324 and a current mirror 326.

The PMOS transistors 322 and 324 are coupled to each other and connected to the drain of the third PMOS transistor 130 of the current supply circuit 100 to receive a constant bias current. The gates of the PMOS transistors 322 and 324 are connected to each of the first input terminal Vin1 and the second input terminal Vin2.

The current mirror 326 has a cascade structure and is connected to the lower ends (drains) of the PMOS transistors 322 and 324.

The differential amplifier 340 may include a first input terminal Vin1, a second input terminal Vin2, a first output terminal Vo1, a second output terminal Vo2, PMOS transistors 342 and 344, and a current mirror ( 346).

The PMOS transistors 342 and 344 are coupled to each other and connected to the drain of the third PMOS transistor 130 of the current supply circuit 100 to receive a constant bias current. The gates of the PMOS transistors 342 and 344 are connected to each of the first input terminal Vin1 and the second input terminal Vin2.

The current mirror 346 has a cascade structure and is connected to lower ends (drains) of the PMOS transistors 342 and 344.

In the differential amplifier 300, the first output terminal Vo1 is connected to the drain of the PMOS transistor 322 of the differential amplifier 320, and the second output terminal Vo2 is connected to the PMOS transistor of the differential amplifier 340. 344 is connected to the drain.

The current supply circuit 200 is a circuit for supplying a constant bias current to the buffer circuit 400.

The current supply circuit 200 is configured as a PMOS transistor 210, an NMOS transistor 220, and a capacitor 230.

The PMOS transistor 210 has a source connected to a power supply terminal VDD, a gate and a drain connected to each other, and an output terminal 202.

The NMOS transistor 220 has a drain connected to the gate of the PMOS transistor 210, a drain connected to the power supply terminal VSS, and a gate connected to the input terminal 201 so that the NMOS transistor 220 may be formed of the differential amplifier 300. 1 Input the signal output from the output terminal Vo1.

The capacitor 230 is connected between the drain of the PMOS transistor 210 and the gate of the NMOS transistor 220.

In the current supply circuit 200, the input terminal 201 receives a signal from the differential amplifier 300 to determine the output impedance of the current supply circuit 200 and the value of the capacitor 230. Within the cutoff frequency range, a drain current determined according to device characteristics of the PMOS transistor 210 and the NMOS transistor 220 is output to the output terminal 202.

The buffer circuit 400 is configured as a PMOS transistor 402, an NMOS transistor 404, and a capacitor 406.

The PMOS transistor 402 has a source connected to a power supply terminal VDDA, a drain connected to an output terminal Vout, and a gate inputs a signal output from the output terminal 202 of the current supply circuit 200. .

The NMOS transistor 404 has a drain connected to the output terminal Vout and a gate connected to the second output terminal Vo2 of the differential amplifier 300.

The capacitor 500 is connected between the drain of the PMOS transistor 402 and the gate of the NMOS transistor 404.

The constant bias currents supplied from the current supply circuits 100 and 200 to the differential amplifier 300 and the buffer circuit 400, respectively, are determined by the characteristics of the elements configuring the current supply circuits 100 and 200. Therefore, the frequency characteristic of the low pass filter according to the exemplary embodiment of FIG. 3 is determined by the differential amplifier 300, the buffer circuit 400, and the capacitor 500.

FIG. 4A is a small signal equivalent circuit of FIG. 3 briefly illustrated to explain the frequency characteristic of FIG. 3. Here, Rs represents the output impedance of the differential amplifier 300. Cgs, Cgd, Cdb, gd, and gm are the gate-source capacitance, gate-drain capacitance, drain-substrate capacitance, drain incremental conductance, and Transconductance is shown respectively. And ro is the equivalent impedance of the PMOS transistor 402 of the buffer circuit 400 operating as a kind of current source and CL is the capacitance of the capacitor 500. 4B is a circuit more briefly illustrating the circuit of FIG. 4A. Where Ci is the input equivalent capacitance given by the Miller Effect, and GL is the equivalent conductance corresponding to the drain incremental conductance of the NMOS transistor 404 and the equivalent impedance ro of the PMOS transistor 402. The input equivalent capacitance Ci and the equivalent conductance GL are given by the following equation.

[Equation 3]

[Equation 4]

Referring to FIG. 4, the frequency response characteristic of FIG. 3 may be represented by a transfer function below.

[Equation 5]

As can be seen from the above equation, in the transfer function of FIG. 3, there are two poles, s1 and s2, each having a negative value, each represented by the equation given below.

[Equation 6]

[Equation 7]

In general, s2 has a much larger value than s1, so the frequency characteristic is given by dominant pole s1. Therefore, the desired frequency characteristic can be obtained by adjusting the value of s1. In other words, by adjusting the value of s1, a low pass filter having a desired cutoff frequency can be configured. The value of s1 is determined by the values of the output impedance (Rs) and the input capacitance (Ci) of the differential amplifier 300, as can be seen in the equation given above, as a result, the output impedance of the differential amplifier 300 ( By adjusting the values of Rs) and input capacitance Ci, a lowpass filter with the desired cutoff frequency can be constructed. The input capacitance Ci is proportional to the capacitance CL of the capacitor 500 as can be seen in the equation given above. The output impedance Rs of the differential amplifier 300 is proportional to the equivalent impedance acting on the differential amplifier 300 by the current supply circuit 100 supplying a constant bias current of the differential amplifier 300. Therefore, while maintaining the capacitance CL of the capacitor 500 at several pico-farads or less, which enables on-chip manufacturing, the low impedance filter having a desired cutoff frequency is formed by increasing the output impedance Rs of the differential amplifier 300. can do.

Thus, using the structure of the operational amplifier and its frequency band characteristics, a cutoff frequency having a desired cutoff frequency, particularly suitable for a phase locked loop circuit, while using a capacitor having a capacitance of several picofarads or less capable of on-chip manufacturing, It is possible to configure a low pass filter having a.

The present invention has the effect of providing a low pass filter having a desired cutoff frequency, in particular a cutoff frequency suitable for a phase locked loop circuit, while using a capacitor having a capacitance of several picofarads or less capable of on-chip fabrication.

Claims (8)

A first power supply terminal; A second power supply terminal; A differential amplifier having an output terminal and positioned between the first power terminal and the second power terminal; A buffer circuit disposed between the first power supply terminal and the second power supply terminal, and having an input terminal connected to an output terminal of the differential amplifier, amplifying an input signal and outputting the amplified signal to an output terminal; A capacitor having a capacitance equal to or less than picofarad connected between an input terminal and an output terminal of the buffer circuit; And Having a first current source for generating a constant current of a degree suitable for the required output impedance and supplying it to the differential amplifier, The required cutoff frequency is determined by the output impedance of the differential amplifier and the capacitance of the capacitor. The method of claim 1, wherein the first current source, A first PMOS transistor having a source coupled to the first power supply terminal and having a drain and a gate connected to each other; A second PMOS transistor having a source connected to the drain of the first PMOS transistor, and a gate and a drain connected to each other; An NMOS transistor having a drain connected to the second PMOS transistor, a source connected to the second power supply terminal, and a gate connected to the first power supply terminal; And A third PMOS transistor having a source connected to the first power supply terminal, a gate connected to a gate of the first PMOS transistor, and a drain connected to supply a constant bias current to the differential amplifier. Low pass filter, characterized in that. The method of claim 1, And a second current source for supplying a constant bias current to the buffer circuit and the capacitor. The method of claim 3, wherein the second current source, A fourth PMOS transistor having a source coupled to the first power supply terminal, a drain and a gate connected to each other, and connected to supply a constant current to the buffer circuit; A first NMOS transistor having a drain connected to the drain of the fourth PMOS transistor, a source connected to the second power supply terminal, and a gate connected to the first output terminal of the differential amplifier part; And And a first capacitor connected between the drain of said fourth PMOS transistor and the gate of said first NMOS transistor. 4. The low pass filter of claim 3, wherein the second current source is configured to supply a very small amount of current to the buffer circuit and the capacitor in order to lower operating characteristics in response to high frequencies. The method of claim 1, wherein in order to generate a bias current corresponding to the required cutoff frequency, ratios of structural sizes of the first to third PMOS transistors and the NMOS transistors constituting the first current source are different from each other. Low pass filter. The method of claim 1, wherein the differential amplifier, A source coupling stage, wherein the source is coupled to each other and composed of PMOS transistors for inputting a first input signal and a second input signal to respective gates; And And two differential amplifiers having a multi-stage current mirror connected to a lower end of the source coupling stage. 2. The low pass filter of claim 1, wherein the capacitance of the capacitor is less than a few picofarad units and is fabricated on chip.