KR100198786B1 - Apparatus for protecting information - Google Patents

Abstract

The present invention relates to an apparatus for information protection in a high-speed information network, by providing an information protection function to the section processing unit in the STM-n physical layer of the high-speed information network to enhance the information protection function of the high-speed information communication network (hacker) The present invention relates to an information protection device in a section processor that can prevent information leakage, information change, and damage caused by a cracker or the like.

Description

Information protection device in section processor

The present invention relates to an information protection device in a section processor capable of real-time processing of an information protection function for high-speed data of a high-speed information communication network by implementing an information protection algorithm in hardware.

At present, the high-speed information communication network under development at home and abroad is urgently developed for the technology of the high-speed information communication network itself, and there is no information protection function on the communication network itself. Accordingly, since 1995, the ATM forum has begun working on standards for information protection in high-speed information networks. This work is not only in its infancy, but it also suggests ways to protect information at higher levels by slower software. However, the information protection method by software has a problem that it is difficult to process the high-speed data of the high-speed information communication network in real time.

Recently, the demand for multimedia for computer communication using ATM (Asynchronous Transfer Mode) technology, which is the core technology of high-speed information communication network, is increasing at home and abroad. However, in recent years, the possibility of threat of various information loss in ATM systems is increasing by hackers and crackers. In particular, information breaches in the high-speed information network by hackers or crackers can access a lot of data in a short time, so information protection in the high-speed information network is more important than any other system.

Conventional information protection techniques for ATM have been carried out using software at the high level of the high-speed information network using a processor or digital signal processor. However, such a prior art uses a general purpose processor or a digital signal processor to perform information protection using software at a higher level of the high speed information network, thereby slowing down the processing speed of the data, thereby real-time processing of the high speed data using the high speed information network. There is a problem that cannot be done.

Accordingly, an object of the present invention is to provide an information protection device in a section processor capable of performing an information protection function at high speed by implementing hardware in which an information protection encoder and a decoder are inserted into a section processor of a high speed information communication network.

In order to achieve the above object, an information protection apparatus in an interval processor according to the present invention includes a transmitting ATM layer processing means for creating and processing a transmitting ATM cell, and an ATM cell for the ATM cell coming to the transmitting ATM layer processing means. Transmission ATM cell processing means for inserting an error control signal capable of compensating for errors, transmission path processing means for inserting various types of information for maintenance of a path by making the ATM cells into one payload, and an STM-n frame Inserting the AU-n pointer generating means into which information for indicating the starting point of the output data of the transmission path processing means is inserted, and the information for maintenance of the interval into the output of the AU-n pointer generating means, Frame scrambling is performed on 2,421n bytes except 9n bytes, the first column of the interval overhead bytes. A transmission section encryption processing means for encrypting 2,424n bytes excluding 6n frame bytes in a 64-bit unit by a block cipher algorithm and adding 6n frame bytes to the front end of the encrypted data to generate 125 sec of frame data; It is characterized in that it comprises a transmission optical processing means for converting the electrical signal of the STM-n class, which is the output of the transmission section encryption processing means into an optical signal (TSTM-n) to transmit through the optical path.

In addition, the receiving optical processing means for converting the STM-n-class optical signal received through the optical path into an electrical signal, except for 6n frame bytes for the STM-n-class electrical signal from the receiving optical processing means Decodes 2,424n bytes in 64-bit units using a block decoding algorithm, performs descrambling for frame moving methods on 2,421n bytes except 9n bytes, which is the first column of the interval overhead bytes, and finally Receiving section decoding processing means for extracting section maintenance information and collecting maintenance information on a track, and analyzing AU-n pointer data among the output data of the receiving section decoding processing means, and having an STM- having a 125 sec period. AU-n pointer processing means for finding a starting point of RVC4-n data among n data, and outputting of the AU-n pointer processing means. Receiving path processing means for extracting the maintenance information of the path from the to perform the maintenance of the receiving path, and processing error control information of the ATM cell from the output of the receiving path processing means to correct the error for one error The ATM cell having two or more errors is composed of a receiving ATM cell processing means for discarding and extracting a correct ATM cell and a receiving ATM layer means for receiving a valid ATM cell from the receiving ATM processing means. It features.

Since the hardware can be implemented simply by inserting the information protection encoder and the decoder in the section processor of the high-speed information communication network, it is not only easy to implement the section processor having the information protection function as one integrated circuit but also to other devices. On the other hand, it is superior in terms of strengthening information protection function, economic efficiency, efficiency, and power consumption reduction in high speed information communication network.

1 is a block diagram of STM-n frame data.

2 is a block diagram of STM-n block data for encryption and decryption.

3 is a block diagram for information protection in the STM-n matching unit.

4 is a detailed configuration diagram for information protection in the section processor.

* Explanation of symbols for main parts of the drawings

1: transmitting ATM layer processing means 2: transmitting ATM cell processing means

3: transmission path processing means 4: AU-n pointer generating means

5: transmission section encryption processing means 6: transmission optical module processing means

7: receiving optical module processing means 8: transmitting section decoding processing means

9: AU-n pointer processing means 10: receiving path processing means

11: receiving ATM cell processing means 12: receiving ATM layer processing means

According to the present invention, information protection is performed for 2,424n bytes except for 6n frame bytes for frame alignment in the first column of the section overhead corresponding to frame synchronization among data of a high-speed information communication network, thereby adding frame synchronization to transmit / receive data. No hardware is required, and information protection is fully performed without adding or losing extra bytes in a frame.

As shown in FIG. 1, the frame interval of 125 μsec processed by the STM-n ATM matching unit is composed of a total of 2,430 n bytes, among which is a section overhead consisting of 72 n bytes and 9 n bytes. Path overhead, an AUG-n pointer consisting of 9n bytes, and an STM-n payload consisting of 2,430n bytes are included. In particular, the first column of the interval overhead is allocated 6n bytes for frame alignment. Where n is 0, 4, 16, 64, ... 4 (m-1), and m is a positive integer.

Since frame synchronization in a high-speed information network is performed using frame bytes of the ATM matching unit, in order to obtain frame synchronization in STM-n units, the frame alignment bytes composed of 6n bytes in the first column of the interval overhead should not be sparked. .

Therefore, in the present invention, as shown in FIG. 2, the block cipher algorithm is applied to each block unit by dividing 64 bits into one block for the remaining bytes of the STM-n data except the frame alignment byte 6n. In other words, if 2,424n bytes except 6n frame bytes of STM-n, except 6n frame bytes, are divided into 64 bits, all are divided into 303n blocks, so the total number of blocks processed for secretion in one frame is 303n blocks. . 3 is a configuration diagram for information protection in the section processor. The transmitting ATM cell processing means (2) creates an ATM cell (TEATM) in which an error control signal capable of compensating for an error of an ATM cell is inserted into an ATM cell (TATM) coming out from the transmitting ATM layer processing means (1), thereby transmitting path. To the processing means (3). The transmission path processing means 3 inserts various types of information for the maintenance of the path, creates a virtual container TVC4-n, and sends it to the AU-n pointer generation means 4. The AU-n pointer generating means 4 sends the data TAUG-n into which the information for indicating the starting point of the virtual container is inserted, to the transmission section encryption processing means 5. The transmission section encryption processing means 5 inserts information for maintenance of the interval into the data TAUG-n coming from the AU-n pointer generation means 4, and inserts 9n bytes, which is the first column of the interval overhead bytes. The frame moving method scrambling is performed on the excluded 2,421n bytes. Then, the 2,424n bytes except the 6n frame bytes are encrypted in a 64-bit unit by the block cipher algorithm, and the 6n frame bytes are encrypted at the front of the encrypted data. In addition, frame data (TESTM-n) of 125 mu sec is generated and sent to the optical module processing means 6 for transmission. The transmitting optical module processing means 6 converts the electrical signal of STM-n into an optical signal TSTM-n and transmits it through the optical path.

On the other hand, the transmitting optical module processing means 7 converts the optical signal RSTM-n of the STM-n received through the optical path into an electrical signal RESTM-n to the receiving section decoding processing means 7. send. The reception interval decoding processing means 7 decodes the received data RESTM-n in 64 bit units by 2,424n bytes except 6n frame bytes by the block decoding algorithm. Then, frame moving picture scrambling is performed on 2,421n bytes except 9n bytes, which is the first column of the section overhead bytes, and finally, various section maintenance information is extracted to collect maintenance information on the track. The AU-n pointer processing means 29 analyzes the AU-n pointer data among the data RAUG-n coming from the receiving section overhead processing means 28, and RVC4-n of the STM-n data having a 125 µsec period. After finding the starting point of the data, the correct RVC4-n data is sent out to the reception path processing means 10. The reception path processing means 10 extracts the maintenance information for the path from the path data RVC4-n and performs maintenance on the reception path. The receiving ATM cell processing means 11 processes the error control information of the ATM cell from the data REATM coming from the receiving path processing means 10, so that an ATM cell having one error performs error correction and two or more errors. The ATM cell with a discarded process sends only the correct ATM cells (RATM) to the receiving ATM layer means 12.

4 is a block diagram of a section processor for information protection. The transmission section overhead processing means 21 inserts information for the maintenance of the section with respect to the data TAUG-n outputted to the AU-n pointer generation means 4, and thus the frame synchronization scrambling means 22 Send the data (TSAUG-n). The scrambling means 22 for the frame moving picture system performs scrambling for the frame moving picture method on all the TSAUG-n data except for the first column of the section overhead bytes, 9n bytes, on the received data TSAUG-n. The scrambled data (TFAUG-n) is encrypted by using a block cipher algorithm for the 2,424n bytes except the 6n frame bytes in the first column of the section overhead in the block cipher 23. (TEAUG-n) is sent to the transmission frame processing means 24. The transmission frame processing means 24 inserts 6n frame bytes into the encrypted 2,424n bytes and sends them to the transmission optical processing means 6.

On the other hand, the receiving frame synchronizing means 25 performs byte alignment and frame synchronization using 6n frame bytes of the electrical data RESTM-n outputted from the receiving optical processing means 7 to perform frame alignment of 125 µsec. Align all the bytes of and frame-synchronize with respect to 125 μsec frame data from the aligned data. The block decoding means 26 uses 64 block decoding algorithms for the 2,424n bytes excluding 6n frame bytes from the data (REAUG-n) of 125 µsec unit in which the frame synchronization output from the receiving frame synchronization means 25 is set. Decode bit by bit. The frame moving picture descrambling means 27 performs a frame moving picture method for 2,421n bytes except for 9n bytes, which is the first column of the section overhead bytes of the data RFAUG-n having a decoded 125 μsec period output from the decoding means. Perform descrambling for The receiving section overhead processing means 28 extracts various overhead data of data having a 125 μsec period output from the frame moving picture descrambling 27 and utilizes it as the maintenance information of the section, and the final data (RAUG -n) is sent to the AU-n pointer processing means 29.

As described above, the present invention provides an information protection function to a section processor of the STM-n ATM matching unit using a block encryption algorithm and a block decoding algorithm in order to effectively perform an information protection function for STM-n-class high-speed data of an ultrahigh-speed information communication network. Strengthened. In addition, since the present invention can easily insert the section processor information protection encoder and decoder of the STM-n-class high-speed information communication network, it is easy to implement the STM-n-class ATM matching unit with enhanced information protection as one integrated circuit. In addition, since STM-n high-speed information network can process information protection in real time, it has the advantage of improving the economics, efficiency and low power characteristics of the product.

Claims (4)

In the STM-n-class ATM matching unit, an error control signal for compensating for an error of an ATM cell to a sending ATM layer processing means for creating and processing a sending ATM cell and an ATM cell coming to the sending ATM layer processing means. Transmitting ATM cell processing means for inserting, transmission path processing means for inserting various types of information for maintenance of a path by making the ATM cells into one payload, and outputting of the transmission path processing means in STM-n frame data AU-n pointer generating means for inserting information for indicating the starting point of data, and information for maintenance of the interval is inserted into the output of the AU-n pointer generating means, and 9n bytes, which is the first column of the interval overhead bytes. Frame scrambling is performed on 2,421n bytes except for the following, and then 2,424n bytes except 6n frame bytes are performed. Transmission section encryption processing means for encrypting the data in 64-bit units by a block encryption algorithm and adding 6n frame bytes to the front end to generate 125 sec frame data, and STM which is an output of the transmission section encryption processing means. and an optical processing means for transmission which converts an electrical signal of an n-class into an optical signal (TSTM-n) and transmits it through an optical path. The transmission section overhead processing means according to claim 1, wherein the section encryption processing means includes: transmission section overhead processing means for inserting information for maintenance of the section with respect to an output of the AU-n pointer generating means; Frame synchronization scrambling means for performing frame moving picture scrambling on all STM-n data except 9n bytes, which is the first column of the section overhead bytes of the output of the above, and section over the output data of the frame moving picture scrambling means. A block cipher means for encrypting 2,424n bytes except for 6n frame bytes in the first column of the head by a block cipher algorithm in 64-bit units, and 6n frame bytes for 2,424n bytes encrypted by the block cipher means. By inserting the optical processing means for transmission Information protection device in section processor to be done. In the STM-n ATM matching unit, receiving optical processing means for converting an STM-n-class optical signal received through an optical path into an electrical signal, and an STM-n-class from the receiving optical processing means. For the electrical signal, 2,424n bytes except 6n frame bytes are decoded in 64-bit units using a block decoding algorithm, and frame moving method is performed for 2,421n bytes except 9n bytes, the first column of the interval overhead byte. Receiving section decoding processing means for performing descrambling, finally extracting various section maintenance information to collect maintenance information for the track, and AU-n pointer data among the output data of the receiving section decoding processing means. An AU-n pointer processing means for analyzing and finding the starting point of the RVC4-n data among the STM-n data having a 125 µsec period, and the A Receiving path processing means for extracting path maintenance information from the output of the Un-pointer processing means and performing maintenance on the receiving path, and processing error control information of an ATM cell from the output of the receiving path processing means. Error correction is performed on the error, and the ATM cell processing means for discarding an ATM cell having two or more errors to extract a correct ATM cell, and a receiving ATM receiving an effective ATM cell from the receiving ATM processing means. An information protection apparatus in an interval processor, characterized in that it comprises hierarchical means. 4. The method of claim 3, wherein the interval decoding processing means performs byte alignment and frame synchronization using 6n frame bytes of electrical data output from the receiving optical module processing means to align all bytes of the frame data of 125 secsec. Receiving frame synchronizing means for frame-synchronizing the frame data of 125 μsec from the aligned data, and 2,424n bytes except 6n frame bytes among the outputs of the receiving frame synchronizing means in 64-bit units by a block decoding algorithm. Descrambling means for frame moving method for 2,421n bytes except 9n bytes which are the first column of the interval overhead bytes of data having a 125μsec period output from the block decoding means; Descrambling Number for Frame Animation It is composed of a receiving section overhead processing means for extracting various overhead data of data having a 125 μsec period outputted from the stage and using it as the maintenance information of the section, and sending the output to the AU-n pointer processing means. Information protection device in the section processor, characterized in that.