KR100195718B1 - A quantizer - Google Patents

Abstract

The present invention relates to a quantizer, the quantizer of the present invention receives an intra-DC-precision value and outputs an intra-DC-multiply value; A quantization scale value generator 72 receiving a quantization scale code value and a quantization scale value and outputting a quantization scale value; A quantization matrix storage unit 74 storing a quantization matrix; A control unit (76) for controlling the quantization matrix storage unit (74) to output a quantization matrix; And an operation unit 78 for quantizing the discrete cosine transform coefficients input according to the intra-DC-multiply value, the quantization scale value, and the quantization matrix, and outputting a quantized value. By efficiently implementing hardware for performing quantization on the input discrete cosine transformed coefficient in the image encoder, the hardware size may be reduced while maintaining the quantization performance.

Description

Quantizer

1 is a block diagram of an image encoder equipped with a transmission coordination and quantization control unit.

2 is a block diagram of a conventional quantizer.

3 is a block diagram of a quantizer according to the present invention.

FIG. 4 is a detailed block diagram of the calculator shown in FIG.

* Explanation of symbols for main parts of the drawings

70: intra-DC-multiply generator 72: quantization scale value generator

74: Quantization Matrix Storage 76: Control

78: calculator 78-1: first complement converter

78-2: Multiplier 78-3: Multiplexer

78-4: divider 78-5: second complementary converter

78-6: rounding

The present invention relates to a quantizer, and more particularly, to a quantizer adapted to approximate a discrete cosine transformed coefficient inputted in an image encoder to a finite number of values.

In general, mode selection and compensation to be moved are performed based on a macro block (MB), but conversion and quantization are performed based on a block of 8 * 8 pixels.

In addition, adaptive field / frame Discrete Cosine Transform (DCT) coding is performed to further increase the compression rate by using the statistical characteristics of the parallel-scanned image signal, and the field / frame DCT coding decision is performed every macroblock (MB). Determined in units. The block transform is transformed by two-dimensional DCT.

The DCT transformed coefficients are basically divided into intra and non-intra quantized by the mode selected in the motion prediction.

With regard to intra frame and intra macro block quantization, intra macroblock DCT coefficients are quantized with a uniform quantizer without dead-zone. The DC coefficient quantization step size of the brightness signal and the color signals is always eight. The AC coefficients are first scaled with an intra quantizer matrix and then quantized. The interval for quantization of scaled coefficients is obtained from mquant, a quantizer variable. Mquant is obtained according to the complexity of the original image and the fullness of the buffer for each macroblock.

On the other hand, with reference to predicted and interpolated frame quantization, non-intra macroblocks in a predicted and interpolated frame are quantized by a uniform quantizer having a dead-zone near zero. The transformed coefficients are scaled by a non-intra quantizer matrix, and the DC and AC coefficients are quantized using the quantization interval obtained by mquant. In predicted and interpolated frames, intra type macroblocks are quantized as in intra frames.

Subsequently, in the case of variable length coding (ALC) of the quantized symbols, since the number of bits generated varies irregularly according to the input image, a buffer for maintaining a constant bit rate is required. In general, the beeper control is to feed back the fullness of the buffer to adjust the quantization interval of the image currently being encoded in order to prevent underflow and overflow of data.

The rate control is mainly to adjust the generation amount of data by varying the step size of the quantizer according to the buffer fullness (d _j ) and the activity of the input image (act _j ).

In other words, if the number of generated bits is greater than or equal to the reference value, the amount of data filled in the buffer is increased. Therefore, the quantization step size is increased to reduce the number of bits to be generated later. Adjust the buffer data to maintain a constant value overall.

In this case, the quantization error occurs according to the quantization step size, which directly affects the image quality, and thus, the rate control technique is one of important factors that determine the image quality.

The rate control method differs slightly depending on the video signal compression method, but the target bit is set as in the Moving Picture Expert Group (MPEG), and the virtual buffer's fullness is calculated using the actual data. As a result, there is a method of determining the quantization step size and continuously updating the target bit. As used in Digicipher, DSC-HDTV, etc. There is a method of encoding the next slice by receiving the determined step size.

Refer to the MPEG-2 material (TEST MODEL 5, document number AVC-491) under international standardization in ISO / IEC JTC1 / SC29 / WG11, the organization of the International Organization for Standardization (ISO). Is done.

The first step is to allocate a target bit, the target bit (T ₁ , for the frame to be encoded according to the image code and I (Intra) mode, B (Bidirectional interpolative) mode, P (Predictive) mode and bit rate T _B , T _P ) is set.

The second step is to adjust the transmission rate, and calculate a reference value (Q _j ) of the quantization parameter for each macro block according to the fullness of the virtual buffer.

The third step is an adaptive quantization step. After calculating the normalized activity (N-Act _j ) by obtaining an activity (Act _j : activity) of a macroblock to be encoded currently, the normalized activity (N-Act) is calculated. Multiplying by the reference value Q _j of the quantization parameter obtained in the second step to obtain a quantization parameter mquant _J to be actually used for quantization.

FIG. 1 is a block diagram of an image encoder equipped with a transmission coordination and quantization control unit. Compression codes and systems used in HDTV are shown in FIG. A subtractor 10 for outputting the input image as it is or subtracting and outputting the motion estimation image; A discrete cosine converter 12 for converting the output image of the subtractor 10 in block units to output a corresponding coefficient value; A quantizer 14 for quantizing the output of the discrete cosine converter 12 according to a predetermined quantization step (Mquant); A variable length encoder (16) for performing a zigzag scan of the quantized image data to run-length transform and then encoding the quantized image data into a variable length using a Huffman table; An inverse quantizer 18 for inversely quantizing the quantized data; An inverse discrete cosine transformer for inverse discrete cosine transforming the inverse quantized data; An adder 22 for adding the inter-frame difference image and the motion compensation image reconstructed by the inverse discrete cosine converter 20; A frame memory 24 for storing the added image data; A motion estimation unit 26 for comparing the input image with the image stored in the frame memory 24 and calculating a motion vector (MV); A motion compensator (28) for compensating image data stored in the frame memory (24) according to the motion vector (MV); A mode selector 30 which receives the input image data and the motion compensated image data and selects a mode favorable for encoding from an inter or intra mode to turn on / off a switch (SW); A buffer 32 which temporarily stores data and outputs the data at a constant speed since the variable length coded data has a constant length; A reference quantization parameter calculator (34) for calculating a reference quantization parameter (Q _j ) according to the buffer fullness (d _j ) from the buffer (32); An activity calculator 36 for calculating an activity of the input image; The quantization parameter generator 38 generates a quantization parameter (mquant) to be used for actual quantization according to the obtained reference quantization parameter (Q _j ) and the calculated activity (act _j ).

The video compression encoding system configured as described above is already widely known as MPEG-2, and is also used in HDTV. Referring to FIG. 1, the operation of each component block is described as follows.

The subtractor 10 generates a difference image between frames by subtracting the motion compensation image of the original image of the current frame and the reconstructed image of the previous frame, which are input in units of frames.

The discrete cosine transforming unit 12 outputs a discrete cosine transform coefficient by performing discrete cosine transforming of the inter-frame difference image into a block of 8x8 pixels, for example, to remove the correlation between pixels.

The quantizer 14 quantizes the discrete cosine transform coefficients of the interframe difference image output from the discrete cosine transform unit 12 at a predetermined quantization interval and outputs the quantized intervals.

In the variable length encoder 16, the variable length encoding of the inter-frame difference image quantized by the quantizer 14 is performed. For example, among the signals represented by 8 bits, more frequent data is represented by fewer bits, and less frequently data is represented. Representing as many bits reduces the total number of bits representing the difference image.

The inverse quantizer 18 is connected to the output terminal of the quantizer 14 and restores the quantized interframe difference image to a state before being input to the quantizer 14.

The inverse discrete cosine transform unit 20 is connected to an output terminal of the inverse quantizer 18, and the inverse quantized interframe difference image is input to the discrete cosine transform unit 12 by the inverse quantizer 18. Restore

The adder 22 adds the inter-frame difference image and the motion compensation image reconstructed by the inverse discrete cosine transform unit 20 and stores the reconstructed image of the previous frame in the frame memory 24.

The motion estimation unit 26 generally uses a block matching algorithm, estimates a similar portion between the image of the current frame input and the image of the previous frame stored in the frame memory 24 and outputs the result of the position shift as a motion vector. .

The motion compensator 28 outputs the motion compensation image compensated by the motion vector of the motion position of the reconstructed image for the previous frame stored in the frame memory 24.

The mode selector 30 receives the input image data and the motion compensated image data and selects a mode favorable for encoding from the inter or intra mode to turn on / off the switch SW.

The buffer 32 temporarily stores the variable-length coded data and outputs a constant speed. The reference quantization parameter calculator 34 determines the reference quantization parameter Q according to the fullness d _j of the buffer 32. _j )

The activity calculator 36 calculates an activity of an intra macro block of the input image data regardless of the encoding mode (inter or intra).

The quantization parameter generator 38 outputs the quantization parameter mquant to be used for actual quantization according to the obtained reference quantization parameter Q _j and the calculated activity act _j to the quantizer 14.

FIG. 2 is a block diagram of a conventional quantizer. The conventional quantizer determines whether an input DCT transform coefficient is positive or negative, and outputs it as it is if it is positive. 40), a first multiplexer 42 which selects and outputs one of 32 and 1, and a first multiplying the input signal from the first complement converter 40 and the input signal from the first multiplexer 42. A second multiplexer 46 that receives a multiplier 44, q-matrix and dc-precision (used for an intra-dc value), selects one of the two outputs, and divides it by 2 A shifter 48 for shifting one bit to the right with respect to the input signal from the multiplexer 46, and a first adder for adding the multiplication signal from the first multiplier 44 and the input signal from the shifter 48 ( 50), the first A first divider 52 that divides the addition signal from the adder 50 and the input signal from the second multiplexer 46, a second multiplier 54 that multiplies mquant with 32, and the second A third multiplier 56 for multiplying the multiplication signal from the multiplier 54 by a second, a third multiplexer 58 for selecting and outputting one of the multiplication signal from the third multiplier 56 and 0, and the first A second adder 60 that adds an input signal from the divider 52 and an input signal from the third multiplexer 58, a fourth multiplier 62 that multiplies mquant and 2, and the fourth multiplier 62 A fourth multiplexer 64 which selects and outputs a multiplication signal from 1 and an output signal; and a divider which divides the addition signal from the second adder 60 and the input signal from the fourth multiplexer 64. 2 divides the input signal from the divider 66 and the second divider 66 The consists of a 1's complement conversion unit only when a signal was input to the 40 negative (determined by the most significant bit), the two's complement conversion unit 68 for maintenance processing.

The conventional quantizer configured as described above is implemented by the following equation.

Where F '' [v] [u] represents the input DCT transform coefficient, W [w] [v] [u] represents the q-matrix, and quantizer-scale represents mquant.

There is a need for reducing the size of hardware while maintaining the performance of the conventional quantizer as described above.

Accordingly, an object of the present invention is to provide a quantizer having a reduced size by efficiently configuring hardware for performing quantization on a discrete cosine transformed coefficient input in an image encoder. There is this.

The quantizer of the present invention for achieving the above object, an intra-DC-multiply value generator for receiving an intra-DC-precision value and outputs an intra-DC-multiply value; A quantization scale value generator which receives a quantization scale code value and a quantization scale type value and outputs a quantization scale value; A quantization matrix storage unit for storing a quantization matrix; A control unit controlling the quantization matrix storage unit to output a quantization matrix; And an operation unit configured to quantize discrete cosine transform coefficients according to the intra-DC-multiply value, the quantization scale value, and the quantization matrix.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3 is a block diagram of a quantizer according to the present invention, and the quantizer of the present invention receives an intra-dc-precision value and outputs an intra-dc-mult value. An intra-DC-multiply value generator 70; A quantization scale value generator 72 which receives a quantization scale code value q-scale and a quantization scale type value q-scale-type and outputs a quantization scale value mquant; A quantization matrix storage unit 74 storing a quantization matrix q-matrix; A control unit (76) for controlling the quantization matrix storage unit (74) to output a quantization matrix (q-matrix); And an operation unit configured to quantize the discrete cosine transform coefficients according to the intra-dc-multiply value, the quantization scale value (mquant), and the quantization matrix (q-matrix) to output a quantized value. 78).

Here, the intra-DC-multiply value generator 70 and the quantization scale value generator 72 may be implemented by a programmable logic array (PLA).

4 is a detailed block diagram of the calculation unit shown in FIG. 3, wherein the calculation unit 78 determines whether the input DCT conversion coefficient is positive or negative, and outputs it as it is if it is positive, and if it is negative, repairs and outputs it. A first complement converter 78-1; A multiplier 78-2 for multiplying a quantization scale value mquant by a quantization matrix q-matrix; A multiplexer (78-3) which selects and outputs one of the multiplication signal from the multiplier (78-2) and the intra-DC-multiply value; A divider (78-4) for performing division on the input value from the first complement conversion unit (78-1) and the selection value from the multiplexer (78-3); The second complement converter 78-5 which receives the input value from the divider 78-4 and performs the complement processing again only when the value input to the first complement converter 78-1 is negative. ); And a rounding unit 78-6 that rounds the input value from the second complement conversion unit 78-5.

Next, the operation and effects of the present invention configured as described above will be described in detail.

The intra-DC-multiply value generator 70 receives an intra-dc-precistion value and outputs an intra-dc-mult value, and outputs an intra-dc-mult. The relationship between the value (intra-dc-precistion) and the intra-DC-multiply value (intra-dc-mult) is shown in Table 1 below.

The quantization scale value generator 72 receives a quantization scale code value (q-scale-code) and a quantization scale type value (q-scale-type) and outputs a quantization scale value (mquant). The relationship between the quantization scale value (mquant or q-scale) according to the code value (q-scale-code) and the quantization scale type value (q-scale-type) is shown in Table 2 below.

Here, the quantization scale code value (q-scale-code) is an integer.

The quantization matrix storage unit 74 stores a quantization matrix q-matrix. In this case, the quantization matrix q-matrix, that is, the weighting matrix is 4: 2: 0, is two, 4: There are four cases of 2: 2 and 4: 4: 4.

1) 4: 2: 0

(1) intra w = 0

(2) non-intra w = 1

2) 4: 2: 2 or 4: 4: 4

(1) Intra luminance w = 0

(2) non-intra luminance w = 1

(3) intra chrominance w = 2

(4) non-intra chrominance w = 3

At this time, it is the index w at w [w] [v] [u] that indicates the type of the matrix. w has a value from 0 to 3, and the relationship between the value and the matrix type is shown in Table 3 below.

Meanwhile, the controller 76 controls the quantization matrix storage 74 to output a quantization matrix q-matrix.

The operation unit 78 quantizes the discrete cosine transform coefficients according to the intra-dc-mult value, the quantization scale value (mquant), and the quantization matrix (q-matrix). Outputs a value, wherein the equation implementing the calculator 78 is as follows.

Looking at the operation unit 78 in more detail, the first complement conversion unit 78-1 determines whether the input DCT conversion coefficient is positive or negative, and outputs as it is positive, and if it is negative, it is output by complementary processing, multiplier In (78-2), the quantization scale value (mquant) is multiplied by the quantization matrix (q-matrix), and in the multiplexer (78-3), the multiplication signal and the intra-DC-multiply value from the multiplier (78-2). One value is selected and output, and the divider 78-4 divides the input value from the first complement converter 78-1 and the selected value from the multiplexer 78-3. The second complement converter 78-5 receives the input value from the divider 78-4 and performs the complement only when the value input to the first complement converter 78-1 is negative. Processing and outputting, and the rounded portion (78-6) the second repair And rounding the input value from the affected part (78-5).

As described above, according to the present invention, it is possible to efficiently implement hardware that performs quantization on the discrete cosine transformed coefficients of the image encoder, thereby reducing the hardware size while maintaining the quantization performance. .

Claims (3)

An intra-DC-multiply value generator 70 which receives an intra-dc-precision value and outputs an intra-dc-multiply value; A quantization scale value generator 72 which receives a quantization scale code value q-scale and a quantization scale type value q-scale-type and outputs a quantization scale value mquant; A quantization matrix storage unit 74 storing a quantization matrix q-matrix; A control unit (76) for controlling the quantization matrix storage unit (74) to output a quantization matrix (q-matrix); And an operation unit configured to quantize the discrete cosine transform coefficients according to the intra-dc-multiply value, the quantization scale value (mquant), and the quantization matrix (q-matrix) to output a quantized value. 78) a quantizer. The quantizer according to claim 1, wherein the intra-DC-multiply value generator (70) and the quantization scale value generator (72) are implemented with a programmable logic array. The first complement conversion unit 78-1 of claim 1, wherein the operation unit 78 determines whether the input DCT conversion coefficient is positive or negative, and outputs it as it is if it is positive. Wow; A multiplier 78-2 for multiplying a quantization scale value mquant by a quantization matrix q-matrix; A multiplexer (78-3) which selects and outputs one of the multiplication signal from the multiplier (78-2) and the intra-DC-multiply value; A divider (78-4) for performing division on the input value from the first complement conversion unit (78-1) and the selection value from the multiplexer (78-3); The second complement converter 78-5, which receives the input value from the divider 78-4 and repairs and outputs it again only when the value input to the first complement converter 78-1 is negative. ); And a rounding unit (78-6) for rounding an input value from the second complement transform unit (78-5).