KR100195270B1 - Contact hole charging method of semiconductor device - Google Patents
Contact hole charging method of semiconductor device Download PDFInfo
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- KR100195270B1 KR100195270B1 KR1019950054705A KR19950054705A KR100195270B1 KR 100195270 B1 KR100195270 B1 KR 100195270B1 KR 1019950054705 A KR1019950054705 A KR 1019950054705A KR 19950054705 A KR19950054705 A KR 19950054705A KR 100195270 B1 KR100195270 B1 KR 100195270B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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Abstract
본 발명은 반도체 소자의 금속 배선층을 위한 콘택홀 및 비아홀을 충입하는 방법에 관한 것이다. 본 발명의 반도체 소자의 접촉창 충입방법은 산화막에 형성된 접촉창 내벽과 상기 산화막상에 장벽금속층을 증착하는 단계; 상기 장벽금속층상에 열처리를 거쳐 금속층을 증착하는 단계; 상기 금속층상에 플로우가 쉬운 물질로 증착하는 단계; 및 상기 장벽금속층 전까지 식각하여 금속플러그를 형성하는 단계를 포함한다.The present invention relates to a method of filling contact holes and via holes for a metal wiring layer of a semiconductor device. Contact window filling method of a semiconductor device of the present invention comprises the steps of depositing a barrier metal layer on the inner wall of the contact window formed on the oxide film and the oxide film; Depositing a metal layer through heat treatment on the barrier metal layer; Depositing a flowable material on the metal layer; And etching until the barrier metal layer to form a metal plug.
상기 접촉창은 콘택홀 또는 비아홀일 수 있다. 상기 장벽금속층은 타이타늄, 타이타늄 나이트라이트, 타이타늄 텅스텐, 텅스텐 나이트라이드, 타이타늄 나이트라이드/타이타늄 중 하나 또는 2 이상의 조합으로 될 물질로 이루어진다. 상기 금속층으로는 알루미늄과 그의 합금, 구리와 그의 합금, 텅스텐 중 하나 또는 2 이상의 조합으로 된 물질로 이루어진다. 상기 플로우가 쉬운 물질로는 포토레지스트, 에스오지, 피에스지, 비피에스지 중 하나 또는 2 이상의 조합으로 된 물질이 사용될 수 있다. 상기 식각공정은 장벽금속층 전까지 건식식각으로 식각한 후, 잔류물질은 습식식각으로 제거한다.The contact window may be a contact hole or a via hole. The barrier metal layer is made of a material which will be one or a combination of two or more of titanium, titanium nitrite, titanium tungsten, tungsten nitride, titanium nitride / titanium. The metal layer is made of a material made of aluminum and its alloys, copper and its alloys, tungsten or a combination of two or more. As the material having an easy flow, a material made of one or a combination of two or more of photoresist, SG, PS, and BPS may be used. After the etching process by dry etching until the barrier metal layer, the residual material is removed by wet etching.
Description
제1도는 종래의 이중 금속 배선층의 구조를 도시한 개략도.1 is a schematic diagram showing the structure of a conventional double metal wiring layer.
제2도 내지 제5도는 본 발명에 일 실시예에 따라 이중 금속 배선층의 접촉창을 충입하는 공정을 설명하기 위한 도면들.2 to 5 are views for explaining a process of filling the contact window of the double metal wiring layer in accordance with an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 콘택홀 12 : 장벽금속층10 contact hole 12 barrier metal layer
13,17 : 금속층 14 : 반사방지막13,17 metal layer 14 antireflection film
15 : 금속간 절연막 16 : 비아홀15: intermetallic insulating film 16: via hole
18 : 보호막 19 : 플로우용이물질18: protective film 19: foreign matter for flow
20 : 1차패턴막 21 : 금속간 화합물20: primary pattern film 21: intermetallic compound
22 : 2차 패턴막 P : 금속플러그22: secondary pattern film P: metal plug
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 상세하게는 반도체 소자의 금속 배선층을 위한 콘택홀(contact hole) 및 비아홀(via hole)을 충입하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of filling contact holes and via holes for a metal wiring layer of a semiconductor device.
일반적으로, 반도체 소자의 고집적화에 따라 콘택홀이나 비아홀의 크기도 감소하게 된다. 작아진 콘택홀이나 비아홀로 말미암아 후속 공정인 메탈(metal) 증착시 스텝 커버리지(step coverage)가 나빠져서 오픈 불량(open failure) 및 저항 불량을 유발하게 된다.In general, as the integration of semiconductor devices increases, the size of contact holes or via holes also decreases. Due to the smaller contact holes or via holes, step coverage becomes worse during subsequent metal deposition, leading to open failure and poor resistance.
이러한 문제점을 개선하기 위해 종래에는 리플로우(reflow) 고온 스퍼터링(sputtering)방법 또는 화학 증착 방법을 이용한 금속 증착 방법등이 이용되거나 제시되고 있다. 이와 같은 방법들은 특수 공정이기 때문에 새로운 증착 설비를 사용하여만 가능하다.In order to improve such a problem, conventionally, a reflow high temperature sputtering method or a metal deposition method using a chemical vapor deposition method is used or suggested. Because these methods are special processes, they are only possible using new deposition equipment.
본 발명은 상기한 종래의 단점을 해결하기 위하여, 반도체 소자의 금속 배선층의 콘택홀이나 비아홀을 완전히 충입시키는 방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for completely filling a contact hole or a via hole of a metal wiring layer of a semiconductor device.
본 발명은 상기 목적을 달성하기 위하여, 반도체 소자의 접촉창 충입 방법에 있어서,The present invention, in order to achieve the above object, in the contact window filling method of a semiconductor device,
산화막에 형성된 접촉창 내벽과 상기 산화막상에 장벽금속층을 증착하는 단계;Depositing a barrier metal layer on the inner wall of the contact window formed on the oxide film and the oxide film;
상기 장벽금속층상에 열처리를 거쳐 금속층을 증착하는 단계;Depositing a metal layer through heat treatment on the barrier metal layer;
상기 금속층상에 플로우가 쉬운 물질로 증착하는 단계; 및Depositing a flowable material on the metal layer; And
상기 장벽금속층 전까지 식각하여 금속플러그를 형성하는 단계를 포함하는 반도체 소자의 금속배선층 접속창 충입방법을 제공한다.It provides a method for filling a metal wiring layer connection window of a semiconductor device comprising the step of etching until the barrier metal layer to form a metal plug.
바람직하기로는 상기 접속창은 콘택홀 또는 비아홀일 수 있다.Preferably, the connection window may be a contact hole or a via hole.
또, 바람직하게는 상기 장벽금속층은 타이타늄, 타이타늄 나이트라이트, 타이타늄 텅스텐, 텅스텐 나이트라이드, 타이타늄 나이트라이드/타이타늄 중 하나 또는 2 이상의 조합으로 된 물질로 이루어진다.In addition, the barrier metal layer is preferably made of a material consisting of one or a combination of two or more of titanium, titanium nitrite, titanium tungsten, tungsten nitride, and titanium nitride / titanium.
또, 바람직하게는 상기 플로우가 쉬운 물질로는 포토레지스트, 에스오지, 피에스지, 비피에스지 중 하나 또는 2 이상의 조합으로 된 물질이 사용될 수 있다.In addition, preferably, the material having an easy flow may be a material made of one or a combination of two or more of photoresist, SOH, PS, BPS.
또, 바람직하게는 상기 식각공정은 장벽금속층 전까지 건식식각으로 식각한후, 잔류물질은 습식식각으로 제거한다.In addition, after the etching process by dry etching until the barrier metal layer, the residual material is removed by wet etching.
또, 바람직하게는 상기 플러그형성물질은 알루미늄, 알루미늄합금, 구리, 구리합금, 텅스텐 중의 하나 또는 2 이상의 조합으로 된 물질인 것을 특징으로 한다.In addition, the plug forming material is preferably characterized in that the material is made of one or a combination of two or more of aluminum, aluminum alloy, copper, copper alloy, tungsten.
이하, 본 발명의 구성 및 동작에 대해서 첨부된 도면을 참조하여 보다 상세히 설명하기로 한다.Hereinafter, the configuration and operation of the present invention will be described in detail with reference to the accompanying drawings.
우선, 본 발명을 설명하기 전에, 제1도를 참조하여, 종래의 방법으로 제조된 이중 금속 배선층을 형성하는 공정을 설명할 것이다. 제1도에 의하면, 종래의 반도체 소자의 콘택홀(1) 또는 비아홀(6)과 같은 접촉창의 충입시, 산화막(100)에 콘택홀(1)을 형성한 후에 콘택홀(1) 내벽 및 산화막(100)위에 보호금속층(2)을 증착하고 열처리를 거쳐서 금속층(3)을 증착한 후 반사방지막(4)을 증착한 다음 패터닝(patterning)을 하여 1차 금속배선을 형성한다. 금속배선이 형성된 후 금속간 절연막(5)을 증착하고 비아홀(6)을 뚫고 이차금속(7)을 증착하여 패터닝하고 보호막(8)을 증착하여 2차 금속배선을 형성하고 있다. 앞에서 기술한 대로, 이러한 종래의 공정은 콘택홀이나 비아홀이 작아지므로 발생되는 오픈 불량 및 저항 불량을 유발하는 것이 단점으로 지적되었다.First, before describing the present invention, a process of forming a double metal wiring layer manufactured by a conventional method will be described with reference to FIG. According to FIG. 1, when the contact window 1 such as the contact hole 1 or the via hole 6 of the conventional semiconductor device is filled, the contact hole 1 is formed in the oxide film 100, and then the inner wall and the oxide film of the contact hole 1 are formed. The protective metal layer 2 is deposited on the (100), the metal layer 3 is deposited through heat treatment, the antireflection film 4 is deposited, and then patterned to form a primary metal wiring. After the metal wiring is formed, the intermetallic insulating film 5 is deposited, the via hole 6 is drilled, the secondary metal 7 is deposited and patterned, and the protective film 8 is deposited to form the secondary metal wiring. As described above, it has been pointed out that this conventional process causes an open failure and a resistance failure that occur because contact holes or via holes become smaller.
본 발명에서는 포토레지스트(phototresist), 에스오지(SOG), 도프트(doped) 또는 언도프트(undoped)산화막등과 같은 플로우(flow)가 잘 일어나는 절연막을 사용하여 금속층을 에치백(etch back)하여 금속 플러그(plug)를 제작하여 콘택홀이나 비아홀을 완전히 채우는 방법을 제시하고자 한다.In the present invention, the metal layer is etched back by using an insulating film having a good flow such as a photoresist, SOG, doped or undoped oxide film, and the like. The present invention proposes a method of fabricating a metal plug to completely fill a contact hole or via hole.
제2도에서 제5도까지는 본 발명에 의한 반도체소자의 금속 배선층을 위한 접촉창의 충입방법의 구체적 실시예를 도식화 한 도면들이다.2 to 5 are diagrams illustrating specific embodiments of a method of filling a contact window for a metal wiring layer of a semiconductor device according to the present invention.
제2도는 산화막(100)에 콘택홀(10)을 뚫은 후 콘택홀(10)내벽 및 산화막(100)위에 장벽금속층(12)을 증착하고 열처리한 후 일차금속층(13)이 콘택홀(10)을 충분히 덮도록 증착한다. 상기 금속층(13)의 증착 후에는 화학 증착법이나 물리 증착법에 의한 산화막이나 포토레지스트(photo resist), 에스오지, 피에스지, 비피에스지, 도프트 또는 언 도프트 산화막 등과 같은 플로우(flow)가 잘 일어나는 재료(19)를 증착한 후 장벽금속층(12)을 에치 스토퍼(etch stopper)로 이용하여 장벽금속층(12)의 전까지 식각을 실시한다.FIG. 2 illustrates that after the contact hole 10 is drilled through the oxide film 100, the barrier metal layer 12 is deposited on the inner wall of the contact hole 10 and the oxide film 100, and heat-treated. Deposit so that it covers enough. After the deposition of the metal layer 13, a flow such as an oxide film, a photoresist, S-OG, PSG, BPS, doped or undoped oxide film, which is caused by chemical vapor deposition or physical vapor deposition, occurs well. After the material 19 is deposited, the barrier metal layer 12 is used as an etch stopper before etching the barrier metal layer 12.
바람직하게는 상기 장벽금속층(12)은 타이타늄, 타이타늄 나이트라이트, 타이타늄 텅스텐, 텅스텐 나이트라이드, 타이타늄 나이트라이드/타이타늄 중 하나 또는 2 이상의 조합으로 된 물질로 이루어진다. 또, 바람직하게는 상기 금속층(13)으로는 알루미늄과 그의 합금, 구리와 그의 합금, 텅스텐 중 하나 또는 2 이상의 조합으로 된 물질로 이루어진다. 또, 바람직하게는 상기 식각공정은 장벽금속층(12)전까지 건식식각으로 식각한 후, 잔류물질은 습식식각으로 제거한다.Preferably, the barrier metal layer 12 is made of a material made of one or a combination of two or more of titanium, titanium nitrite, titanium tungsten, tungsten nitride, and titanium nitride / titanium. Preferably, the metal layer 13 is made of a material made of aluminum, an alloy thereof, copper, an alloy thereof, tungsten, or a combination of two or more thereof. In addition, preferably, the etching process is performed by dry etching until the barrier metal layer 12, and the residual material is removed by wet etching.
제3도에 의하면, 에치백 후 잔류 포토레지스트를 제거하면 알루미늄, 알루미늄합금, 구리, 구리합금, 텅스텐 중의 하나 또는 2 이상의 조합으로 된 금속층(13)은 콘택홀(10)에만 남게 되어 금속플러그(P)를 형성하게 된다. 그 후 상기 장벽금속층(12) 및 상기 금속플러그(P)위에 다시 금속층(20)을 증착하고 반사방지막(14)을 금속층(20)위에 증착한 후 패터닝을 한다.According to FIG. 3, when the residual photoresist is removed after the etch back, the metal layer 13 made of one of aluminum, aluminum alloy, copper, copper alloy, tungsten, or a combination of two or more remains in the contact hole 10 so that the metal plug ( P) is formed. After that, the metal layer 20 is again deposited on the barrier metal layer 12 and the metal plug P, and the antireflection film 14 is deposited on the metal layer 20 and then patterned.
제4-5도는 제2-3도를 참조하여 설명한 콘택홀(10)의 충입공정과 동일한 방법 및 재료로 비아홀(16)에 금속플러그를 충입형성하는 공정을 도시하고 있다.4-5 illustrate a process of filling and forming the metal plug into the via hole 16 by the same method and material as the filling process of the contact hole 10 described with reference to FIGS.
제4도에 의하면, 패터닝된 1차패턴막(20)상에 금속간 절연막(15)을 증착한 후, 상기 절연막(15)내에 상기 반사방지막(14)까지 비아홀(16)을 뚫고 타이타늄나이트라이드(TiN)이나 타이타늄 텅스텐(TiW)과 같은 금속간 화합물(21)을 증착하고, 그 위에 이차금속(17)을 증착한다.Referring to FIG. 4, after the intermetallic insulating film 15 is deposited on the patterned primary pattern film 20, the nitride hole is drilled through the via hole 16 to the antireflection film 14 in the insulating film 15. An intermetallic compound 21 such as (TiN) or titanium tungsten (TiW) is deposited, and a secondary metal 17 is deposited thereon.
증착된 이차금속(17)위에 플로우(flow)가 잘 일어나는 언도프트산화막, 도프트산화막 또는 에스오지(SOG), 피에스지, 비피에스지와 같은 재료(19)를 증착한다.On the deposited secondary metal 17, a material 19 such as an undoped oxide film, a dope oxide film or SOG, a PSG, a BPS paper which flows well is deposited.
그 다음, 제5도에 도시한 바와 같이, 금속간 화합물(21)을 에치스토퍼(etch stopper)로 이용하여 에치백한 후 다시 금속층(22)을 증착하고 패터닝하여 보호막(18)을 증착한 2차패턴막(22)을 형성함으로써 이중 금속 배선층이 형성된다.Next, as shown in FIG. 5, the intermetallic compound 21 is etched back using an etch stopper, and then the metal layer 22 is deposited and patterned again to deposit the protective film 18. By forming the difference pattern film 22, a double metal wiring layer is formed.
상술한 바와 같은 공정을 거쳐 생성된 반도체 소자는 콘택홀이나 비아홀이 금속플러그 형태로써 완벽하게 채워지기 때문에 콘택홀이나 비아홀의 저항 불량의 발생이 방지되고 신뢰도 측면에서도 크게 향상이 된다. 또한, 다중금속배선층의 형성 공정에서의 평탄화에도 크게 효과를 볼 수 있다.Since the semiconductor device produced through the above-described process is completely filled with the contact hole or the via hole in the form of a metal plug, the resistance failure of the contact hole or the via hole is prevented and the reliability is greatly improved. In addition, the effect can be greatly improved in the planarization in the formation process of the multi-metal wiring layer.
Claims (7)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100459332B1 (en) * | 1997-12-30 | 2005-04-06 | 주식회사 하이닉스반도체 | Metal wiring formation method of semiconductor device |
| KR100486108B1 (en) * | 1997-12-19 | 2005-08-31 | 매그나칩 반도체 유한회사 | Multilayer wiring formation method of semiconductor device |
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| KR100782202B1 (en) * | 2005-02-25 | 2007-12-05 | 가부시끼가이샤 도시바 | Semiconductor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100486108B1 (en) * | 1997-12-19 | 2005-08-31 | 매그나칩 반도체 유한회사 | Multilayer wiring formation method of semiconductor device |
| KR100459332B1 (en) * | 1997-12-30 | 2005-04-06 | 주식회사 하이닉스반도체 | Metal wiring formation method of semiconductor device |
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