KR100191724B1 - An apparatus for receiving data - Google Patents

Abstract

The present invention detects the information transmission rate of a modem for a data terminal that can be obtained by decoding the information transmission rate and the data format corresponding to the speed using the result of counting the main clock signal when receiving data by the asynchronous serial interface modem. Relates to a device.

Conventionally, since the central processing unit detects the transmission speed by using interrupt processing, many interrupt ports must be allocated to the speed detection, and since the central processing unit is responsible for the transmission speed detection, other interrupts are performed during the execution of the transmission speed detection routine. It entails the restriction that the original processing cannot be performed, and there is a problem of lowering reliability.

The present invention provides counting means for counting a bit transition period of received data as a main clock signal MCLK, speed detecting means for storing the counted value as a transmission rate detected value, and receiving the received value using the counted value. Data detection means for detecting a data value to be converted; format determination means for decoding the detected data value to determine a transmission format; and storing and outputting the main clock signal count and count value, and detecting and corresponding data value. A control means for generating the control signals necessary for the determination of the transmission format to be supplied to each unit and configuring the information transmission rate detection device of the modem for the data terminal, thereby limiting the use of an interrupt port or the burden on the central processing unit for detecting the transmission rate. Reduce the number of interrupts and perform other interrupt or control processing while the CPU detects the baud rate. , And it provides the data transmission (the reception) of the modem for the data terminal so as to ensure the reliability of the system information transmission rate detecting device.

Description

Data receiver

The present invention enables a data terminal modem to automatically detect the baud rate of digital information. In particular, when a data is received by an asynchronous serial interface modem, the main clock signal is used to obtain information. The present invention relates to a data receiving apparatus capable of decoding and obtaining a transmission speed and a data format corresponding to the speed, thereby receiving data.

FIG. 1 is a circuit configuration for detecting a data transmission speed in a conventional interface modem for a data terminal.

As shown in FIG. 1, a central processing unit (CPU) 1 for determining a data transmission speed, an interface (UART) 2 for data transmission and reception, and a counterpart data terminal device (DTE) connected to a communication line (3).

When data is received from the counterpart's data terminal device 3 via the communication line to the interface 2, the interface 2 issues interrupts INT1 and INT2 to the central processing unit 1 so that the transmission rate can be determined. do.

In other words, the interface between the data terminal and the modem uses the RS232C asynchronous serial interface, which has two characters (AT or at), which are command prefixes of Hayes AT Command Set, which is a standard for commands between modems and terminals. Character) Data format is detected to detect the transmission speed and data format.

As an example of the detection method, the case of a character data reception (Rx) will be described with reference to FIG.

Waiting for the interrupt INT1 to detect the data transfer rate in the central processing unit 1.

On the data terminal device 3 side, the data terminal apparatus 3 maintains an 'O' state during the 1-bit duty ratio for the start bit transmission.

At this time, interrupt 1 INT1 occurs, and when this interrupt INT1 occurs, the central processing unit 1 runs the internal timer.

Subsequently, when a data transition occurs from the '0' state to the '1' state, this is accepted as interrupt 2 (INT2), and when interrupt 2 (INT2) occurs, the CPU 1 stops the timer inside the upper part. The data transfer rate is detected by loading the timer value, which is the time difference between interrupt 1 and interrupt 2 (INT1-INT2).

Thereafter, the data format is determined by searching whether the seventh, eighth and ninth data bit strings are '1' or '0' using whether or not an interrupt is generated using the detected transfer rate.

In the case of the character data t, the data format is also determined by the above-described processing.

That is, the information transmission speed detection device of the modem for a data terminal in the prior art issues a plurality of interrupts to the central processing unit 1 by using a signal transition in accordance with the data transmission, and the central processing unit 1 uses the interrupt generation. The internal timer detects the data transfer rate and also determines the data format.

Therefore, the central processing unit 1 must allocate a plurality of interrupt ports for the transmission rate detection.

The allocation of such interrupt ports limits the range of use of a limited number of interrupt ports, restricts the use of interrupt ports, and performs the transmission rate detection routine because the central processing unit 1 bears the transmission rate detection. Problems with other interrupt sources cannot be handled, resulting in a decrease in CPU performance, and in the case of high-speed communication, the time required to detect the data format and initialize the interface 2 is too long. If it is shortened, there is a problem that the reliability of the data transmission (receipt) system does not operate due to the time burden is high.

The present invention solves the conventional problems as described above, thereby reducing the restriction on the use of an interrupt port and the burden on the central processing unit for detecting the transmission rate, and performing other interrupt or control processing while the central processing unit detects the transmission speed. In addition, it is an object of the present invention to provide a data receiving apparatus that can ensure the reliability of the data transmission (reception) system.

1 is a block diagram showing a configuration for detecting an information transmission rate in a conventional data receiving apparatus.

2 is a conventional information transmission rate detection timing diagram.

3 is a block diagram showing the configuration of the data receiving apparatus of the present invention.

4 is a block diagram of an information transmission rate detecting device according to the present invention.

5 is a waveform diagram of received data applied to the present invention.

6 is a data format decoding table applied to the present invention.

* Explanation of symbols for main parts of the drawings

5, 8, 9: Counter 6, 7, 12: Register

10: shift register 11: memory

13: control circuit

The data receiving apparatus of the present invention for achieving the above object is a configuration in which the transmission rate detecting device 4 is connected between the interface 2 and the counterpart data terminal device 3, as shown in FIG. The transmission rate detecting apparatus 4 detects the information transmission rate and its transmission format using signal data transmitted from the counterpart data terminal apparatus 3 together with the transmission data for data transmission, and detects the detection result and the central processing unit. Provide to (1).

Such a transmission rate detecting apparatus includes counting means for counting a bit transition period initially provided for any character data provided from a counterpart data terminal for information transmission as a main clock signal MCLK, and by the counting means. Speed detecting means for storing the counted value as a transmission speed detection value and outputting the stored value, data detecting means for detecting the received data value using the value counted by the counting means, and the detected data Format determination means for decoding a value to determine a transmission format and outputting the determined result, storing and outputting the main clock signal count and count value, and detecting a data value and determining a transmission format corresponding thereto. And control means for generating and supplying control signals to each unit.

Figure 4 shows a circuit configuration of the embodiment of the transmission rate detection apparatus applied to the present invention as described above.

Referring to FIG. 4, the configuration of the counting means includes a counter 5 which is enabled during the data transition period initially provided in response to the received data Rx and counts the main clock signal MCLK. The speed detecting means includes a first register 6 which temporarily stores the value counted by the counting means, and a second register 7 which temporarily stores the output value of the register 6 and outputs it as a speed detection value. And the data detection means is reloaded at every character value detection period of the reception data Rx and the counted value is counted down as the main clock signal MCLK. A down counter 8, a shift counter 9 for counting these outputs each time an output occurs in the down counter 8, and outputting them as a count value reload signal by character detection; And a register 10 for shifting the literal data Rx each time an output occurs from the down counter 8, and outputting a received data value. A memory 11 for storing information related to the data, and outputting from the memory 11 a data detection value output from the data detection means as an address value, and outputting the transfer format value stored therein; And a format output register 12 for temporarily storing the transferred transmission format value together with the speed detection value, wherein the control means includes an enable signal for detecting a data value when the data is received, and a main clock signal. An output signal for outputting a load and output enable signal for storing and outputting each count result or detection result; It consists of a circuit 13.

In the figure, 14 and 15 are buffers, Rx denotes receive data, Tx-out denotes transmission data output, and Tx-in denotes transmission data input.

The automatic detection of the transmission speed and the format detection operation by the transmission rate detecting device configured as described above are performed as follows.

The automatic detection start (RUN) is instructed by the central processing unit 1 for the automatic detection of the transmission speed, whereby the control circuit 13 supplies the enable signal EN to the buffer 14 so that the buffer 14 ) Is enabled, and the enable signal EN is input to the counter 5.

The counter 5 counts the main clock signal MCLK while '0' of the initial bit provided under the control of the control circuit 13 in response to the received data Rx. When a signal transition occurs to 1 ', the control circuit 13 stops the counting operation of the counter 5 by using the enable signal EN.

Therefore, the counter 5 counts the time for maintaining the state of '0' during the 1-bit duty ratio, which is provided for data transmission at the beginning when data is transmitted from the counterpart data terminal apparatus 3 side. The result is a result of counting a transmission rate value corresponding to the main clock signal MCLK.

For example, as shown in FIG. 5, in the case of the character 'at', the '0' section is counted as the main clock signal MCLK at the start time of 'a' value transmission.

The count value D15-D0 is input to the first register 6, and at this timing, the first register 6 receives the load signal LOAD from the control circuit 13 and loads the count value.

Of the values T15-T0 loaded in the first register 6, the output values T15-T4 excluding the lower four bits are input to the second register 7, and at this timing, the control circuit 13 receives the second value. By inputting the load signal LOAD into the register 7, the input values T15-T1 are stored.

As described above, since the second register 7 stores and outputs the 4-bit shifted value among the clock signal count values in which the main clock signal MCLK is divided into 16 by the counter, the value of the second register 7 is interfaced. (2) It can be used as it is as the upper value T15-T12 and the lower value T11-T4 of the divider latch register of (UART).

On the other hand, the value T15-T1 loaded and output in the first register 6 is input to the down counter 8 (IN = D14-D0), and the down counter 8 is loaded by the control circuit 13. The input value is loaded by the signal LOAD, and the loaded value is down counted by the main clock signal MCLK.

That is, the first one bit data is detected.

When the down counter 8 outputs the down count result of the loaded value, the shift counter 9 counts this value, and the control circuit 13 transmits the counter 9 to the down counter 8 when the counter 9 is output. The reset signal RESET is supplied to reset the down counter 8, and the load signal LOAD is supplied to reload the output values T15-T1 of the first register 6, and then the load is loaded. The operation of counting the calculated value as the main clock signal MCLK is repeatedly performed.

Therefore, the down counter 8 outputs a shift clock signal (SHIFT CLOCK) as a count result for each 1-bit data period. Accordingly, as shown in FIG. 5, from the first 1-bit data, the second 1-bit data is output. The third one bit data, the sixth one bit data, the seventh one bit data, the eighth one bit data, the ninth one bit data, and the tenth one bit data are sequentially detected.

Each time the shift clock signal SHIFT CLOCK is output from the down counter 8, the shift register 10 shifts the received data Rx and outputs the OUT signal. At this time, the enable signal of the control circuit 13 is output. Enable control by (EN).

That is, the received character data is input (IN) to the shift register 10, and this input data is shifted by the clock signal (SHIFT CLOCK) every 1 bit and outputted (OUT).

For example, in FIG. 5, in the case of the character 'a', since the data is '61H' (0110 0001), the value output from the shift register 10 is '0110 0001'.

Among the values output from the shift register 10, as shown in FIG. 5, three bit data values A4, A3, and A2 detected at the sixth, eighth, and ninth data shift timings are stored in the memory 11; In the address (A4, A3, A2).

Then, the second bit data values A1 and A0 detected at the eighth and ninth data shift timings are subjected to the same sequence as described above with respect to the next character 't'. Enter A0).

In the memory 11, a decoding table as shown in Fig. 6 is stored in advance.

This decoding table is created with a value corresponding to each case of FIG.

Therefore, a format data type is decoded corresponding to the data detection value detected from the shift register 10 and input to the addresses A4-A0 into the memory 11, and the corresponding decoding result (code) is decoded. The output terminal DATA outputs the output enable signal OE of the control circuit 13.

For example, when the 'at' character has been transmitted from the counterpart data terminal, an error (code FFH) is detected if the detected A4-A0 value is '00000', and a 7-bit even parity format (code is set) if '00111' is detected. OAH), etc., to detect the data format.

This output coded value is stored in the format output register 12 by a load signal LOAD supplied from the control circuit 13 to the format output register 12.

When all of the above operations are completed, the control circuit 13 disables the buffer 14, and supplies an output enable signal OE to the second register 7 and the format output register 12. The transmission speed detection information stored in the second register 7 is loaded into the central processing unit 1 while the data format information stored in the format output register 12 is transferred to the central processing unit 1. Load and initialize the interface (2).

As a result, the automatic transmission speed detection operation of the transmission speed detection device is completed, and the CPU 1 receives data transmitted from the counterpart data terminal device 3 according to the transmission speed and transmission format detected as described above. Done.

As described above, according to the present invention, in detecting the information transmission speed and the format of the modem for the data terminal, the central processing unit is interrupted by automatically performing the counting of the main clock signal and the decoding of the data value. The central processing unit itself can be solved, and the problem of the conventional technology can be solved, and the efficiency of the interrupt port can be improved, and the central processing unit itself is not intervened during the above process for detecting the transmission speed. You will not be interrupted by other routines.

Therefore, it is possible to improve the system performance and operate the data terminal modem efficiently, and to install the information transmission rate transmitting device of the data terminal modem of the present invention inside the UART chip, it is possible to simplify the circuit configuration and improve the chip performance. It can be effective.

Claims (7)

A transmission rate detecting apparatus for detecting a transmission rate and a transmission format of received data using signal data transmitted from the other party's data terminal for information transmission, an interface unit for an interface between the other party's data terminal and the main system, and the other party's data And a central processing unit for controlling the system to receive data according to the transmission rate and transmission format detected from the transmission rate detection device when receiving information from the terminal through the interface. The apparatus of claim 1, wherein the apparatus for detecting a transmission rate comprises: counting means for counting an initial bit transition period of data provided from a counterpart data terminal for information transmission as a main clock signal MCLK, and counted by the counting means; Speed detecting means for storing a value as a transmission speed detection value and outputting the stored value, data detecting means for detecting the received data value using the value counted by the counting means, and the detected data value Format determination means for decoding a transmission signal to determine a transmission format and outputting the determined result, storing and outputting the main clock signal count and count value, and detecting data values and determining a transmission format corresponding thereto. And control means for generating signals and supplying the signals to the respective units. Data receiving apparatus for a. 3. The speed detecting means according to claim 2, wherein said speed detecting means comprises: a first register (6) for temporarily storing a value counted by said counting means, and a second value for temporarily storing an output value of said register (6) and outputting it as a speed detection value; A data receiving device, characterized in that it consists of two registers (7). The data detection means of claim 2, wherein the value counted by the counting means is reloaded at every character value detection period of the received data Rx, and the loaded value is converted into the main clock signal (3). A down counter 8 for down counting with MCLK), a shift counter 9 for counting this each time an output occurs in the down counter 8 and outputting it as a count value reload signal by character detection; And a shift register (10) for outputting a received data value by shifting the received character data (Rx) each time an output occurs in the down counter (8). 3. The apparatus according to claim 2, wherein said format determining means stores information related to the transmission format of said received data Rx, receives said data detection value output from said data detecting means as an address value, and stores said information. And a memory 11 for outputting the corresponding transport format value, and a format output register 12 for temporarily storing the transport format value output from the memory 11 and outputting the transport format value together with the speed detection value. Data receiving device. 4. The upper and lower register values of the interface UART according to claim 3, wherein the second register 7 stores the remaining upper bit values other than the lower four bits among the output values of the first register 6, and stores the four bit shifted values. Data receiving apparatus characterized in that the output. 3. The counter according to claim 2, wherein said counting means is enabled during an initial data transition period provided in correspondence with the received data Rx and counts a counter clock 5 as a main clock signal MCLK for a '0' period. Data receiving device, characterized in that configured.