KR100190842B1 - An atm switching device and the method using parallel cdp detection - Google Patents

Abstract

The present invention relates to an ATM switching device and a switching method using parallel CDP detection, and simultaneously latches a plurality of input buffers for temporarily storing ATM cells input from the outside and CDP bits of ATM cells stored in the input buffer. A parallel CDP detector for separating and outputting a delay priority ATM cell and a loss priority ATM cell, a first cell buffer for receiving and storing a loss priority ATM cell from the parallel CDP detector, and storing data in the first cell buffer A full signal detector for outputting a predetermined control signal to the parallel CDP detector so as to temporarily stop the data input of the first cell buffer if it is determined that the data has been stored. A second cell buffer for receiving and storing a second cell and an ATM cell stored in the first and second cell buffers based on a predetermined order. An output cell selection switch for selectively outputting the number of delay priority ATM cells output from the second cell buffer, and when the number is greater than or equal to a predetermined setting value, the first cell buffer data is smaller than the predetermined setting value. A counter for controlling the output cell selection switch and an output buffer for receiving data from and outputting data from any one of the first and second cell buffers, so as to properly use the size of the input buffer. It is possible to prevent the input ATM cell from being lost due to the full state of the input buffer.

Description

An ATM Switching Device and the Method Using Parallel CDP Detection

The present invention relates to an ATM switching device and a switching method using parallel CDP (Cell Delay Priority) (hereinafter referred to as 'CDP') detection, and more specifically, to voice or image data used in an ATM switch, The present invention relates to an ATM switching device and a switching method using parallel CDP detection, which improves a serial CLP (cell loss priority; CLP) detection method for setting transmission priority of character data.

A key technology for the construction of a high-speed information communication network is an asynchronous transfer mode (ATM), and the services provided by the ATM are mainly used for providing a telephone network service and text data that deliver voice and video data. It is divided into packet network service.

The voice and image data are required to be processed in real time, and a certain amount of data loss is allowed within the range that does not affect the quality of the entire transmitted information. That is, the audio and image data are sensitive to data delay and have some margin for data loss.

The two services of opposite concepts are determined by the CLP bits in the ATM cell header. This indicates character data sensitive to the data loss when the CLP bit is '0' (LL), and sensitive to the data delay (LD: Low Delay) when the CLP bit is '1'. One audio and image data is shown.

1 is a diagram illustrating an ATM switching apparatus using serial CDP detection according to a conventional embodiment.

Referring to FIG. 1, an ATM switching device includes a cell receiver (CR1CRN) (3-13-N), an input buffer (IB1IBN) 4-14-N, and a cell queuing buffer 5. And a switch controller 6, first and second switches 8 and 12a12b, a cell buffer array 9, a cell number monitor 13, and a cell server ( 7), an output buffer (OB) 10 and a cell transmitter (CT) 11.

The cell receiver 3-13-N receives N ATM cells from the outside through an ATM cell input link 11-11-N, and outputs the N ATM cells when all of the N ATM cells are input.

The input buffer 4-14-N receives and outputs the N ATM cells from the cell receiver 3-13-N.

In addition, the cell queuing buffer 5 evaluates the CLP bits of each of the ATM cells received from the input buffer 4-14-N, and sequentially stores the loss priority and delay priority ATM cells in a predetermined buffer array. Save them one by one.

If the CLP bit of the ATM cell input from the input buffer 4-14-N to the cell queuing buffer 5 is '0', this ATM cell is a loss priority ATM cell as shown in FIG. 1. It is stored in the LL region of the cell buffer array 9.

On the other hand, if the CLP bit is '1', this ATM cell is a delay priority ATM cell and is stored in the LD area of the cell buffer array 9 as shown in FIG.

At this time, the switch controller 6 turns the first switch 8 on and off so that the loss priority and delay priority ATM cells are stored in respective predetermined buffers, and the cell buffer array 9 switches the loss priority ATM. The cell and the delay priority ATM cell are stored in the LL region and the LD region, respectively.

The cell number monitor 13 counts the output of the loss priority ATM cell and controls the second switches 12a, 12b, and the cell server 7 outputs the ATM cell from the cell buffer array 9. Input and output.

In addition, the output buffer 10 receives the ATM cell from the cell server 7 and outputs it, and the cell transmitter 11 transmits the ATM cell received from the output buffer 10 through the ATM cell output link 2. Output it.

As described above, the LOW DELAY OR LOW LOSS SWITCH FOR ATM (Patent Application No. 5,390,176), filed on February 14, 95, has been serialized in the cell queuing buffer 5, as shown in FIG. Since the CLP bits of the ATM cells are detected one by one and sequentially stored in the corresponding buffer of the cell buffer array 9, when the number N of the input ATM cells increases, one by one is detected serially and stored in the corresponding buffer sequentially. The difference between the time for letting and the time for entering the input ATM cell becomes large. Therefore, when the ATM cell is input when the incoming ATM cells are all input to the input buffer and become 'Full', the input ATM cell data is lost.

In addition, in order to prevent the loss of the input ATM cell data, a problem arises in that the size of the input buffer 4-14-N is increased or the storage capacity of the cell queuing buffer 5 is increased. .

The present invention has been proposed to solve the above-mentioned problems, and through CDP parallel detection, to provide an ATM switching device and a switching method capable of appropriately maintaining the size of the ATM cell input buffer and the storage capacity of the ATM cell detection device. The purpose is.

1 is a diagram showing an ATM switching device using serial CLP detection according to a conventional embodiment;

2 illustrates an ATM switching device using parallel CDP detection according to an embodiment of the present invention;

3 illustrates the structure of an ATM cell according to the present invention;

4 is a flowchart illustrating an ATM switching method using parallel CDP detection according to another embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

2, 60: ATM cell output link 3-1 3-N: cell receiver

5: cell queuing buffer 6: switch controller

7: cell server 8: first switch

9: Cell buffer array 10, 800: Output buffer

11 cell transmitter 12a 12b second switch

13: cell number monitor 200: parallel CDP detector

300: first cell buffer 400: full signal detector

500: second cell buffer 600: output cell selection switch

700: counter 902: CDP detection bit

904: ATM cell header 906: ATM cell data

1-1 1-N, 50-1 50-N: ATM cell input link

4-1 4-N, 100-1 100-N: Input buffer

According to a feature of the present invention proposed to achieve the above object, an ATM switching device using a parallel CDP detection method, a plurality of input buffers for temporarily storing an ATM cell input from the outside, and is stored in the input buffer A parallel CDP detector configured to simultaneously latch the CDP bits of the ATM cell to separate and output a delay priority ATM cell and a loss priority ATM cell, and a first CD receiving and storing the loss priority ATM cell from the parallel CDP detector. It is detected whether all data is stored in the cell buffer and the first cell buffer, and if it is determined that all data is stored, a predetermined control signal is sent to the parallel CDP detector to temporarily stop data input of the first cell buffer. A second signal for receiving and storing the delayed priority ATM cell from the parallel CDP detector; A cell buffer, an output cell selection switch for selectively outputting ATM cells stored in the first and second cell buffers in a predetermined order, and the number of delay priority ATM cells output from the second cell buffer; A counter for controlling the output cell selection switch so that the first cell buffer data is output by a number smaller than the predetermined set value when the count is greater than or equal to a predetermined set value, and the first and second cell buffers It includes an output buffer for receiving data from any one of the cell buffer.

In a preferred embodiment of this aspect, the ATM cell includes ATM cell data and ATM cell header, and predetermined CDP detection bits.

In a preferred embodiment of this feature, the ATM cell header includes a CLP bit indicating whether or not the loss priority ATM cell.

In a preferred embodiment of this aspect, the CDP detection bit 902 is set to either a delay priority bit or a loss priority bit, depending on the result of detecting the CLP bit in the ATM cell header by an external device.

In a preferred embodiment of this aspect, the first and second cell buffers are buffers of a first-in, first-out structure.

According to another aspect of the present invention, a plurality of cell input buffers, a parallel CDP detector, a first cell buffer storing a loss priority ATM cell, a second cell buffer storing a delay priority ATM cell, a full signal detector, a cell selection A switching method of an ATM switching device using a parallel CDP detection method including a switch, a counter, and an output buffer includes storing an ATM cell from the outside in the plurality of input buffers, and storing the loss priority bits of the respective ATM cells. Detecting and setting a delay priority bit of each corresponding ATM cell to one of '1' and '0', simultaneously inputting each set ATM cell to the parallel CDP detector; After detecting the delay priority bit of each ATM cell, storing the ATM cell in a corresponding one of the first and second cell buffers according to a value thereof, and filling the first cell buffer Determining whether the first cell buffer is not filled, outputting an ATM cell of the second cell buffer, and outputting an ATM cell of the second cell buffer to a predetermined value. Judging whether the ATM cell of the second cell buffer is less than a predetermined value by determining whether or not the set value is equal to or greater than a preset value; and returning to outputting the ATM cell of the second cell buffer; When the buffer is filled with the ATM cells and when the output count of the ATM cell is greater than or equal to a predetermined value in the step, outputting the ATM cell of the first cell buffer and outputting the ATM cell of the second cell buffer The process includes the steps.

In a preferred embodiment of this aspect, the CDP setting step, when the loss priority bit of the ATM cell is '0', the delay priority bit of the ATM cell to '1', the loss priority of the ATM cell If the priority bit is '1', setting the delay priority bit of the ATM cell to '0';

In a preferred embodiment of the present invention, after the delay priority detection of each ATM cell, the step of sequentially storing the ATM cells in a corresponding buffer includes: when the cell delay priority bit is '1', And storing in the one cell buffer, and in the second cell buffer when the cell delay priority bit is '0'.

The present invention relates to an ATM switching device and a switching method using parallel CDP detection, and simultaneously latches a plurality of input buffers for temporarily storing ATM cells input from the outside and CDP bits of ATM cells stored in the input buffer. A parallel CDP detector for separating and outputting a delay priority ATM cell and a loss priority ATM cell, a first cell buffer for receiving and storing a loss priority ATM cell from the parallel CDP detector, and storing data in the first cell buffer A full signal detector for outputting a predetermined control signal to the parallel CDP detector so as to temporarily stop the data input of the first cell buffer if it is determined that the data has been stored. A second cell buffer for receiving and storing a second cell and an ATM cell stored in the first and second cell buffers based on a predetermined order. An output cell selection switch for selectively outputting the number of delay priority ATM cells output from the second cell buffer, and when the number is greater than or equal to a predetermined setting value, the first cell buffer data is smaller than the predetermined setting value. A counter for controlling the output cell selection switch, and an output buffer for receiving data from and outputting data from any one of the first and second cell buffers to process the CLP detection in parallel. In addition, the size of the input buffer can be used appropriately, and the input ATM cell can be prevented from being lost due to the full state of the input buffer.

3 is a diagram showing the structure of an ATM cell according to the present invention.

As shown in Fig. 3, the ATM cell includes an ATM cell header 904 having a CLP bit indicating whether or not the loss priority cell is present, ATM cell data 906 having substantial data information, and an external device. And a CDP detection bit 902 that is set to either '1' or '0' according to the CLP bit detection result in the ATM cell header 904 by the microprocessor.

This is the sum of the ATM cell header 904 and ATM cell data 906 is 53 bytes, in which the CDP detection bit 902 for ATM cell processing is added as a dummy bit.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 to 4.

2 is a diagram illustrating an ATM switching apparatus using parallel CDP detection according to an embodiment of the present invention.

4 is a flowchart illustrating an ATM switching method using parallel CDP detection according to another embodiment of the present invention.

Referring to FIG. 4, an ATM switching method using a parallel CDP detection method is as follows.

First, ATM cells input from the outside are stored in the plurality of input buffers 100-1100 -N, respectively (S10).

As shown in FIG. 2, the input buffer 100-1100 -N temporarily receives N ATM cells from the outside through an ATM cell input link 50-150 -N and temporarily stores them. The ATM cell, which is inputted as, is buffered to be output in sync.

Next, the loss priority (CLP) bit of each ATM cell is detected, and the CDP bit of each ATM cell corresponding thereto is set to one of '1' and '0' (S20). That is, when the loss priority (CLP) bit of the ATM cell is '0', the delay priority (CDP) bit of the ATM cell is set to '1', and the loss priority (CLP) bit of the ATM cell is set. Is 1, the delay priority (CDP) bit of the ATM cell is set to '0'.

The ATM cells are simultaneously input to the parallel CDP detector 200 (S30).

As shown in FIG. 2, the parallel CDP detector 200 simultaneously latches the CDP bits of the ATM cell stored in the input buffer 100-1100 -N, so that the delay priority ( CDP) separates the loss priority (CLP) ATM cell with the bit '1' and the delay priority (CDP) ATM cell with the delay priority (CDP) bit '0' and outputs them sequentially.

Subsequently, after detecting the CDP of each ATM cell, the ATM cells are sequentially added to corresponding buffers among the first and second cell buffers 300 and 500 having a first-in first-out (FIFO) structure according to the value. Save to (S40). That is, as shown in FIG. 2, when the cell delay priority (CDP) bit is '1', the cell delay priority (CDP) bit is stored in the first cell buffer 300, and the cell delay priority (CDP) bit is '0'. If it is, it is stored in the second cell buffer 500.

At this time, the full signal detector 400 determines whether the first cell buffer 300 is full (S50).

As shown in FIG. 2, the full signal detector 400 detects whether all of the data is stored in the first cell buffer 300 and, if all of the data is stored, inputs the data input of the first cell buffer 300. A predetermined control signal is output to the parallel CDP detector 200 to temporarily stop. This is to prevent the loss of the loss priority ATM cell input when all data is stored in the first cell buffer 300.

If all of the first cell buffer 300 is not filled in the step S50, the ATM cell of the second cell buffer 500 is output (S60).

Next, as shown in FIG. 2, the counter 700 determines whether the output count of the ATM cell of the second cell buffer 500 is greater than or equal to a predetermined setting value, and thus, the second cell buffer 500. If the output count of the ATM cell is less than the set value, the process returns to step S60 of outputting the ATM cell of the second cell buffer 500 (S70).

The counter 700 counts the number of delay priority (CDP) ATM cells output from the second cell buffer 500, when the first cell buffer 300 data is greater than or equal to a predetermined value. The output cell selection switch 600 is controlled to be output through the output buffer 800 by a number smaller than a predetermined set value. For example, when the set value is '5', when the number of output ATM cells of the second cell buffer 500 becomes '5', the output cell selection switch 600 is controlled to control the first cell buffer. The number of output ATM cells of 300 is '1', and the operation is repeatedly performed.

The output buffer 800 receives data from one cell buffer among the first and second cell buffers 300 and 500 and outputs the data through one ATM cell output link 60.

However, when the first cell buffer 300 is completely filled with the ATM cell in the determining step S50 and when the output count of the ATM cell is greater than or equal to a set value in the step S70, the first cell buffer 300 The ATM cell of the second cell buffer 500 is output, and the process returns to step S60 of outputting the ATM cell of the second cell buffer 500 (S80).

The present invention solves the problem of loss of data due to the full state of the input buffer when there are many input ATM cells, as the conventional ATM switching apparatus detects one CLP bit of each ATM cell in a serial manner. By detecting the CDP bits of each ATM cell set according to the CLP bit detection result in parallel, the size of the input buffer can be used appropriately, and the effect of preventing the input ATM cell from being lost due to the full state of the input buffer can be prevented. have.

Claims (8)

In an ATM switching device, A plurality of input buffers 100-1100-N for temporarily storing ATM cells input from the outside; A parallel CDP detector (200) for simultaneously latching the CDP bits of the ATM cells stored in the input buffer (100-1100-N) to separate and output a delay priority ATM cell and a loss priority ATM cell; A first cell buffer (300) for receiving and storing the loss priority ATM cell from the parallel CDP detector (200); The control unit detects whether all the data has been stored in the first cell buffer 300, and if it is determined that all data has been stored, outputs a predetermined control signal to the parallel CDP to temporarily stop data input of the first cell buffer 300. A full signal detector 400 output to the detector 200; A second cell buffer (500) for receiving and storing the delay priority ATM cell from the parallel CDP detector (200); An output cell select switch (600) for selectively outputting the ATM cells stored in the first and second cell buffers (300, 500) based on a predetermined order; When the number of delay priority ATM cells output from the second cell buffer 500 is counted to be equal to or greater than a predetermined setting value, the first cell buffer 300 data is smaller than the predetermined setting value. A counter 700 for controlling the output cell selection switch 600 to be output; And an output buffer (800) for receiving and outputting data from any one of the first and second cell buffers (300, 500). The method of claim 1, The ATM cell includes an ATM cell data (906), an ATM cell header (904), and predetermined CDP detection bits (902). The method of claim 2, The ATM cell header (904) includes a CLP bit indicating whether or not the loss-priority ATM cell. The method of claim 2, The CDP detection bit 902 is set to one of a delay priority bit and a loss priority bit according to a result of detecting the CLP bit in the ATM cell header 904 by an external device. ATM switching device. The method of claim 1, And the first and second cell buffers (300, 500) are buffers of a first-in, first-out structure. A plurality of cell input buffers (100-1100-N), a parallel CDP detector (200), a first cell buffer (300) storing loss priority ATM cells, a second cell buffer (500) storing delay priority ATM cells In the switching method of the ATM switching apparatus using a parallel CDP detection method including a full signal detector 400, a cell selection switch 600, a counter 700, an output buffer 800, Storing ATM cells from the outside in the plurality of input buffers (100-1100-N) (S10); Detecting a loss priority (CLP) bit of each ATM cell and setting a delay priority (CDP) bit of the corresponding ATM cell to any one of '1' and '0'; Simultaneously inputting the set ATM cells to the parallel CDP detector (200) (S30); (S40) sequentially storing the ATM cells in a corresponding one of the first and second cell buffers (300, 500) after detecting a delay priority (CDP) bit of each ATM cell; Determining whether the first cell buffer 300 is full (S50); Outputting an ATM cell of the second cell buffer (500) when all of the first cell buffer (300) is not filled in the step (S50); It is determined whether the output count of the ATM cell of the second cell buffer 500 is greater than or equal to a predetermined setting value, and when the output count of the ATM cell of the second cell buffer 500 is less than a predetermined value, the second cell buffer Returning to step S60 of outputting an ATM cell of step 500; When the first cell buffer 300 is completely filled with the ATM cell in step S50 and when the output count of the ATM cell is greater than or equal to a set value in step S70, the ATM of the first cell buffer 300 And outputting a cell and returning (S80) to outputting (S60) the ATM cell of the second cell buffer (500). The method of claim 6, In the CDP setting step (S20), when the loss priority (CLP) bit of the ATM cell is '0', the delay priority (CDP) bit of the ATM cell is set to '1', and the loss priority of the ATM cell is set. And if the priority (CLP) bit is '1', setting the delay priority (CDP) bit of the ATM cell to '0'. The method of claim 6, After the delay priority (CDP) of each ATM cell is detected, the step of sequentially storing the ATM cells in a corresponding buffer (S40) may include the first if the cell delay priority (CDP) bit is '1'. Storing in the cell buffer 300, and storing the cell delay priority (CDP) bit in the second cell buffer 500 when the cell delay priority (CDP) bit is '0'. ATM switching method.