KR100189550B1 - Device and method of memory data input/output - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Memory data input / output device and method

2. The technical problem to be solved by the invention

Even if the input / output terminal of the IC is composed of multiple bits, it is possible to detect and correct errors using one bit error correction code.If the error correction coding does not have a general data bus width, the data bus width is converted to the general data bus width. The present invention provides a memory data input / output device and a method for adjusting the error, and even if the bad memory in which an error occurs at the same time, the error is easily distributed by appropriately distributing the error so that the memory can operate at almost the same level as the normal memory.

3. Summary of Solution to Invention

The memory data input / output device includes a memory having two or more data terminals simultaneously input and output, a buffer consisting of predetermined rows and columns, for outputting data to or inputting data from the memory, and a predetermined error correction code in the buffer. Reads in the column direction and outputs the data to the memory after inputting a plurality of rows in the row direction, and reads the data output from the memory in the column direction and outputs the data to the buffer in the row direction. And control means for controlling the operation of distributing as an error correction code.

4. Important uses of the invention

Used to control memory input and output.

Description

Memory data input / output device and control method thereof

1 is a block diagram showing a conventional memory data storage state

2 is a block diagram of an m-row x n-column buffer added to a memory entry and exit in accordance with the present invention.

3 is a diagram showing a state in which data is stored in each device when the input / output terminal is 4 bits per device.

4 is a schematic diagram of any one cell and peripheral circuit of the buffer according to the present invention.

5 is a flowchart illustrating a process of inputting a hamming codeword to an auxiliary memory through a buffer according to the present invention.

* Explanation of symbols for main parts of the drawings

FF: Deflip-flop G1, G2: Endgate

G3, G4: Oagate BF1, BF2: Buffer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for inputting and outputting data to and from a semiconductor memory device, and more particularly, to an apparatus for inputting and outputting data to which an error correction code is added for error detection and correction, and a control method thereof.

Generally, there are many types of semiconductor memory devices that can store digital data, such as DRAM, SRAM, ROM, and flash memory. Data can be input / output from the data input / output terminal by the signal and the address signal. The device dedicated to output can only output data from the data output terminal. However, even if it is an output-only device, data must be input through a process called programming. Therefore, the input / output process of data is necessary whether the device is an input / output device or an output-only device.

No matter which of the above devices is used, if it is a bad device, a cell will be partially inoperable in the memory device, causing a data error. In order to prevent such an error, an error correction code is added to the data to correct the error when an error occurs.

However, conventionally, since the data input and output of the memory IC device mainly used a single bit, the error was distributed based on each address even when an error occurred. However, the number of additional bits of the error correction code has been reduced. Due to the tendency to make multiple errors, multiple bits of error occur at the same time, and the number of additional bits of the error correction code has to be increased. In this case, not only the additional bits increase, but also the complexity of the control circuit and the increase in the processing time and the increase in the software program are combined. That is, when the input / output stage is composed of x4 (4 bits), x8 (8 bits), x16 (16 bits), x32 (32 bits), etc., the probability of multiple errors is much higher than that of x1 (1 bit). Processing is necessary.

In other words, for example, in a memory device that inputs and outputs word by word (16 bits) to one memory access, if each input / output terminal of the IC has one bit, data is obtained from 16 ICs one bit each time the data is accessed. The probability that a bit is an error is independent. At the same time, the probability of two, three, or four bit errors decreases exponentially. Therefore, if the probability of one bit error is about the error rate allowed by the device, the error probability for more than two bits can be ignored, so the error correction code may be designed for only one bit error.

However, if each input / output terminal of the IC has four bits (x4), four bits of data are obtained from four ICs each time they are accessed. This is very high. So the error correction code should be designed for four bit errors.

In addition, if the input / output stage is 8 bit or 16 bit, the error correction code should be designed accordingly. When the number of expected occurrence errors increases to 1, 4, 8, 16, 32, parity is added to the original data accordingly. The number of bits increases exponentially, not arithmetic.

As a result, in terms of the amount of data, it may be desirable to employ a one-bit error correction code to satisfy the error rate allowed by the device.

Another problem is that if the number of bits of error-correction coded data is not in bytes (8 bits), the system has a data bus width that applies only to the device, rather than to the general-purpose memory structure of the byte unit. In other words, for example, when (7, 4) Hamming Code is adopted as an error correction code, the width of the data bus should be 7 bits instead of the usual 8 bits or 16 bits.

Accordingly, it is an object of the present invention to provide a memory input / output device and a method of controlling the same, capable of detecting and correcting a single bit error even when the input / output terminal of the IC is composed of several bits.

Another object of the present invention is to provide a memory input / output device and a control method for adjusting the data bus width to a general data bus width when the error correction coding does not have a general data bus width.

Another object of the present invention is to provide a memory data input / output device and a method of controlling the same, in which errors are easily distributed by appropriately distributing them when errors occur simultaneously.

The memory data input / output device for achieving the above object includes a memory having two or more data terminals simultaneously input and output, a buffer consisting of predetermined rows and columns, for outputting data to or inputting data from the memory; Inputs a plurality of predetermined error correction codes into a buffer in a row direction, reads them in a column direction, and outputs them to the memory, and inputs data output from the memory in a column direction and reads them in a row direction to output to the buffer, And control means for controlling an operation of distributing an error occurring in the memory as each error correction code.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In addition, in the following description, many specific details such as components of specific circuits are shown, which are provided to help a more comprehensive understanding of the present invention, and the present invention may be practiced without these specific details. It will be obvious to those of ordinary skill in Esau. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

In this embodiment, 8 bits are possible by adjusting the width of the data bus through the buffer.

FIG. 2 is a configuration diagram of an m-row x n-column buffer added to an input / output terminal of a memory according to the present invention, and includes 56 cells, and each cell may be implemented as a single flip-flop. m corresponds to the length of the code length of the error correction code employed, and n means the maximum number of bits when accessing the memory system. In other words, if the error correction code employed in a system is a (7, 4) hamming code and the memory system has 8-bit and 16-bit access, then m = 16 and n = 7 (m = 8, n in Figure 2). = 7).

According to FIG. 2, when error correcting coded data is inputted through the buffer into the memory, the error correcting coded data is once inputted into the buffer {1A, 1B, 1C, ..., 1G}, 2 rows {2A]. , 2B, 2C, ..., 2G}, 3 rows, ..., 8 rows, if 8 rows are entered, address 0 to 1 column 1 byte from the buffer into memory from the buffer {1A, 2A , (3,1), ..., 8A}, 2 columns {1B, 2A, (3,2), ..., 8B}, 3 columns, ..., 7 columns Complete the input.

FIG. 3 shows that data is stored in each device in the case of a memory having input / output terminals having 4 bits per device. After completing the data input for one element by the method as shown in FIG. 2, the error correction coded data is again stored in the first, second, third, ..., eighth row of the buffer. If it is inputted in order, and up to 8 lines, it inputs 1 column, 2 columns, 3 columns, ..., 7 columns into the memory from the buffer in the order of 1 byte to complete the next 7 bytes and total 14 bytes. Complete the input. Data is input up to address 13. Subsequent data entry also completes the entry of the necessary data through the above-described process.

When the error-corrected coded data is output from the memory through the buffer, the data from the memory is output from address 0 in a byte unit to the buffer so that one row {1A, 2A, (3,1), ..., 1G}, 2 lines {2A, 2B, 2C, ..., 2G}, 3 lines, ..., 8 lines are output in this order. As a result, data is processed in 7x8 = 56 bit units.

4 shows any one cell constituting the buffer according to the present invention and its peripheral circuit, which is composed of a deflip-flop FF and an AND gates G1 and G2, an oragate G3 and G4, and buffers BF1 and BF2. First and second buffer inputs BF _m and BF _n are connected to one terminal of the AND gates G1 and G2, respectively, and first and second buffer input control signals IC1 and IC2 are respectively input to the other terminal. The first and second buffer input control signals IC1 and IC2 are input to the oragate G4. The output signals of the AND gates G1 and G2 are input to the oragate G3. The data input terminal of the flip-flop FF is input to the output signal of the oragate G3 to D, and the output signal of the orifice G4 is input to the clock terminal CLK. Input terminals of the buffers BF1 and BF2 are connected to the data output terminal OUT of the flip-flop FF, and the buffers BF1 and BF2 operate under the control of the first and second buffer output control signals OC1 and OC2.

Although only one cell is shown in FIG. 4, each cell has the same structure. Therefore, not all the flip-flops and control signals for each row and column are shown, but for convenience of description, the first buffer input control signal ICm is a row, and the second buffer input control signal ICn is representative of the signals for the column. IC1A to IC8G Explain separately. The same applies to the first and second buffer output control signals OCm and OCn. The first and second buffer inputs are also classified into BFm and BFn, where m represents A to G of the row and n represents 1 to 8 of the column. The flip-flop is also described by dividing it by FFmn.

If the first buffer input control signal IC1n corresponding to one row is 1, {1A, 1B, 1C, ..., 1G} are enabled and 7-bit data is input to the buffer in the row direction. At this time, the second buffer input control signal IC2 is zero.

Similarly, if the first buffer input control signal IC2n corresponding to two rows is 1, {2A, 2B, 2C, ..., 2G} will be enabled so that 7 bits of data will be input to the buffer in the row direction, and the remaining rows The same also works.

On the other hand, when the second buffer input control signal IC2 corresponding to one column is 1, {1A, 2A, 3A, ..., 8A} are enabled so that one byte of data is stored in the buffer in the auxiliary memory (not shown). Direction is input. At this time, the first buffer input control signal IC1 is zero. Do the same for the other columns.

The same operation is also performed when outputting data of each row and column of the buffer according to the states of the first and second buffer output control signals 0Cm and 0Cn. m shall be A-G, n shall represent 1-8 of heat | fever. The flip-flop is also represented by FFmn.

On the other hand, the operation of inputting data into the auxiliary memory via the buffer from the CPU or other equipment is performed as follows.

7-bit data bus, i.e., data is loaded on the buffer inputs BF ₁ to BF ₇ , and 7-bit data is input to the flip-flop FF 1A to 17 with the first buffer input control signal IC1 as 1, and then the first buffer input control signal. Set IC1 to 0. Thereafter, data is loaded on the buffer inputs BF ₁ to BF ₇ again and 7 bits of data are input to the flip-flop FF 21 to 27 using the second buffer input control signal IC2 as 1, and then the second buffer input control signal IC2 is set to 0. Shall be. At this time, the other buffer input / output control signal is zero. Repeat this operation to complete the input up to {8A, 8B, 8C, ..., 8G}.

Next, when the first buffer output control signal OC1 is set to 1, data of the def flip-flop FF 1A to 8A is loaded on the data bus connected to the memory, and 1 byte is input to the memory, and then the first buffer output control signal OC1 is set to 0. do.

When the second buffer output control signal OC2 is set to 1 again, the data of the de-flop flops FF 1B to 8B is loaded on the data bus connected to the memory, and 1 byte is input to the memory, and then the second buffer output control signal OC2 is set to 0. This operation is repeated to complete the input up to {1G, 2G, 3G, ..., 8G}.

The operation of outputting data from the auxiliary memory to the CPU or other device via the buffer may be performed in the reverse of the above process.

FIG. 5 is a flowchart illustrating a process of inputting eight Hamming codewords to the auxiliary memory through a buffer consisting of eight bytes each, according to the present invention, where BASE_BUF represents the starting number of the set buffer, and [BASE_BUF] BASE_BUF represents the contents, [BASE_BUF + m] represents the contents m bytes after BASE-BUF, BASE_MEM represents the start address of the auxiliary memory, and H1, ..., H8 represent eight Hamming codewords.

Step 5a is a step of inputting eight Hamming codes into the buffer. In step 5b, since BASE_BUF,..., And BASE_BUF + 7 are configured in byte units, a step of 1 bit shift is performed for dummy processing. Steps 5c and 5d are for setting the number of loops. In step 5e, 1A to 1G stored in BASE_BUF are shifted, and 1A is input to the flag bit. This is usually because the CPU stores shifted bits in flag bits when shifting. For example, the Intel 80 series carries a carry flag, while the Motorola 68 series carries a carry bit and an x flag.

In step 5f, if the flag bit inputted in step 5e is rotated, 1A is input to the temporary variable TEMP of one byte. In steps 5g and 5h, 8A, 7A, ..., 1A are input by repeating the processes 5e to 5h eight times by checking whether the preset number of loops is exceeded.

In step 5i, enter TEMP in the auxiliary memory. Steps 5j and 5k are operation processes for completing the input from the buffer to the memory by repeating the above operation up to seven times.

Comparing the same input / output method with the first embodiment, in case of FIG. 1, if an error occurs in address 3 of the first memory device, the 4 bit of 4D, 4E, 4F, and 4G are all due to the nature of data stored in the same device. The probability of error is very high, and most of the error occurs more than 2 bits if not all 4 bits. In this case, more than one error occurs among 7 bits of {4A, 4B, 4C, 4D, 4E, 4F, 4G}, which constitute one codeword of the (7, 4) hamming code. The error correction capability exceeds the limit of the 1-bit (7, 4) hamming code, making it impossible to correct the error. In addition, since one codeword length of a code is 7 bits, it is a waste to a memory device having a data bus width of a multiple of a general byte. As described above, although 1 bit of waste occurs in the conventional method, the present embodiment can eliminate waste as follows for the same error.

{4D, 3D, 2D, 1D} Assuming that an error occurs in all 4 bits, when this data is output through the buffer, it is distributed in 4 codewords of the next Hamming code.

{1A, 1B, 1C, 1D, 1E, 1F, 1G}

{2A, 2B, 2C, 2D, 2E, 2F, 2G}

{3A, 3B, 3C, 3D, 3E, 3F, 3G}

{4A, 4B, 4C, 4D, 4E, 4F, 4G}

The number of errors generated in each codeword is 1 bit due to the variance of the error, and the correcting ability of the Hamming code is 1 bit. Therefore, all the generated errors can be corrected to restore the original data. Also, if the number of rows in the buffer matches the memory data bus width, there is no waste of storage space.

This embodiment is useful when a large amount of image or audio data is inputted and stored.

As described above, the present invention can efficiently detect and correct errors using one bit error correction code even when the input / output terminal of the IC is composed of several bits, and is effective as a buffer when the error correction encoding does not have a general data bus width. By adjusting the data bus width to the general data bus width, it can be used as it is in a general-purpose memory device, and even if the bad memory where an error occurs several bits at the same time, the error is easily distributed by appropriately distributing the errors so that it is almost similar to the normal memory. It has the advantage of working at the level.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.

Claims (4)

A memory input / output device for inputting and outputting data, comprising: a memory having two or more data terminals input and output at the same time; a buffer configured to output data to or output data from the memory; After inputting a large number of predetermined error correction codes in the row direction, the input error correction codes are read in the column direction and output to the memory. The data output from the memory is input in the column direction and then read in the row direction and output to the buffer. And control means for controlling to distribute the error occurring in the memory as each error correcting code. The memory data input / output device according to claim 1, wherein a length of a row in the buffer is a multiple of bytes. A memory input / output control method for a memory data input / output device having a memory having two or more data terminals simultaneously input and output, and a buffer configured to output data to or input data from the memory, the buffer comprising: a plurality of rows and columns; A first process of inputting a plurality of predetermined error correction codes in a row direction to read in a column direction and outputting the data to the memory, and inputting data output from the memory in a column direction and reading in a row direction to the buffer In the second process, if the amount of all data is checked not to be a multiple of the buffer size, and if the last input data does not fill the buffer completely, the additional parity bit for the zero data string of the error correction code is zero data string. , The third to fill the rest of the buffer with zeros. Memory data input and output control method characterized in that consisting of a process. A memory input / output control method for a memory input / output device having a memory having two or more data terminals simultaneously input and output, and a buffer configured to output data to or input data from the memory, the memory input / output device having a predetermined row and column. A first process of inputting a plurality of predetermined error correction codes in a row direction and reading them in a column direction, and outputting the data output from the memory in a column direction and reading them in a row direction to the buffer; Process 2, if the amount of all data is not a multiple of the buffer size, and if the last input data has not been filled completely, the additional parity bit for one data string of the error correction code is one data string. In the third process, filling the rest of the buffer with 1s Memory output control method for a load characterized luer.